Vm-dev February 2022

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VM Maker: VMMaker.oscog-nice.3170.mcz
by commits＠source.squeak.org 24 Feb '22

24 Feb '22

Nicolas Cellier uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-nice.3170.mcz ==================== Summary ==================== Name: VMMaker.oscog-nice.3170 Author: nice Time: 24 February 2022, 2:48:39.990237 pm UUID: 6b851cd8-b485-1047-acfd-8adee37e3660 Ancestors: VMMaker.oscog-nice.3169 Revise the 3 new BitBlt rules again (see https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/505) - use a proper division by 255 (factor alpha/255) in alphaScale:with: instead of approximate factor alpha/256 previously - use a proper rounding (by adding 16r80 before the division by 255) in alphaScale:with: - split the unscale ops in 3 separate r/g/b channels, otherwise, when grouping rb, the division by alpha will leak red bits not only on green components but also on blue - fixup the carry used for saturating the rbg components in case of 16rFF overflow in alphaUnscale:with: Note: division by 255 can be checked thru this snippet (should answer 0): (0 to: 16rFF squared) inject: 0 into: [:max :num | | rat | rat := num + 16r80. "+ 16r80 for rounding" rat := rat + (rat - 1 >> 8 bitAnd: 16rFF) >> 8 bitAnd: 16rFF. "divide by 255" ((num/255) rounded - rat) abs max: max]. =============== Diff against VMMaker.oscog-nice.3169 =============== Item was changed: ----- Method: BitBltSimulation>>alphaBlendUnscaled:with: (in category 'combination rules') ----- alphaBlendUnscaled: sourceWord with: destinationWord "Blend sourceWord with destinationWord using the alpha value from both sourceWord and destinationWord. Alpha is encoded as 0 meaning 0.0, and 255 meaning 1.0. The alpha channel and color produced are srcAlpha + (destAlpha*(1-srcAlpha)) (srcAlpha*srcColor + (destAlpha*(1-srcAlpha)*dstColor)) / (srcAlpha + (destAlpha*(1-srcAlpha))) In contrast to alphaBlend:with: the method does not assume that destination form is opaque. In contrast to alphaBlendScaled:with: the method does not assume that colors have been pre-scaled (muliplied) by alpha channel." + | alpha blendA result blendR blendB blendG | - | alpha blendA result blendRB blendG | <inline: false> <returnTypeC: 'unsigned int'> <var: 'sourceWord' type: #'unsigned int'> <var: 'destinationWord' type: #'unsigned int'> + <var: 'blendA' type: #'unsigned int'> + <var: 'blendR' type: #'unsigned int'> - <var: 'blendRB' type: #'unsigned int'> <var: 'blendG' type: #'unsigned int'> + <var: 'blendB' type: #'unsigned int'> <var: 'result' type: #'unsigned int'> <var: 'alpha' type: #'unsigned int'> - <var: 'blendA' type: #'unsigned int'> alpha := sourceWord >> 24. "High 8 bits of source pixel, assuming ARGB encoding" alpha = 0 ifTrue: [ ^ destinationWord ]. alpha = 255 ifTrue: [ ^ sourceWord ]. + blendA := 16rFF * alpha + (16rFF - alpha * (destinationWord >> 24)) + 16r80. "blend alpha channels" - blendA := 16rFF * alpha + (16rFF - alpha * (destinationWord >> 24)) + 16rFF. "blend alpha channels" blendA := blendA + (blendA - 1 >> 8 bitAnd: 16rFF) >> 8 bitAnd: 16rFF. "divide by 255" + blendR := ((sourceWord bitAnd: 16rFF0000) * alpha) + + ((destinationWord bitAnd: 16rFF0000) * (blendA-alpha)) + +(blendA<<15) + // blendA bitAnd: 16rFF0000. "blend red" + - blendRB := ((sourceWord bitAnd: 16rFF00FF) * alpha) + - ((destinationWord bitAnd: 16rFF00FF) * (blendA-alpha)) - / blendA bitAnd: 16rFF00FF. "blend red and blue" - blendG := ((sourceWord bitAnd: 16r00FF00) * alpha) + ((destinationWord bitAnd: 16r00FF00) * (blendA-alpha)) + +(blendA<<7) + // blendA bitAnd: 16r00FF00. "blend green" + + blendB := ((sourceWord bitAnd: 16r0000FF) * alpha) + + ((destinationWord bitAnd: 16r0000FF) * (blendA-alpha)) + +(blendA>>1) + // blendA bitAnd: 16r0000FF. "blend blue" + + result := ((blendR bitOr: blendB) bitOr: blendG) bitOr: blendA << 24. - / blendA bitAnd: 16r00FF00. "blend green" - result := (blendRB bitOr: blendG) bitOr: blendA << 24. ^ result ! Item was changed: ----- Method: BitBltSimulation>>alphaScale:with: (in category 'combination rules') ----- alphaScale: sourceWord with: destinationWord "Scale (premultiply) the destination with its alpha channel. Note that sourceWord is ignored." | alpha rb g | <inline: false> "Do NOT inline this into optimized loops" <returnTypeC: 'unsigned int'> <var: 'sourceWord' type: #'unsigned int'> <var: 'destinationWord' type: #'unsigned int'> <var: 'rb' type: #'unsigned int'> <var: 'g' type: #'unsigned int'> <var: 'alpha' type: #'unsigned int'> alpha := destinationWord >> 24. "High 8 bits is opacity (ARGB format)" + rb := (destinationWord bitAnd: 16rFF00FF) * alpha + 16r800080. "scale red and blue components" + rb := rb + (rb - 16r010001 >> 8 bitAnd: 16rFF00FF) >> 8 bitAnd: 16rFF00FF. "divide by 255" + g := (destinationWord bitAnd: 16r00FF00) * alpha + 16r008000. "scale green component" + g := g + (g - 16r000100 >> 8 bitAnd: 16r00FF00) >> 8 bitAnd: 16r00FF00. "divide by 255" - rb := ((destinationWord bitAnd: 16rFF00FF) * alpha >> 8 bitAnd: 16rFF00FF). "scale red and blue components" - g := ((destinationWord bitAnd: 16r00FF00) * alpha >> 8 bitAnd: 16r00FF00). "scale green component" ^(g bitOr: rb) bitOr: (destinationWord bitAnd: 16rFF000000) "recompose"! Item was changed: ----- Method: BitBltSimulation>>alphaUnscale:with: (in category 'combination rules') ----- alphaUnscale: sourceWord with: destinationWord "Unscale (divide) the destination with its alpha channel. Note that sourceWord is ignored." + | alpha r b g rgb carry | - | alpha rb g rgb carry | <inline: false> "Do NOT inline this into optimized loops" <returnTypeC: 'unsigned int'> <var: 'sourceWord' type: #'unsigned int'> <var: 'destinationWord' type: #'unsigned int'> + <var: 'r' type: #'unsigned int'> - <var: 'rb' type: #'unsigned int'> <var: 'g' type: #'unsigned int'> + <var: 'b' type: #'unsigned int'> <var: 'rgb' type: #'unsigned int'> <var: 'alpha' type: #'unsigned int'> <var: 'carry' type: #'unsigned int'> alpha := destinationWord >> 24. "High 8 bits is opacity (ARGB format)" alpha = 0 ifTrue: [^0]. + r := (destinationWord bitAnd: 16rFF0000) * 255 + (alpha+1<<15) // alpha. "unscale red components" + g := (destinationWord bitAnd: 16r00FF00) * 255 + (alpha+1<<7) // alpha. "unscale green component" + b := (destinationWord bitAnd: 16r0000FF) * 255 + (alpha+1>>1) // alpha. "unscale blue components" + carry := (((r bitAnd: 16rFF000000) bitOr: (g bitAnd: 16rFF0000)) bitOr: (b bitAnd: 16rFF00)) >> 8. + carry := carry bitOr: ((carry bitAnd: 16rAAAAAA) >> 1 bitOr: (carry bitAnd: 16r555555) << 1). + carry := carry bitOr: ((carry bitAnd: 16rCCCCCC) >> 2 bitOr: (carry bitAnd: 16r333333) << 2). + carry := carry bitOr: ((carry bitAnd: 16rF0F0F0) >> 4 bitOr: (carry bitAnd: 16r0F0F0F) << 4). + rgb := ((r bitAnd: 16rFF0000) bitOr: (g bitAnd: 16r00FF00)) bitOr: (b bitAnd: 16r0000FF). - rb := (destinationWord bitAnd: 16rFF00FF) << 8 / alpha. "unscale red and blue components" - g := (destinationWord bitAnd: 16r00FF00) / alpha. "unscale green component" - carry := ((rb >> 8 bitAnd: 16rAA00AA) >> 1 bitOr: (rb >> 8 bitAnd: 16r550055) << 1) - bitOr: ((g bitAnd: 16r00AA00) >> 1 bitOr: (g bitAnd: 16r005500) << 1). - carry := (carry bitAnd: 16rCCCCCC) >> 2 bitOr: (carry bitAnd: 16r333333) << 2. - carry := (carry bitAnd: 16rF0F0F0) >> 4 bitOr: (carry bitAnd: 16r0F0F0F) << 4. - rgb := (rb bitAnd: 16rFF00FF) bitOr: (g << 8 bitAnd: 16r00FF00). rgb := rgb bitOr: carry. "saturate RGB components if division overflows" ^rgb bitOr: (destinationWord bitAnd: 16rFF000000) "restore alpha"!

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[OpenSmalltalk/opensmalltalk-vm] 59ed59: Pin GHA for Windows builds to "windows-2019" platf...
by Marcel Taeumel 24 Feb '22

24 Feb '22

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 59ed5999dec92ec4e37b1982bb9acb7b8988057a https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/59ed5999dec92ec4e3… Author: Marcel Taeumel <marcel.taeumel(a)hpi.de> Date: 2022-02-24 (Thu, 24 Feb 2022) Changed paths: M .github/workflows/extra.yml M .github/workflows/win.yml Log Message: ----------- Pin GHA for Windows builds to "windows-2019" platform since "windows-latest" recently changed to "windows-2022", which did some incompatible things to the MSYS installation.

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VM Maker: VMMaker.oscog-nice.3169.mcz
by commits＠source.squeak.org 24 Feb '22

24 Feb '22

Nicolas Cellier uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-nice.3169.mcz ==================== Summary ==================== Name: VMMaker.oscog-nice.3169 Author: nice Time: 24 February 2022, 1:53:42.760293 am UUID: e2ca1296-dc0c-418e-b1ac-7def7ff9a33d Ancestors: VMMaker.oscog-eem.3168 Fix alphaBlendUnscaled some bits were leaking in the neighbour color. =============== Diff against VMMaker.oscog-eem.3168 =============== Item was changed: ----- Method: BitBltSimulation>>alphaBlendUnscaled:with: (in category 'combination rules') ----- alphaBlendUnscaled: sourceWord with: destinationWord "Blend sourceWord with destinationWord using the alpha value from both sourceWord and destinationWord. Alpha is encoded as 0 meaning 0.0, and 255 meaning 1.0. The alpha channel and color produced are srcAlpha + (destAlpha*(1-srcAlpha)) (srcAlpha*srcColor + (destAlpha*(1-srcAlpha)*dstColor)) / (srcAlpha + (destAlpha*(1-srcAlpha))) In contrast to alphaBlend:with: the method does not assume that destination form is opaque. In contrast to alphaBlendScaled:with: the method does not assume that colors have been pre-scaled (muliplied) by alpha channel." | alpha blendA result blendRB blendG | <inline: false> <returnTypeC: 'unsigned int'> <var: 'sourceWord' type: #'unsigned int'> <var: 'destinationWord' type: #'unsigned int'> <var: 'blendRB' type: #'unsigned int'> <var: 'blendG' type: #'unsigned int'> <var: 'result' type: #'unsigned int'> <var: 'alpha' type: #'unsigned int'> <var: 'blendA' type: #'unsigned int'> alpha := sourceWord >> 24. "High 8 bits of source pixel, assuming ARGB encoding" alpha = 0 ifTrue: [ ^ destinationWord ]. alpha = 255 ifTrue: [ ^ sourceWord ]. blendA := 16rFF * alpha + (16rFF - alpha * (destinationWord >> 24)) + 16rFF. "blend alpha channels" blendA := blendA + (blendA - 1 >> 8 bitAnd: 16rFF) >> 8 bitAnd: 16rFF. "divide by 255" blendRB := ((sourceWord bitAnd: 16rFF00FF) * alpha) + ((destinationWord bitAnd: 16rFF00FF) * (blendA-alpha)) + / blendA bitAnd: 16rFF00FF. "blend red and blue" - / blendA. "blend red and blue" blendG := ((sourceWord bitAnd: 16r00FF00) * alpha) + ((destinationWord bitAnd: 16r00FF00) * (blendA-alpha)) + / blendA bitAnd: 16r00FF00. "blend green" - / blendA. "blend green" result := (blendRB bitOr: blendG) bitOr: blendA << 24. ^ result !

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disabling epoll (temporarily)
by Eliot Miranda 23 Feb '22

23 Feb '22

Hi All, we're debugging an issue with a VNC session on a 64-bit x86_64 linux virtual machine. To do this I want to turn off epoll support via platforms/unix/conf/configure but e.g. --disable-EPOLL does nothing. Is there any chance we can have such a feature in the configure? Editing config.h is a PITA. _,,,^..^,,,_ best, Eliot

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[OpenSmalltalk/opensmalltalk-vm] 9b418c: [unix] add configure option to disable epoll
by Tobias Pape 23 Feb '22

23 Feb '22

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 9b418c904b175141c8d915220fbb7504b97087b4 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/9b418c904b175141c8… Author: Tobias Pape <tobias(a)netshed.de> Date: 2022-02-23 (Wed, 23 Feb 2022) Changed paths: M platforms/unix/config/aclocal.m4 M platforms/unix/config/configure M platforms/unix/config/configure.ac M platforms/unix/config/ltmain.sh Log Message: ----------- [unix] add configure option to disable epoll also: regenerate configure (slightly bumps autoconf version)

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[OpenSmalltalk/opensmalltalk-vm] High-DPI window decorations (Issue #611)
by Christoph Thiede 23 Feb '22

23 Feb '22

In the Squeak bundles, the executables for Windows now contain a manifest file to make sure the image contents are not displayed blurry on high-DPI screens but we can use the image-side scaling mechanism instead. However, the VM does not scale up the window decorations properly even though this is promised by the manifest file: 100% DPI: ![image](https://user-images.githubusercontent.com/38782922/149572360-b7a3b0f8-623a-427c-b408-50d9d0c305f1.png) 250% DPI: ![image](https://user-images.githubusercontent.com/38782922/149572201-23f311f6-b2a2-424d-8f4a-891eedb32e02.png) -- Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/611 You are receiving this because you are subscribed to this thread. Message ID: <OpenSmalltalk/opensmalltalk-vm/issues/611(a)github.com>

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[OpenSmalltalk/opensmalltalk-vm] f2dc60: CogVM source as per VMMaker.oscog-eem.3168
by Eliot Miranda 23 Feb '22

23 Feb '22

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: f2dc60af97e3770d85a84f6ef0dfc17661c2f2e7 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/f2dc60af97e3770d85… Author: Eliot Miranda <eliot.miranda(a)gmail.com> Date: 2022-02-23 (Wed, 23 Feb 2022) Changed paths: M src/spur32.cog.lowcode/cogit.h M src/spur32.cog.lowcode/cogitARMv5.c M src/spur32.cog.lowcode/cogitIA32.c M src/spur32.cog/cogit.h M src/spur32.cog/cogitARMv5.c M src/spur32.cog/cogitIA32.c M src/spur32.sista/cogit.h M src/spur32.sista/cogitARMv5.c M src/spur32.sista/cogitIA32.c M src/spur64.cog.lowcode/cogit.h M src/spur64.cog.lowcode/cogitARMv8.c M src/spur64.cog.lowcode/cogitX64SysV.c M src/spur64.cog.lowcode/cogitX64WIN64.c M src/spur64.cog/cogit.h M src/spur64.cog/cogitARMv8.c M src/spur64.cog/cogitX64SysV.c M src/spur64.cog/cogitX64WIN64.c M src/spur64.sista/cogit.h M src/spur64.sista/cogitARMv8.c M src/spur64.sista/cogitX64SysV.c M src/spur64.sista/cogitX64WIN64.c M src/v3.cog/cogit.h M src/v3.cog/cogitARMv5.c M src/v3.cog/cogitIA32.c Log Message: ----------- CogVM source as per VMMaker.oscog-eem.3168 CogARMv8Compiler: add logging of which lines set or clear executability via pthread_jit_write_protect_np. Hence find that Cogit>>freeUnmarkedMachineCode was not enabling executability. StackToRegisterMappingCogit: Fix assert failures on first pass of embedded block compilations.

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VM Maker: VMMaker.oscog-eem.3168.mcz
by commits＠source.squeak.org 23 Feb '22

23 Feb '22

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.3168.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.3168 Author: eem Time: 23 February 2022, 11:26:52.582045 am UUID: a0f1436f-0a54-429c-a61e-271ce020741a Ancestors: VMMaker.oscog-eem.3167 CogARMv8Compiler: add logging of which lines set or clear executability via pthread_jit_write_protect_np. Hence find that Cogit>>freeUnmarkedMachineCode was not enabling executability. We'll leave the logging in for now; it can be made conditional at some future date. =============== Diff against VMMaker.oscog-eem.3167 =============== Item was changed: CogAbstractInstruction subclass: #CogARMv8Compiler instanceVariableNames: '' + classVariableNames: 'AL ArithmeticAdd ArithmeticAddS ArithmeticSub ArithmeticSubS CASAL CArg0Reg CArg1Reg CArg2Reg CArg3Reg CArg4Reg CArg5Reg CArg6Reg CBNZ CBZ CC CCMPNE CLREX CS CSET D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 DC DC_CISW DC_CIVAC DC_CSW DC_CVAC DC_CVAU DC_ISW DC_IVAC DC_ZVA DMB DSB DSB_ALL DSB_ALLSY DSB_ISH DSB_NSH DSB_OSH DSB_READS DSB_SY DSB_WRITES DataCacheFlushRequired DataCacheLineLength DivRRR EQ FP GE GT HI HasAtomicInstructions IC IC_IALLU IC_IALLUIS IC_IVAU ISB InstructionCacheFlushRequired InstructionCacheLineLength LDAXR LE LR LS LT LogicalAnd LogicalAndS LogicalOr LogicalXor MI MRS_CTR_EL0 MRS_ID_AA64ISAR0_EL1 MSubRRR MoveAwRR MoveRRAw MulOverflowRRR MulRRR NE NativePopRR NativePushRR PJWPNChange PJWPNClear PJWPNSet PJWPNState PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 SMULHRRR SP STLR STLXR SXTB SXTH SXTW SXTX UXTB UXTH UXTW UXTX VC VS XZR' - classVariableNames: 'AL ArithmeticAdd ArithmeticAddS ArithmeticSub ArithmeticSubS CASAL CArg0Reg CArg1Reg CArg2Reg CArg3Reg CArg4Reg CArg5Reg CArg6Reg CBNZ CBZ CC CCMPNE CLREX CS CSET D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 DC DC_CISW DC_CIVAC DC_CSW DC_CVAC DC_CVAU DC_ISW DC_IVAC DC_ZVA DMB DSB DSB_ALL DSB_ALLSY DSB_ISH DSB_NSH DSB_OSH DSB_READS DSB_SY DSB_WRITES DataCacheFlushRequired DataCacheLineLength DivRRR EQ FP GE GT HI HasAtomicInstructions IC IC_IALLU IC_IALLUIS IC_IVAU ISB InstructionCacheFlushRequired InstructionCacheLineLength LDAXR LE LR LS LT LogicalAnd LogicalAndS LogicalOr LogicalXor MI MRS_CTR_EL0 MRS_ID_AA64ISAR0_EL1 MSubRRR MoveAwRR MoveRRAw MulOverflowRRR MulRRR NE NativePopRR NativePushRR PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 SMULHRRR SP STLR STLXR SXTB SXTH SXTW SXTX UXTB UXTH UXTW UXTX VC VS XZR' poolDictionaries: 'ARMv8A64Opcodes' category: 'VMMaker-JIT'! !CogARMv8Compiler commentStamp: 'eem 1/7/2021 23:01' prior: 0! I generate ARMv8 machine code instructions from CogAbstractInstructions with CogRTLOpcodes. Here in "Arm ARM" refers to Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-ma… Some things to know about ARMv8 instructions: Whether 31 in a register field implies the zero register or the SP register(s) depends on the specific instruction. C3.2.1 Load/Store register If a Load instruction specifies writeback and the register being loaded is also the base register, then behavior is CONSTRAINED UNPREDICTABLE and one of the following behaviors must occur: - The instruction is treated as UNDEFINED. - The instruction is treated as a NOP. - The instruction performs the load using the specified addressing mode and the base register becomes UNKNOWN. In addition, if an exception occurs during the execution of such an instruction, the base address might be corrupted so that the instruction cannot be repeated. If a Store instruction performs a writeback and the register that is stored is also the base register, then behavior is CONSTRAINED UNPREDICTABLE and one of the following behaviors must occur: - The instruction is treated as UNDEFINED. - The instruction is treated as a NOP. - The instruction performs the store to the designated register using the specified addressing mode, but the value stored is UNKNOWN.! Item was changed: ----- Method: CogARMv8Compiler class>>declareCVarsIn: (in category 'translation') ----- declareCVarsIn: aCCodeGenerator #('hasAtomicInstructions' 'instructionCacheLineLength' 'instructionCacheFlushRequired' 'dataCacheLineLength' 'dataCacheFlushRequired') do: [:varName| aCCodeGenerator declareVar: varName type: #'unsigned char'; removeConstant: varName capitalized]. + (classPool keys select: [:k| k beginsWith: 'PJWPN']) do: + [:k| + aCCodeGenerator removeConstant: k; declareVar: k type: #int]. aCCodeGenerator var: #ceFlushDCache "sigh; this is here to placate Slang; we don't use this, but Slang doesn't elide the assignment..." declareC: 'static void (*ceFlushDCache)(usqIntptr_t from, usqIntptr_t to)'! Item was changed: ----- Method: CogARMv8Compiler class>>initialize (in category 'class initialization') ----- initialize "Initialize various ARM64 instruction-related constants." "self initialize" "main registers; a minor complication in reading the doc. ARM refer to the 64bit registers as X0...30 and use R0...30 to refer to the 32bit lower halves. They also use a whole suite of names for the floating point/SIMD registers. See ARMARM DDI0487 B1.2.1 etc for the gory details. Note that R30 (yes, yes, X30) is used as the link register and as such is not really a general purpose register. Also note that 31 in a general register field means R31, and that in most of these instructions R31 is the zero register named XZR in ARM doc. but in the rest of these instructions R31 the effective SP register. XZR is a pseudo-register that always reads as 0 and writes to /dev/null. And note that unlike the ARM32, there is no general purpose register for the PC; a big difference. See ARMARM DDI0487 C1.2.5. wrt to both the lack of a PC register and the XZR/SP distinction." "and initialize most sets of variables that run from 0 to N - 1..." #( "General registers, 0 to 31. We stick with R0...30 to refer to the 64 bit general regs and D0...31 (note the extra reg here!!) for the FP/SIMD regs" (R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31) "Floating-point registers, 0 to 31" (D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31) "C argument registers, 0 to 6" (CArg0Reg CArg1Reg CArg2Reg CArg3Reg CArg4Reg CArg5Reg CArg6Reg) "Condition Codes 0 to 16. Note that cc=16rF is mapped back to AL in AARCH64. Generally it shouldn't be used." (EQ NE CS CC MI PL VS VC HI LS GE LT GT LE AL) "Logical Op Codes" (LogicalAnd LogicalOr LogicalXor LogicalAndS) "Arithmetic Opcodes" "ADD (shifted register) on page C6-763 10001011 ADDS (shifted register) on page C6-771 10101011 CMN (shifted register) on page C6-854 10101011 Rd=XZR SUB (shifted register) on page C6-1313 11001011 SUBS (shifted register) on page C6-1323 11101011 CMP (shifted register) on page C6-860 11101011 Rd=XZR NEG (shifted register) on page C6-1114 11001011 Rn=XZR NEGS on page C6-1116 11101011 Rn=XZR" (ArithmeticAdd ArithmeticAddS ArithmeticSub ArithmeticSubS) "Extension Methods " (UXTB UXTH UXTW UXTX "a.k.a. LSL" SXTB SXTH SXTW SXTX)) do: [:classVarNames| classVarNames withIndexDo: [:k :v| CogARMv8Compiler classPool at: k put: v - 1]]. SP := XZR := R31. LR := R30. FP := R29. "DC variant selectors; see concretizeDataCacheControl" DC_CISW := 13. DC_CIVAC := 14. DC_CSW := 15. DC_CVAC := 16. DC_CVAU := 19. DC_ISW := 26. DC_IVAC := 27. DC_ZVA := 28. "IC variant selectors; see concretizeInstructionCacheControl" IC_IALLU := 0. IC_IALLUIS := 1. IC_IVAU := 2. "DSB domains and types C6.2.81 DSB C6-891" DSB_OSH := 0. "Domain_OuterSharable" DSB_NSH := 1. "Domain_NonSharable" DSB_ISH := 2. "Domain_InnerSharable" DSB_SY := 3. "Domain_FullSystem" DSB_ALLSY := 0. "Types_All; domain = Domain_FullSystem" DSB_READS := 1. "Types_Reads" DSB_WRITES := 2. "Types_Writes" DSB_ALL := 3. "Types_All; domain ~= Domain_FullSystem" + "Debugging of the executable/writable switch on Apple." + PJWPNState := false. PJWPNClear := PJWPNSet := PJWPNChange = 0. + "Specific instructions" self initializeSpecificOpcodes: #(MulRRR MulOverflowRRR SMULHRRR DivRRR MSubRRR "N.B. ARMv8 has MSUBRRRR but we only support three operands" MoveAwRR MoveRRAw NativePushRR NativePopRR "these map to ldp/stp" "Cache control and memory barrier" "B2.3.7 Memory barriers B2-124" DC IC DMB DSB ISB MRS_CTR_EL0 MRS_ID_AA64ISAR0_EL1 CASAL CBNZ CBZ CCMPNE CSET CLREX LDAXR STLXR STLR) in: thisContext method! Item was added: + ----- Method: CogARMv8Compiler class>>mustBeGlobal: (in category 'translation') ----- + mustBeGlobal: var + "Answer if a variable must be global and exported. Used for inst vars that are accessed from VM support code." + + ^var beginsWith: 'PJWPN'! Item was changed: ----- Method: CogARMv8Compiler>>makeCodeZoneExecutable (in category 'memory access') ----- makeCodeZoneExecutable <inline: #always> + self cCode: + [self cppIf: #__APPLE__ & #__MACH__ + ifTrue: + [cogit pthread_jit_write_protect_np: true. + PJWPNSet := #__LINE__. + PJWPNState ifFalse: + [PJWPNChange := #__LINE__. + PJWPNState := true]]]! - self cCode: [self cppIf: #__APPLE__ & #__MACH__ ifTrue: [cogit pthread_jit_write_protect_np: true]]! Item was changed: ----- Method: CogARMv8Compiler>>makeCodeZoneWritable (in category 'memory access') ----- makeCodeZoneWritable <inline: #always> + self cCode: + [self cppIf: #__APPLE__ & #__MACH__ + ifTrue: + [cogit pthread_jit_write_protect_np: false. + PJWPNClear := #__LINE__. + PJWPNState ifTrue: + [PJWPNChange := #__LINE__. + PJWPNState := false]]]! - self cCode: [self cppIf: #__APPLE__ & #__MACH__ ifTrue: [cogit pthread_jit_write_protect_np: false]]! Item was added: + ----- Method: CogAbstractInstruction class>>mustBeGlobal: (in category 'translation') ----- + mustBeGlobal: var + "Answer if a variable must be global and exported. Used for inst vars that are accessed from VM support code." + + ^false! Item was changed: ----- Method: Cogit class>>mustBeGlobal: (in category 'translation') ----- mustBeGlobal: var "Answer if a variable must be global and exported. Used for inst vars that are accessed from VM support code, or that need visibility at the gdb/lldb level." + ^(#('ceBaseFrameReturnTrampoline' ceCaptureCStackPointers 'ceCheckForInterruptTrampoline' - ^#('ceBaseFrameReturnTrampoline' ceCaptureCStackPointers 'ceCheckForInterruptTrampoline' ceEnterCogCodePopReceiverReg realCEEnterCogCodePopReceiverReg ceCallCogCodePopReceiverReg realCECallCogCodePopReceiverReg ceCallCogCodePopReceiverAndClassRegs realCECallCogCodePopReceiverAndClassRegs ceInvokeInterpret 'ceReturnToInterpreterTrampoline' 'ceCannotResumeTrampoline' ceTryLockVMOwner 'cmEntryOffset' 'cmNoCheckEntryOffset' 'cmDynSuperEntryOffset' 'cmSelfSendEntryOffset' 'missOffset' 'cbEntryOffset' 'cbNoSwitchEntryOffset' 'blockNoContextSwitchOffset' breakPC ceGetFP ceGetSP cFramePointerInUse methodZoneBase traceFlags traceStores) + includes: var) + or: [self activeCompilerClass mustBeGlobal: var]! - includes: var! Item was changed: ----- Method: Cogit>>freeUnmarkedMachineCode (in category 'jit - api') ----- freeUnmarkedMachineCode "Free machine-code methods whose compiled methods are unmarked and open PICs whose selectors are not marked, and closed PICs that refer to unmarked objects." <api> <option: #SpurObjectMemory> | cogMethod freedMethod | self moveProfileToMethods. "simulation only..." freedMethod := false. cogMethod := self cCoerceSimple: methodZoneBase to: #'CogMethod *'. [cogMethod < methodZone limitZony] whileTrue: [(cogMethod cmType = CMMethod and: [(objectMemory isMarked: cogMethod methodObject) not]) ifTrue: [freedMethod := true. methodZone freeMethod: cogMethod]. (cogMethod cmType = CMOpenPIC and: [(objectMemory isImmediate: cogMethod selector) not and: [(objectMemory isMarked: cogMethod selector) not]]) ifTrue: [freedMethod := true. methodZone freeMethod: cogMethod]. (cogMethod cmType = CMClosedPIC and: [self closedPICRefersToUnmarkedObject: cogMethod]) ifTrue: [freedMethod := true. methodZone freeMethod: cogMethod]. cogMethod := methodZone methodAfter: cogMethod]. freedMethod ifTrue: + [self unlinkSendsToFree]. + backEnd ensureExecutableCodeZone! - [self unlinkSendsToFree]!

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VM Maker: VMMaker.oscog-eem.3167.mcz
by commits＠source.squeak.org 23 Feb '22

23 Feb '22

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.3167.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.3167 Author: eem Time: 22 February 2022, 6:00:47.332049 pm UUID: ab240217-a8b0-4942-9951-c2164bcb3479 Ancestors: VMMaker.oscog-eem.3166 StackToRegisterMappingCogit: Fix assert failures on first pass of embedded block compilations. In-image compilation: Fix a slip in debugStackPointersFor: =============== Diff against VMMaker.oscog-eem.3166 =============== Item was changed: ----- Method: CurrentImageCoInterpreterFacade>>debugStackPointersFor: (in category 'accessing') ----- debugStackPointersFor: anOop ^CArrayAccessor on: ((StackDepthFinder on: (objectMap keyAtValue: anOop)) + encoderClass: (coInterpreter encoderClassForHeader: (objectMemory integerObjectOf: (objectMap keyAtValue: anOop) header)); - encoderClass: (coInterpreter encoderClassForHeader: (objectMap keyAtValue: anOop) header); stackPointers)! Item was changed: ----- Method: StackToRegisterMappingCogit>>assertCorrectSimStackPtr (in category 'compile abstract instructions') ----- assertCorrectSimStackPtr <inline: true> "Would like to assert simply simSpillBase > methodOrBlockNumTemps but can't because of the initialNils hack for nested blocks in SqueakV3PlusClosures" self assert: (simSpillBase >= methodOrBlockNumTemps or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil and: [simSpillBase > methodOrBlockNumArgs]]). (needsFrame and: [simSpillBase > 0]) ifTrue: + [self assert: ((self simStackAt: simSpillBase - 1) spilled == true or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil and: [simSpillBase > methodOrBlockNumArgs]]). - [self assert: (self simStackAt: simSpillBase - 1) spilled == true. self assert: (simSpillBase > simStackPtr or: [(self simStackAt: simSpillBase) spilled == false])]. self cCode: '' inSmalltalk: [deadCode ifFalse: [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) = (self debugStackPointerFor: bytecodePC)]].!

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[OpenSmalltalk/opensmalltalk-vm] f65940: CogVM surce as per VMMaker.oscog-eem.3166
by Eliot Miranda 23 Feb '22

23 Feb '22

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: f6594056fa5de7709b67e323877ff8d1d7de573a https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/f6594056fa5de7709b… Author: Eliot Miranda <eliot.miranda(a)gmail.com> Date: 2022-02-22 (Tue, 22 Feb 2022) Changed paths: M building/macos32x86/gdbarm32/conf.COG M building/macos32x86/gdbarm64/conf.COG M building/macos64ARMv8/gdbarm32/conf.COG M building/macos64ARMv8/gdbarm64/conf.COG M building/macos64x64/gdbarm32/conf.COG M building/macos64x64/gdbarm64/conf.COG M src/plugins/AsynchFilePlugin/AsynchFilePlugin.c M src/plugins/B2DPlugin/B2DPlugin.c M src/plugins/BitBltPlugin/BitBltPlugin.c M src/plugins/BochsIA32Plugin/BochsIA32Plugin.c M src/plugins/BochsX64Plugin/BochsX64Plugin.c M src/plugins/CameraPlugin/CameraPlugin.c M src/plugins/ClipboardExtendedPlugin/ClipboardExtendedPlugin.c M src/plugins/CroquetPlugin/CroquetPlugin.c M src/plugins/DESPlugin/DESPlugin.c M src/plugins/DSAPrims/DSAPrims.c M src/plugins/FileAttributesPlugin/FileAttributesPlugin.c M src/plugins/FileCopyPlugin/FileCopyPlugin.c M src/plugins/FileDialogPlugin/FileDialogPlugin.c M src/plugins/FilePlugin/FilePlugin.c M src/plugins/Float64ArrayPlugin/Float64ArrayPlugin.c M src/plugins/FloatArrayPlugin/FloatArrayPlugin.c M src/plugins/GdbARMPlugin/GdbARMPlugin.c M src/plugins/GdbARMv8Plugin/GdbARMv8Plugin.c M src/plugins/GeniePlugin/GeniePlugin.c M src/plugins/HostWindowPlugin/HostWindowPlugin.c M src/plugins/IA32ABI/IA32ABI.c M src/plugins/ImmX11Plugin/ImmX11Plugin.c M src/plugins/InternetConfigPlugin/InternetConfigPlugin.c M src/plugins/JPEGReadWriter2Plugin/JPEGReadWriter2Plugin.c M src/plugins/JoystickTabletPlugin/JoystickTabletPlugin.c M src/plugins/LargeIntegers/LargeIntegers.c M src/plugins/MD5Plugin/MD5Plugin.c M src/plugins/MIDIPlugin/MIDIPlugin.c M src/plugins/MacMenubarPlugin/MacMenubarPlugin.c M src/plugins/MiscPrimitivePlugin/MiscPrimitivePlugin.c M src/plugins/Mpeg3Plugin/Mpeg3Plugin.c M src/plugins/QuicktimePlugin/QuicktimePlugin.c M src/plugins/SHA2Plugin/SHA2Plugin.c M src/plugins/SerialPlugin/SerialPlugin.c M src/plugins/SocketPlugin/SocketPlugin.c M src/plugins/SoundCodecPrims/SoundCodecPrims.c M src/plugins/SoundPlugin/SoundPlugin.c M src/plugins/Squeak3D/Squeak3D.c M src/plugins/SqueakFFIPrims/ARM32FFIPlugin.c M src/plugins/SqueakFFIPrims/ARM64FFIPlugin.c M src/plugins/SqueakFFIPrims/IA32FFIPlugin.c M src/plugins/SqueakFFIPrims/X64SysVFFIPlugin.c M src/plugins/SqueakFFIPrims/X64Win64FFIPlugin.c M src/plugins/UnixOSProcessPlugin/UnixOSProcessPlugin.c M src/plugins/VMProfileLinuxSupportPlugin/VMProfileLinuxSupportPlugin.c M src/plugins/VMProfileMacSupportPlugin/VMProfileMacSupportPlugin.c M src/plugins/Win32OSProcessPlugin/Win32OSProcessPlugin.c M src/plugins/ZipPlugin/ZipPlugin.c M src/spur32.cog.lowcode/cogit.h M src/spur32.cog.lowcode/cogitARMv5.c M src/spur32.cog.lowcode/cogitIA32.c M src/spur32.cog.lowcode/cointerp.c M src/spur32.cog.lowcode/cointerp.h M src/spur32.cog.lowcode/gcc3x-cointerp.c M src/spur32.cog/cogit.h M src/spur32.cog/cogitARMv5.c M src/spur32.cog/cogitIA32.c M src/spur32.cog/cointerp.c M src/spur32.cog/cointerp.h M src/spur32.cog/cointerpmt.c M src/spur32.cog/cointerpmt.h M src/spur32.cog/gcc3x-cointerp.c M src/spur32.cog/gcc3x-cointerpmt.c M src/spur32.sista/cogit.h M src/spur32.sista/cogitARMv5.c M src/spur32.sista/cogitIA32.c M src/spur32.sista/cointerp.c M src/spur32.sista/cointerp.h M src/spur32.sista/gcc3x-cointerp.c M src/spur32.stack.lowcode/gcc3x-interp.c M src/spur32.stack.lowcode/interp.c M src/spur32.stack/gcc3x-interp.c M src/spur32.stack/interp.c M src/spur32.stack/validImage.c M src/spur64.cog.lowcode/cogit.h M src/spur64.cog.lowcode/cogitARMv8.c M src/spur64.cog.lowcode/cogitX64SysV.c M src/spur64.cog.lowcode/cogitX64WIN64.c M src/spur64.cog.lowcode/cointerp.c M src/spur64.cog.lowcode/cointerp.h M src/spur64.cog.lowcode/gcc3x-cointerp.c M src/spur64.cog/cogit.h M src/spur64.cog/cogitARMv8.c M src/spur64.cog/cogitX64SysV.c M src/spur64.cog/cogitX64WIN64.c M src/spur64.cog/cointerp.c M src/spur64.cog/cointerp.h M src/spur64.cog/cointerpmt.c M src/spur64.cog/cointerpmt.h M src/spur64.cog/gcc3x-cointerp.c M src/spur64.cog/gcc3x-cointerpmt.c M src/spur64.sista/cogit.h M src/spur64.sista/cogitARMv8.c M src/spur64.sista/cogitX64SysV.c M src/spur64.sista/cogitX64WIN64.c M src/spur64.sista/cointerp.c M src/spur64.sista/cointerp.h M src/spur64.sista/gcc3x-cointerp.c M src/spur64.stack.lowcode/gcc3x-interp.c M src/spur64.stack.lowcode/interp.c M src/spur64.stack/gcc3x-interp.c M src/spur64.stack/interp.c M src/spur64.stack/validImage.c M src/v3.cog/cogit.h M src/v3.cog/cogitARMv5.c M src/v3.cog/cogitIA32.c M src/v3.cog/cointerp.c M src/v3.cog/cointerp.h M src/v3.cog/gcc3x-cointerp.c M src/v3.stack/gcc3x-interp.c M src/v3.stack/interp.c Log Message: ----------- CogVM surce as per VMMaker.oscog-eem.3166 StackInterpreter: stackPage should either be nil or a StackPage, not zero or a StackPage. Slang type inferrence: have it construct pointer types in the house style (no space between the * and the following var name). macos64ARMv8: fix the gdbarm32/64 simulator support lib configuration scripts.

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Vm-dev February 2022