Vm-dev November 2015

vm-dev@lists.squeakfoundation.org

32 participants
118 discussions

VM Maker: Cog-rmacnak.294.mcz
by commits＠source.squeak.org 12 Nov '15

12 Nov '15

Ryan Macnak uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-rmacnak.294.mcz ==================== Summary ==================== Name: Cog-rmacnak.294 Author: rmacnak Time: 11 November 2015, 8:49:29.983 pm UUID: 474cf204-cc7d-4c72-bf46-806f7a8095f9 Ancestors: Cog-eem.293 Initial commit of MIPSEL simulator. =============== Diff against Cog-eem.293 =============== Item was added: + SharedPool subclass: #MIPSConstants + instanceVariableNames: '' + classVariableNames: 'A0 A1 A2 A3 ADDIU ADDU AND ANDI AT BEQ BGEZ BGTZ BLEZ BLTZ BNE BREAK FP GP J JAL JALR JR K0 K1 LB LBU LH LHU LUI LW OR ORI OneInstruction R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 RA REGIMM S0 S1 S2 S3 S4 S5 S6 S7 SB SH SLL SLLV SLT SLTI SLTIU SLTU SP SPECIAL SRA SRAV SRL SRLV SUBU SW T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TwoInstructions V0 V1 XOR XORI ZR' + poolDictionaries: '' + category: 'Cog-Processors'! + + !MIPSConstants commentStamp: 'rmacnak 11/11/2015 20:29:59' prior: 0! + MIPS opcodes and register names.! Item was added: + ----- Method: MIPSConstants class>>initialize (in category 'as yet unclassified') ----- + initialize + super initialize. + + OneInstruction := 4. + TwoInstructions := 8. + + self initializeRegisters. + self initializeOpcodes. + self initializeSpecialFunctions. + self initializeRegImmRts.! Item was added: + ----- Method: MIPSConstants class>>initializeOpcodes (in category 'as yet unclassified') ----- + initializeOpcodes + SPECIAL := 0. + REGIMM := 1. + J := 2. + JAL := 3. + BEQ := 4. + BNE := 5. + BLEZ := 6. + BGTZ := 7. + ADDIU := 9. + SLTI := 10. + SLTIU := 11. + ANDI := 12. + ORI := 13. + XORI := 14. + LUI := 15. + LB := 32. + LH := 33. + LW := 35. + LBU := 36. + LHU := 37. + SB := 40. + SH := 41. + SW := 43.! Item was added: + ----- Method: MIPSConstants class>>initializeRegImmRts (in category 'as yet unclassified') ----- + initializeRegImmRts + BLTZ := 0. + BGEZ := 1.! Item was added: + ----- Method: MIPSConstants class>>initializeRegisters (in category 'as yet unclassified') ----- + initializeRegisters + self flag: #OABI. + R0 := ZR := 0. "Hardwired zero" + R1 := AT := 1. "Assembler temp - used to expand psuedo instructions" + R2 := V0 := 2. "ABI: result register" + R3 := V1 := 3. "ABI: result register" + R4 := A0 := 4. "ABI: argument register" + R5 := A1 := 5. "ABI: argument register" + R6 := A2 := 6. "ABI: argument register" + R7 := A3 := 7. "ABI: argument register" + R8 := T0 := 8. "ABI: volatile" + R9 := T1 := 9. "ABI: volatile" + R10 := T2 := 10. "ABI: volatile" + R11 := T3 := 11. "ABI: volatile" + R12 := T4 := 12. "ABI: volatile" + R13 := T5 := 13. "ABI: volatile" + R14 := T6 := 14. "ABI: volatile" + R15 := T7 := 15. "ABI: volatile" + R16 := S0 := 16. "ABI: preserved" + R17 := S1 := 17. "ABI: preserved" + R18 := S2 := 18. "ABI: preserved" + R19 := S3 := 19. "ABI: preserved" + R20 := S4 := 20. "ABI: preserved" + R21 := S5 := 21. "ABI: preserved" + R22 := S6 := 22. "ABI: preserved" + R23 := S7 := 23. "ABI: preserved" + R24 := T8 := 24. "ABI: volatile" + R25 := T9 := 25. "Special use in some position-independent code" + R26 := K0 := 26. "Reserved for OS" + R27 := K1 := 27. "Reserved for OS" + R28 := GP := 28. "Special use in some position-independent code" + R29 := SP := 29. "Stack pointer" + R30 := FP := 30. "Frame pointer" + R31 := RA := 31. "Link register" + + ! Item was added: + ----- Method: MIPSConstants class>>initializeSpecialFunctions (in category 'as yet unclassified') ----- + initializeSpecialFunctions + SLL := 0. + SRL := 2. + SRA := 3. + SLLV := 4. + SRLV := 6. + SRAV := 7. + JR := 8. + JALR := 9. + BREAK := 13. + ADDU := 33. + SUBU := 35. + AND := 36. + OR := 37. + XOR := 38. + SLT := 42. + SLTU := 43.! Item was added: + ----- Method: MIPSConstants class>>nameForRegister: (in category 'as yet unclassified') ----- + nameForRegister: registerNumber + ^#(zr at v0 v1 a0 a1 a2 a3 + t0 t1 t2 t3 t4 t5 t6 t7 + s0 s1 s2 s3 s4 s5 s6 s7 + t8 t9 k0 k1 gp sp fp ra) at: registerNumber + 1! Item was added: + Object subclass: #MIPSDisassembler + instanceVariableNames: 'pc' + classVariableNames: '' + poolDictionaries: 'MIPSConstants' + category: 'Cog-Processors'! Item was added: + ----- Method: MIPSDisassembler>>addImmediateUnsigned: (in category 'instructions - arithmetic') ----- + addImmediateUnsigned: instruction + ^'addiu ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (instruction signedImmediate printString)! Item was added: + ----- Method: MIPSDisassembler>>addUnsigned: (in category 'instructions - arithmetic') ----- + addUnsigned: instruction + ^'addu ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (MIPSConstants nameForRegister: instruction rt)! Item was added: + ----- Method: MIPSDisassembler>>andImmediate: (in category 'instructions - arithmetic') ----- + andImmediate: instruction + ^'andi ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (instruction unsignedImmediate printString)! Item was added: + ----- Method: MIPSDisassembler>>bitwiseAnd: (in category 'instructions - arithmetic') ----- + bitwiseAnd: instruction + ^'and ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (MIPSConstants nameForRegister: instruction rt)! Item was added: + ----- Method: MIPSDisassembler>>bitwiseOr: (in category 'instructions - arithmetic') ----- + bitwiseOr: instruction + ^'or ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (MIPSConstants nameForRegister: instruction rt)! Item was added: + ----- Method: MIPSDisassembler>>bitwiseXor: (in category 'instructions - arithmetic') ----- + bitwiseXor: instruction + ^'xor ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (MIPSConstants nameForRegister: instruction rt)! Item was added: + ----- Method: MIPSDisassembler>>branchEqual: (in category 'instructions - control') ----- + branchEqual: instruction + | offset target | + offset := instruction signedImmediate << 2. + target := pc + offset + OneInstruction. "Offset is relative to the delay slot" + ^'beq ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (offset > 0 ifTrue: ['+'] ifFalse: ['']), offset printString, ' ; =', (target printStringBase: 16)! Item was added: + ----- Method: MIPSDisassembler>>branchGreaterEqualZero: (in category 'instructions - control') ----- + branchGreaterEqualZero: instruction + | offset target | + offset := instruction signedImmediate << 2. + target := pc + offset + OneInstruction. "Offset is relative to the delay slot" + ^'bgez ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (offset > 0 ifTrue: ['+'] ifFalse: ['']), offset printString, ' ; =', (target printStringBase: 16)! Item was added: + ----- Method: MIPSDisassembler>>branchGreaterThanZero: (in category 'instructions - control') ----- + branchGreaterThanZero: instruction + | offset target | + offset := instruction signedImmediate << 2. + target := pc + offset + OneInstruction. "Offset is relative to the delay slot" + ^'bgtz ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (offset > 0 ifTrue: ['+'] ifFalse: ['']), offset printString, ' ; =', (target printStringBase: 16)! Item was added: + ----- Method: MIPSDisassembler>>branchLessEqualZero: (in category 'instructions - control') ----- + branchLessEqualZero: instruction + | offset target | + offset := instruction signedImmediate << 2. + target := pc + offset + OneInstruction. "Offset is relative to the delay slot" + ^'blez ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (offset > 0 ifTrue: ['+'] ifFalse: ['']), offset printString, ' ; =', (target printStringBase: 16)! Item was added: + ----- Method: MIPSDisassembler>>branchLessThanZero: (in category 'instructions - control') ----- + branchLessThanZero: instruction + | offset target | + offset := instruction signedImmediate << 2. + target := pc + offset + OneInstruction. "Offset is relative to the delay slot" + ^'bltz ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (offset > 0 ifTrue: ['+'] ifFalse: ['']), offset printString, ' ; =', (target printStringBase: 16)! Item was added: + ----- Method: MIPSDisassembler>>branchNotEqual: (in category 'instructions - control') ----- + branchNotEqual: instruction + | offset target | + offset := instruction signedImmediate << 2. + target := pc + offset + OneInstruction. "Offset is relative to the delay slot" + ^'bne ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (offset > 0 ifTrue: ['+'] ifFalse: ['']), offset printString, ' ; =', (target printStringBase: 16)! Item was added: + ----- Method: MIPSDisassembler>>break: (in category 'instructions - control') ----- + break: instruction + ^'break'! Item was added: + ----- Method: MIPSDisassembler>>disassemble:from:to: (in category 'as yet unclassified') ----- + disassemble: memory from: startPC to: limitPC + | stream | + stream := WriteStream on: ''. + self disassemble: memory from: startPC to: limitPC for: nil labels: nil on: stream. + ^stream contents! Item was added: + ----- Method: MIPSDisassembler>>disassemble:from:to:for:labels:on: (in category 'as yet unclassified') ----- + disassemble: memory from: startPC to: limitPC for: aSymbolManager "<Cogit>" labels: labelDictionary on: aStream + pc := startPC. + [pc < limitPC] whileTrue: + [ | word instruction | + pc printOn: aStream base: 16 nDigits: 8. + aStream space; space. + word := memory unsignedLongAt: pc + 1. + word printOn: aStream base: 16 nDigits: 8. + aStream space; space. + instruction := MIPSInstruction new value: word. + aStream nextPutAll: (instruction decodeFor: self). + aStream cr. + pc := pc + OneInstruction].! Item was added: + ----- Method: MIPSDisassembler>>jump: (in category 'instructions - control') ----- + jump: instruction + | target | + target := (pc + OneInstruction) bitAnd: 16rF0000000. "Region is that of the delay slot" + target := target + (instruction target << 2). + ^'j ', (target printStringBase: 16)! Item was added: + ----- Method: MIPSDisassembler>>jumpAndLink: (in category 'instructions - control') ----- + jumpAndLink: instruction + | target | + target := (pc + OneInstruction) bitAnd: 16rF0000000. "Region is that of the delay slot" + target := target + (instruction target << 2). + ^'jal ', (target printStringBase: 16)! Item was added: + ----- Method: MIPSDisassembler>>jumpAndLinkRegister: (in category 'instructions - control') ----- + jumpAndLinkRegister: instruction + instruction rd = 31 ifTrue: [^'jalr ', (MIPSConstants nameForRegister: instruction rs)]. + ^'jalr ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rs)! Item was added: + ----- Method: MIPSDisassembler>>jumpRegister: (in category 'instructions - control') ----- + jumpRegister: instruction + ^'jr ', (MIPSConstants nameForRegister: instruction rs)! Item was added: + ----- Method: MIPSDisassembler>>loadByte: (in category 'instructions - memory') ----- + loadByte: instruction + ^'lb ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (instruction signedImmediate printString), '(', + (MIPSConstants nameForRegister: instruction rs), ')'! Item was added: + ----- Method: MIPSDisassembler>>loadByteUnsigned: (in category 'instructions - memory') ----- + loadByteUnsigned: instruction + ^'lbu ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (instruction signedImmediate printString), '(', + (MIPSConstants nameForRegister: instruction rs), ')'! Item was added: + ----- Method: MIPSDisassembler>>loadHalfword: (in category 'instructions - memory') ----- + loadHalfword: instruction + ^'lh ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (instruction signedImmediate printString), '(', + (MIPSConstants nameForRegister: instruction rs), ')'! Item was added: + ----- Method: MIPSDisassembler>>loadHalfwordUnsigned: (in category 'instructions - memory') ----- + loadHalfwordUnsigned: instruction + ^'lhu ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (instruction signedImmediate printString), '(', + (MIPSConstants nameForRegister: instruction rs), ')'! Item was added: + ----- Method: MIPSDisassembler>>loadUpperImmediate: (in category 'instructions - arithmetic') ----- + loadUpperImmediate: instruction + ^'lui ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (instruction signedImmediate printString)! Item was added: + ----- Method: MIPSDisassembler>>loadWord: (in category 'instructions - memory') ----- + loadWord: instruction + ^'lw ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (instruction signedImmediate printString), '(', + (MIPSConstants nameForRegister: instruction rs), ')'! Item was added: + ----- Method: MIPSDisassembler>>orImmediate: (in category 'instructions - arithmetic') ----- + orImmediate: instruction + ^'ori ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (instruction unsignedImmediate printString)! Item was added: + ----- Method: MIPSDisassembler>>setOnLessThan: (in category 'instructions - arithmetic') ----- + setOnLessThan: instruction + ^'slt ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (MIPSConstants nameForRegister: instruction rt)! Item was added: + ----- Method: MIPSDisassembler>>setOnLessThanImmediate: (in category 'instructions - arithmetic') ----- + setOnLessThanImmediate: instruction + ^'slti ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (instruction signedImmediate printString)! Item was added: + ----- Method: MIPSDisassembler>>setOnLessThanImmediateUnsigned: (in category 'instructions - arithmetic') ----- + setOnLessThanImmediateUnsigned: instruction + "The immediate is still sign-extended; it is the comparison that is unsigned." + ^'sltiu ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (instruction signedImmediate printString) ! Item was added: + ----- Method: MIPSDisassembler>>setOnLessThanUnsigned: (in category 'instructions - arithmetic') ----- + setOnLessThanUnsigned: instruction + ^'sltu ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (MIPSConstants nameForRegister: instruction rt)! Item was added: + ----- Method: MIPSDisassembler>>shiftLeftLogical: (in category 'instructions - arithmetic') ----- + shiftLeftLogical: instruction + instruction value = 0 ifTrue: [^'nop']. + ^'sll ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rt), ', ', + instruction sa printString! Item was added: + ----- Method: MIPSDisassembler>>shiftLeftLogicalVariable: (in category 'instructions - arithmetic') ----- + shiftLeftLogicalVariable: instruction + ^'sllv ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (MIPSConstants nameForRegister: instruction rs)! Item was added: + ----- Method: MIPSDisassembler>>shiftRightArithmetic: (in category 'instructions - arithmetic') ----- + shiftRightArithmetic: instruction + ^'sra ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rt), ', ', + instruction sa printString! Item was added: + ----- Method: MIPSDisassembler>>shiftRightArithmeticVariable: (in category 'instructions - arithmetic') ----- + shiftRightArithmeticVariable: instruction + ^'srav ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (MIPSConstants nameForRegister: instruction rs)! Item was added: + ----- Method: MIPSDisassembler>>shiftRightLogical: (in category 'instructions - arithmetic') ----- + shiftRightLogical: instruction + ^'srl ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rt), ', ', + instruction sa printString! Item was added: + ----- Method: MIPSDisassembler>>shiftRightLogicalVariable: (in category 'instructions - arithmetic') ----- + shiftRightLogicalVariable: instruction + ^'srlv ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (MIPSConstants nameForRegister: instruction rs)! Item was added: + ----- Method: MIPSDisassembler>>storeByte: (in category 'instructions - memory') ----- + storeByte: instruction + ^'sb ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (instruction signedImmediate printString), '(', + (MIPSConstants nameForRegister: instruction rs), ')'! Item was added: + ----- Method: MIPSDisassembler>>storeHalfword: (in category 'instructions - memory') ----- + storeHalfword: instruction + ^'sh ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (instruction signedImmediate printString), '(', + (MIPSConstants nameForRegister: instruction rs), ')'! Item was added: + ----- Method: MIPSDisassembler>>storeWord: (in category 'instructions - memory') ----- + storeWord: instruction + ^'sw ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (instruction signedImmediate printString), '(', + (MIPSConstants nameForRegister: instruction rs), ')'! Item was added: + ----- Method: MIPSDisassembler>>subtractUnsigned: (in category 'instructions - arithmetic') ----- + subtractUnsigned: instruction + ^'subu ', + (MIPSConstants nameForRegister: instruction rd), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (MIPSConstants nameForRegister: instruction rt)! Item was added: + ----- Method: MIPSDisassembler>>xorImmediate: (in category 'instructions - arithmetic') ----- + xorImmediate: instruction + ^'xori ', + (MIPSConstants nameForRegister: instruction rt), ', ', + (MIPSConstants nameForRegister: instruction rs), ', ', + (instruction unsignedImmediate printString)! Item was added: + MIPSSimulator subclass: #MIPSELSimulator + instanceVariableNames: '' + classVariableNames: '' + poolDictionaries: '' + category: 'Cog-Processors'! + + !MIPSELSimulator commentStamp: 'rmacnak 11/11/2015 20:33:13' prior: 0! + Simulator for little-endian 32-bit MIPS.! Item was added: + ----- Method: MIPSELSimulator>>signedByte: (in category 'as yet unclassified') ----- + signedByte: address + ^memory signedByteAt: address + 1! Item was added: + ----- Method: MIPSELSimulator>>signedByte:put: (in category 'memory') ----- + signedByte: address put: value + ^memory signedByteAt: address + 1 put: value! Item was added: + ----- Method: MIPSELSimulator>>signedHalfword: (in category 'as yet unclassified') ----- + signedHalfword: address + (address bitAnd: 1) = 0 ifFalse: [self error: 'Unaligned read']. + ^memory signedShortAt: address + 1! Item was added: + ----- Method: MIPSELSimulator>>signedHalfword:put: (in category 'memory') ----- + signedHalfword: address put: value + (address bitAnd: 1) = 0 ifFalse: [self error: 'Unaligned read']. + ^memory signedShortAt: address + 1 put: value! Item was added: + ----- Method: MIPSELSimulator>>signedWord: (in category 'as yet unclassified') ----- + signedWord: address + (address bitAnd: 3) = 0 ifFalse: [self error: 'Unaligned read']. + ^memory signedLongAt: address + 1! Item was added: + ----- Method: MIPSELSimulator>>signedWord:put: (in category 'memory') ----- + signedWord: address put: value + (address bitAnd: 3) = 0 ifFalse: [self error: 'Unaligned read']. + ^memory signedLongAt: address + 1 put: value! Item was added: + ----- Method: MIPSELSimulator>>snsignedWord: (in category 'as yet unclassified') ----- + snsignedWord: address + (address bitAnd: 3) = 0 ifFalse: [self error: 'Unaligned read']. + ^memory unsignedLongAt: address + 1 bigEndian: false! Item was added: + ----- Method: MIPSELSimulator>>unsignedByte: (in category 'as yet unclassified') ----- + unsignedByte: address + ^memory at: address + 1! Item was added: + ----- Method: MIPSELSimulator>>unsignedByte:put: (in category 'memory') ----- + unsignedByte: address put: value + ^memory at: address + 1 put: value! Item was added: + ----- Method: MIPSELSimulator>>unsignedHalfword: (in category 'as yet unclassified') ----- + unsignedHalfword: address + (address bitAnd: 1) = 0 ifFalse: [self error: 'Unaligned read']. + ^memory unsignedShortAt: address + 1 bigEndian: false! Item was added: + ----- Method: MIPSELSimulator>>unsignedHalfword:put: (in category 'memory') ----- + unsignedHalfword: address put: value + (address bitAnd: 1) = 0 ifFalse: [self error: 'Unaligned read']. + ^memory unsignedShortAt: address + 1 put: value! Item was added: + ----- Method: MIPSELSimulator>>unsignedWord: (in category 'as yet unclassified') ----- + unsignedWord: address + (address bitAnd: 3) = 0 ifFalse: [self error: 'Unaligned read']. + ^memory unsignedLongAt: address + 1 bigEndian: false! Item was added: + TestCase subclass: #MIPSELSimulatorTests + instanceVariableNames: '' + classVariableNames: '' + poolDictionaries: 'MIPSConstants' + category: 'Cog-Processors-Tests'! Item was added: + ----- Method: MIPSELSimulatorTests>>testAddiu (in category 'tests - arithmetic') ----- + testAddiu + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: 42). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 2402002A addiu v0, zr, 42 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 42].! Item was added: + ----- Method: MIPSELSimulatorTests>>testAddiuNegative (in category 'tests - arithmetic') ----- + testAddiuNegative + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: -42). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 2402FFD6 addiu v0, zr, -42 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: -42].! Item was added: + ----- Method: MIPSELSimulatorTests>>testAddiuOverflow (in category 'tests - arithmetic') ----- + testAddiuOverflow + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler luiR: T0 C: 16r7FFF). + stream nextPut: (compiler oriR: T0 R: T0 C: 16rFFFF). + stream nextPut: (compiler addiuR: V0 R: T0 C: 1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 3C087FFF lui t0, 32767 + 00000004 3508FFFF ori t0, t0, 65535 + 00000008 25020001 addiu v0, t0, 1 + 0000000C 03E00008 jr ra + 00000010 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: -1 << 31].! Item was added: + ----- Method: MIPSELSimulatorTests>>testAddiuUnderflow (in category 'tests - arithmetic') ----- + testAddiuUnderflow + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler luiR: T0 C: 16r8000). + stream nextPut: (compiler addiuR: V0 R: T0 C: -1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 3C088000 lui t0, -32768 + 00000004 2502FFFF addiu v0, t0, -1 + 00000008 03E00008 jr ra + 0000000C 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: (1 << 31) - 1].! Item was added: + ----- Method: MIPSELSimulatorTests>>testAddu (in category 'tests - arithmetic') ----- + testAddu + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler adduR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00851021 addu v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 3 with: 4 with: 0 with: 0. + self assert: result equals: 7. + result := simulator call: 0 with: 3 with: -4 with: 0 with: 0. + self assert: result equals: -1. + result := simulator call: 0 with: -3 with: 4 with: 0 with: 0. + self assert: result equals: 1. + result := simulator call: 0 with: 16r7FFFFFFF with: 1 with: 0 with: 0. + self assert: result equals: (-1 << 31). + result := simulator call: 0 with: (-1 << 31) with: -1 with: 0 with: 0. + self assert: result equals: (1 << 31) - 1].! Item was added: + ----- Method: MIPSELSimulatorTests>>testAnd (in category 'tests - arithmetic') ----- + testAnd + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler andR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00851024 and v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 2r1101 with: 2r1011 with: 0 with: 0. + self assert: result equals: 2r1001. + result := simulator call: 0 with: -1 with: 42 with: 0 with: 0. + self assert: result equals: 42].! Item was added: + ----- Method: MIPSELSimulatorTests>>testAndi (in category 'tests - arithmetic') ----- + testAndi + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler andiR: V0 R: A0 C: 16rFF). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 308200FF andi v0, a0, 255 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 16r12345678 with: 0 with: 0 with: 0. + self assert: result equals: 16r78. + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 16rFF].! Item was added: + ----- Method: MIPSELSimulatorTests>>testAndiNegative (in category 'tests - arithmetic') ----- + testAndiNegative + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler andiR: V0 R: A0 C: -1). "Immediate is zero-extended, so same as 16rFFFF" + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 3082FFFF andi v0, a0, 65535 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 16r12345678 with: 0 with: 0 with: 0. + self assert: result equals: 16r5678. + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 16rFFFF].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBeq (in category 'tests - control') ----- + testBeq + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). + stream nextPut: (compiler beqR: A0 R: A1 offset: 8). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 24020004 addiu v0, zr, 4 + 00000004 10850002 beq a0, a1, +8 ; =10 + 00000008 00000000 nop + 0000000C 24020003 addiu v0, zr, 3 + 00000010 03E00008 jr ra + 00000014 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 4. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBeqDelaySlot (in category 'tests - control') ----- + testBeqDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler beqR: A0 R: A1 offset: 8). + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 10850002 beq a0, a1, +8 ; =C + 00000004 24020003 addiu v0, zr, 3 + 00000008 24420004 addiu v0, v0, 4 + 0000000C 03E00008 jr ra + 00000010 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 7].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBgez (in category 'tests - control') ----- + testBgez + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). + stream nextPut: (compiler bgezR: A0 offset: 8). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 24020004 addiu v0, zr, 4 + 00000004 04810002 bgez a0, +8 ; =10 + 00000008 00000000 nop + 0000000C 24020003 addiu v0, zr, 3 + 00000010 03E00008 jr ra + 00000014 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 4. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 4].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBgezDelaySlot (in category 'tests - control') ----- + testBgezDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler bgezR: A0 offset: 8). + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 04810002 bgez a0, +8 ; =C + 00000004 24020004 addiu v0, zr, 4 + 00000008 24020003 addiu v0, zr, 3 + 0000000C 03E00008 jr ra + 00000010 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 4. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 4].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBgtz (in category 'tests - control') ----- + testBgtz + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). + stream nextPut: (compiler bgtzR: A0 offset: 8). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 24020004 addiu v0, zr, 4 + 00000004 1C800002 bgtz a0, +8 ; =10 + 00000008 00000000 nop + 0000000C 24020003 addiu v0, zr, 3 + 00000010 03E00008 jr ra + 00000014 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 4].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBgtzDelaySlot (in category 'tests - control') ----- + testBgtzDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler bgtzR: A0 offset: 8). + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 1C800002 bgtz a0, +8 ; =C + 00000004 24020004 addiu v0, zr, 4 + 00000008 24020003 addiu v0, zr, 3 + 0000000C 03E00008 jr ra + 00000010 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 4].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBlez (in category 'tests - control') ----- + testBlez + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). + stream nextPut: (compiler blezR: A0 offset: 8). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 24020004 addiu v0, zr, 4 + 00000004 18800002 blez a0, +8 ; =10 + 00000008 00000000 nop + 0000000C 24020003 addiu v0, zr, 3 + 00000010 03E00008 jr ra + 00000014 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 4. + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 4. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBlezDelaySlot (in category 'tests - control') ----- + testBlezDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler blezR: A0 offset: 8). + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 18800002 blez a0, +8 ; =C + 00000004 24020004 addiu v0, zr, 4 + 00000008 24020003 addiu v0, zr, 3 + 0000000C 03E00008 jr ra + 00000010 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 4. + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 4. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBltz (in category 'tests - control') ----- + testBltz + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). + stream nextPut: (compiler bltzR: A0 offset: 8). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 24020004 addiu v0, zr, 4 + 00000004 04800002 bltz a0, +8 ; =10 + 00000008 00000000 nop + 0000000C 24020003 addiu v0, zr, 3 + 00000010 03E00008 jr ra + 00000014 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 4. + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBltzDelaySlot (in category 'tests - control') ----- + testBltzDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler bltzR: A0 offset: 8). + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 04800002 bltz a0, +8 ; =C + 00000004 24020004 addiu v0, zr, 4 + 00000008 24020003 addiu v0, zr, 3 + 0000000C 03E00008 jr ra + 00000010 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: 4. + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBne (in category 'tests - control') ----- + testBne + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). + stream nextPut: (compiler bneR: A0 R: A1 offset: 8). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 24020004 addiu v0, zr, 4 + 00000004 14850002 bne a0, a1, +8 ; =10 + 00000008 00000000 nop + 0000000C 24020003 addiu v0, zr, 3 + 00000010 03E00008 jr ra + 00000014 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 3. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 4].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBneDelaySlot (in category 'tests - control') ----- + testBneDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler bneR: A0 R: A1 offset: 8). + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 14850002 bne a0, a1, +8 ; =C + 00000004 24020003 addiu v0, zr, 3 + 00000008 24420004 addiu v0, v0, 4 + 0000000C 03E00008 jr ra + 00000010 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 7. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testBreak (in category 'tests - control') ----- + testBreak + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler break: 0)] + disassembly: + '00000000 0000000D break + ' run: + [:simulator | + self should: [simulator call: 0 with: 0 with: 0 with: 0 with: 0] raise: Error].! Item was added: + ----- Method: MIPSELSimulatorTests>>testGenerateInto:disassembly:run: (in category 'execution') ----- + testGenerateInto: generateBlock disassembly: expectedDisassembly run: executeBlock + | actualDisassembly compiler memory stopInstr instructions simulator | + MIPSConstants initialize. + compiler := CogMIPSELCompiler new. + + stopInstr := compiler stop. + memory := ByteArray new: 1024. + 1 to: 1024 by: 4 do: + [:i | memory unsignedLongAt: i put: stopInstr bigEndian: false]. + + instructions := Array streamContents: [:stream | generateBlock value: stream value: compiler]. + instructions withIndexDo: + [:instr :i | memory unsignedLongAt: (4 * (i - 1)) + 1 put: instr bigEndian: false]. + + actualDisassembly := MIPSDisassembler new disassemble: memory from: 0 to: instructions size * 4. + self assert: actualDisassembly equals: expectedDisassembly. + + simulator := MIPSELSimulator new initializeWithMemory: memory. + executeBlock value: simulator.! Item was added: + ----- Method: MIPSELSimulatorTests>>testJ (in category 'tests - control') ----- + testJ + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler jA: 16r10). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 24020003 addiu v0, zr, 3 + 00000004 08000004 j 10 + 00000008 00000000 nop + 0000000C 24420004 addiu v0, v0, 4 + 00000010 03E00008 jr ra + 00000014 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testJDelaySlot (in category 'tests - control') ----- + testJDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler jA: 16rC). + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 08000003 j C + 00000004 24020003 addiu v0, zr, 3 + 00000008 24420004 addiu v0, v0, 4 + 0000000C 03E00008 jr ra + 00000010 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testJal (in category 'tests - control') ----- + testJal + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: T0 R: RA C: 0). + stream nextPut: (compiler jalA: 16r1C). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 3). + stream nextPut: (compiler jR: T0). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler stop). + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 27E80000 addiu t0, ra, 0 + 00000004 0C000007 jal 1C + 00000008 00000000 nop + 0000000C 24420003 addiu v0, v0, 3 + 00000010 01000008 jr t0 + 00000014 00000000 nop + 00000018 0000000D break + 0000001C 24020004 addiu v0, zr, 4 + 00000020 03E00008 jr ra + 00000024 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 7].! Item was added: + ----- Method: MIPSELSimulatorTests>>testJalDelaySlot (in category 'tests - control') ----- + testJalDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: T0 R: RA C: 0). + stream nextPut: (compiler jalA: 16r1C). + stream nextPut: (compiler addiuR: V0 R: ZR C: 11). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 3). + stream nextPut: (compiler jR: T0). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler stop). + stream nextPut: (compiler addiuR: V0 R: V0 C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 27E80000 addiu t0, ra, 0 + 00000004 0C000007 jal 1C + 00000008 2402000B addiu v0, zr, 11 + 0000000C 24420003 addiu v0, v0, 3 + 00000010 01000008 jr t0 + 00000014 00000000 nop + 00000018 0000000D break + 0000001C 24420004 addiu v0, v0, 4 + 00000020 03E00008 jr ra + 00000024 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 18].! Item was added: + ----- Method: MIPSELSimulatorTests>>testJalr (in category 'tests - control') ----- + testJalr + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: T0 R: RA C: 0). + stream nextPut: (compiler addiuR: T9 R: ZR C: 16r20). + stream nextPut: (compiler jalR: T9). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 3). + stream nextPut: (compiler jR: T0). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler stop). + stream nextPut: (compiler addiuR: V0 R: ZR C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 27E80000 addiu t0, ra, 0 + 00000004 24190020 addiu t9, zr, 32 + 00000008 0320F809 jalr t9 + 0000000C 00000000 nop + 00000010 24420003 addiu v0, v0, 3 + 00000014 01000008 jr t0 + 00000018 00000000 nop + 0000001C 0000000D break + 00000020 24020004 addiu v0, zr, 4 + 00000024 03E00008 jr ra + 00000028 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 7].! Item was added: + ----- Method: MIPSELSimulatorTests>>testJalrDelaySlot (in category 'tests - control') ----- + testJalrDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: T0 R: RA C: 0). + stream nextPut: (compiler addiuR: T9 R: ZR C: 16r20). + stream nextPut: (compiler jalR: T9). + stream nextPut: (compiler addiuR: V0 R: ZR C: 11). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 3). + stream nextPut: (compiler jR: T0). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler stop). + stream nextPut: (compiler addiuR: V0 R: V0 C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 27E80000 addiu t0, ra, 0 + 00000004 24190020 addiu t9, zr, 32 + 00000008 0320F809 jalr t9 + 0000000C 2402000B addiu v0, zr, 11 + 00000010 24420003 addiu v0, v0, 3 + 00000014 01000008 jr t0 + 00000018 00000000 nop + 0000001C 0000000D break + 00000020 24420004 addiu v0, v0, 4 + 00000024 03E00008 jr ra + 00000028 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 18].! Item was added: + ----- Method: MIPSELSimulatorTests>>testJr (in category 'tests - control') ----- + testJr + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). + stream nextPut: (compiler addiuR: T9 R: ZR C: 16r14). + stream nextPut: (compiler jR: T9). + stream nextPut: (compiler nop). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 24020003 addiu v0, zr, 3 + 00000004 24190014 addiu t9, zr, 20 + 00000008 03200008 jr t9 + 0000000C 00000000 nop + 00000010 24420004 addiu v0, v0, 4 + 00000014 03E00008 jr ra + 00000018 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testJrDelaySlot (in category 'tests - control') ----- + testJrDelaySlot + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler addiuR: T9 R: ZR C: 16r10). + stream nextPut: (compiler jR: T9). + stream nextPut: (compiler addiuR: V0 R: ZR C: 3). "Delay slot" + stream nextPut: (compiler addiuR: V0 R: V0 C: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 24190010 addiu t9, zr, 16 + 00000004 03200008 jr t9 + 00000008 24020003 addiu v0, zr, 3 + 0000000C 24420004 addiu v0, v0, 4 + 00000010 03E00008 jr ra + 00000014 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 3].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLb (in category 'tests - memory') ----- + testLb + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lbR: V0 base: A0 offset: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 80820004 lb v0, 4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE0 with: 0 with: 0 with: 0. + self assert: result equals: 42. + result := simulator call: 0 with: 16rE1 with: 0 with: 0 with: 0. + self assert: result equals: 43. + result := simulator call: 0 with: 16rE2 with: 0 with: 0 with: 0. + self assert: result equals: 44. + result := simulator call: 0 with: 16rE3 with: 0 with: 0 with: 0. + self assert: result equals: 45. + result := simulator call: 0 with: 16rF0 with: 0 with: 0 with: 0. + self assert: result equals: -42. + result := simulator call: 0 with: 16rF1 with: 0 with: 0 with: 0. + self assert: result equals: -43. + result := simulator call: 0 with: 16rF2 with: 0 with: 0 with: 0. + self assert: result equals: -44. + result := simulator call: 0 with: 16rF3 with: 0 with: 0 with: 0. + self assert: result equals: -45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLbNegativeOffset (in category 'tests - memory') ----- + testLbNegativeOffset + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lbR: V0 base: A0 offset: -4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 8082FFFC lb v0, -4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE8 with: 0 with: 0 with: 0. + self assert: result equals: 42. + result := simulator call: 0 with: 16rE9 with: 0 with: 0 with: 0. + self assert: result equals: 43. + result := simulator call: 0 with: 16rEA with: 0 with: 0 with: 0. + self assert: result equals: 44. + result := simulator call: 0 with: 16rEB with: 0 with: 0 with: 0. + self assert: result equals: 45. + result := simulator call: 0 with: 16rF8 with: 0 with: 0 with: 0. + self assert: result equals: -42. + result := simulator call: 0 with: 16rF9 with: 0 with: 0 with: 0. + self assert: result equals: -43. + result := simulator call: 0 with: 16rFA with: 0 with: 0 with: 0. + self assert: result equals: -44. + result := simulator call: 0 with: 16rFB with: 0 with: 0 with: 0. + self assert: result equals: -45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLbu (in category 'tests - memory') ----- + testLbu + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lbuR: V0 base: A0 offset: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 90820004 lbu v0, 4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE0 with: 0 with: 0 with: 0. + self assert: result equals: 42. + result := simulator call: 0 with: 16rE1 with: 0 with: 0 with: 0. + self assert: result equals: 43. + result := simulator call: 0 with: 16rE2 with: 0 with: 0 with: 0. + self assert: result equals: 44. + result := simulator call: 0 with: 16rE3 with: 0 with: 0 with: 0. + self assert: result equals: 45. + result := simulator call: 0 with: 16rF0 with: 0 with: 0 with: 0. + self assert: result equals: 16r100 - 42. + result := simulator call: 0 with: 16rF1 with: 0 with: 0 with: 0. + self assert: result equals: 16r100 - 43. + result := simulator call: 0 with: 16rF2 with: 0 with: 0 with: 0. + self assert: result equals: 16r100 - 44. + result := simulator call: 0 with: 16rF3 with: 0 with: 0 with: 0. + self assert: result equals: 16r100 - 45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLbuNegativeOffset (in category 'tests - memory') ----- + testLbuNegativeOffset + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lbuR: V0 base: A0 offset: -4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 9082FFFC lbu v0, -4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE8 with: 0 with: 0 with: 0. + self assert: result equals: 42. + result := simulator call: 0 with: 16rE9 with: 0 with: 0 with: 0. + self assert: result equals: 43. + result := simulator call: 0 with: 16rEA with: 0 with: 0 with: 0. + self assert: result equals: 44. + result := simulator call: 0 with: 16rEB with: 0 with: 0 with: 0. + self assert: result equals: 45. + result := simulator call: 0 with: 16rF8 with: 0 with: 0 with: 0. + self assert: result equals: 16r100 - 42. + result := simulator call: 0 with: 16rF9 with: 0 with: 0 with: 0. + self assert: result equals: 16r100 - 43. + result := simulator call: 0 with: 16rFA with: 0 with: 0 with: 0. + self assert: result equals: 16r100 - 44. + result := simulator call: 0 with: 16rFB with: 0 with: 0 with: 0. + self assert: result equals: 16r100 - 45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLh (in category 'tests - memory') ----- + testLh + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lhR: V0 base: A0 offset: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 84820004 lh v0, 4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE0 with: 0 with: 0 with: 0. + self assert: result equals: 16r2B2A. + self should: [simulator call: 0 with: 16rE1 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rE2 with: 0 with: 0 with: 0. + self assert: result equals: 16r2D2C. + self should: [simulator call: 0 with: 16rE3 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rF0 with: 0 with: 0 with: 0. + self assert: result equals: -16r2A2A. + self should: [simulator call: 0 with: 16rF1 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rF2 with: 0 with: 0 with: 0. + self assert: result equals: -16r2C2C. + self should: [simulator call: 0 with: 16rF3 with: 0 with: 0 with: 0] raise: Error].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLhNegativeOffset (in category 'tests - memory') ----- + testLhNegativeOffset + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lhR: V0 base: A0 offset: -4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 8482FFFC lh v0, -4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE8 with: 0 with: 0 with: 0. + self assert: result equals: 16r2B2A. + self should: [simulator call: 0 with: 16rE9 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rEA with: 0 with: 0 with: 0. + self assert: result equals: 16r2D2C. + self should: [simulator call: 0 with: 16rEB with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rF8 with: 0 with: 0 with: 0. + self assert: result equals: -16r2A2A. + self should: [simulator call: 0 with: 16rF9 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rFA with: 0 with: 0 with: 0. + self assert: result equals: -16r2C2C. + self should: [simulator call: 0 with: 16rFB with: 0 with: 0 with: 0] raise: Error].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLhu (in category 'tests - memory') ----- + testLhu + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lhuR: V0 base: A0 offset: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 94820004 lhu v0, 4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE0 with: 0 with: 0 with: 0. + self assert: result equals: 16r2B2A. + self should: [simulator call: 0 with: 16rE1 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rE2 with: 0 with: 0 with: 0. + self assert: result equals: 16r2D2C. + self should: [simulator call: 0 with: 16rE3 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rF0 with: 0 with: 0 with: 0. + self assert: result equals: 16rD5D6. + self should: [simulator call: 0 with: 16rF1 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rF2 with: 0 with: 0 with: 0. + self assert: result equals: 16rD3D4. + self should: [simulator call: 0 with: 16rF3 with: 0 with: 0 with: 0] raise: Error].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLhuNegativeOffset (in category 'tests - memory') ----- + testLhuNegativeOffset + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lhuR: V0 base: A0 offset: -4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 9482FFFC lhu v0, -4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE8 with: 0 with: 0 with: 0. + self assert: result equals: 16r2B2A. + self should: [simulator call: 0 with: 16rE9 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rEA with: 0 with: 0 with: 0. + self assert: result equals: 16r2D2C. + self should: [simulator call: 0 with: 16rEB with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rF8 with: 0 with: 0 with: 0. + self assert: result equals: 16rD5D6. + self should: [simulator call: 0 with: 16rF9 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rFA with: 0 with: 0 with: 0. + self assert: result equals: 16rD3D4. + self should: [simulator call: 0 with: 16rFB with: 0 with: 0 with: 0] raise: Error].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLoadLargeLiteral (in category 'tests - arithmetic') ----- + testLoadLargeLiteral + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler luiR: V0 C: 16r3FFF). + stream nextPut: (compiler oriR: V0 R: V0 C: 16rFFFF). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 3C023FFF lui v0, 16383 + 00000004 3442FFFF ori v0, v0, 65535 + 00000008 03E00008 jr ra + 0000000C 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 16r3FFFFFFF].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLui (in category 'tests - arithmetic') ----- + testLui + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler luiR: V0 C: 42). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 3C02002A lui v0, 42 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 42 << 16].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLuiNegative (in category 'tests - arithmetic') ----- + testLuiNegative + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler luiR: V0 C: -42). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 3C02FFD6 lui v0, -42 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: -42 << 16].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLw (in category 'tests - memory') ----- + testLw + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lwR: V0 base: A0 offset: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 8C820004 lw v0, 4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE0 with: 0 with: 0 with: 0. + self assert: result equals: 16r2D2C2B2A. + self should: [simulator call: 0 with: 16rE1 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rE2 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rE3 with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rF0 with: 0 with: 0 with: 0. + self assert: result equals: -16r2C2B2A2A. + self should: [simulator call: 0 with: 16rF1 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rF2 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rF3 with: 0 with: 0 with: 0] raise: Error].! Item was added: + ----- Method: MIPSELSimulatorTests>>testLwNegativeOffset (in category 'tests - memory') ----- + testLwNegativeOffset + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler lwR: V0 base: A0 offset: -4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 8C82FFFC lw v0, -4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator memory at: 16rE4 + 1 put: 42. + simulator memory at: 16rE5 + 1 put: 43. + simulator memory at: 16rE6 + 1 put: 44. + simulator memory at: 16rE7 + 1 put: 45. + simulator memory at: 16rF4 + 1 put: 16r100 - 42. + simulator memory at: 16rF5 + 1 put: 16r100 - 43. + simulator memory at: 16rF6 + 1 put: 16r100 - 44. + simulator memory at: 16rF7 + 1 put: 16r100 - 45. + result := simulator call: 0 with: 16rE8 with: 0 with: 0 with: 0. + self assert: result equals: 16r2D2C2B2A. + self should: [simulator call: 0 with: 16rE9 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rEA with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rEB with: 0 with: 0 with: 0] raise: Error. + result := simulator call: 0 with: 16rF8 with: 0 with: 0 with: 0. + self assert: result equals: -16r2C2B2A2A. + self should: [simulator call: 0 with: 16rF9 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rFA with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rFB with: 0 with: 0 with: 0] raise: Error].! Item was added: + ----- Method: MIPSELSimulatorTests>>testOr (in category 'tests - arithmetic') ----- + testOr + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler orR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00851025 or v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 2r101 with: 2r011 with: 0 with: 0. + self assert: result equals: 2r111. + result := simulator call: 0 with: -1 with: 42 with: 0 with: 0. + self assert: result equals: -1].! Item was added: + ----- Method: MIPSELSimulatorTests>>testOri (in category 'tests - arithmetic') ----- + testOri + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler oriR: V0 R: ZR C: 16rFFFF). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 3402FFFF ori v0, zr, 65535 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 16rFFFF].! Item was added: + ----- Method: MIPSELSimulatorTests>>testOriNegative (in category 'tests - arithmetic') ----- + testOriNegative + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler oriR: V0 R: ZR C: -42). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 3402FFD6 ori v0, zr, 65494 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0. + self assert: result equals: 16r10000 - 42].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSb (in category 'tests - memory') ----- + testSb + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sbR: A1 base: A0 offset: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 A0850004 sb a1, 4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator call: 0 with: 16rE0 with: 42 with: 0 with: 0. + simulator call: 0 with: 16rE1 with: 43 with: 0 with: 0. + simulator call: 0 with: 16rE2 with: 44 with: 0 with: 0. + simulator call: 0 with: 16rE3 with: 45 with: 0 with: 0. + simulator call: 0 with: 16rF0 with: -42 with: 0 with: 0. + simulator call: 0 with: 16rF1 with: -43 with: 0 with: 0. + simulator call: 0 with: 16rF2 with: -44 with: 0 with: 0. + simulator call: 0 with: 16rF3 with: -45 with: 0 with: 0. + self assert: (simulator memory at: 16rE4 + 1) equals: 42. + self assert: (simulator memory at: 16rE5 + 1) equals: 43. + self assert: (simulator memory at: 16rE6 + 1) equals: 44. + self assert: (simulator memory at: 16rE7 + 1) equals: 45. + self assert: (simulator memory at: 16rF4 + 1) equals: 16r100 - 42. + self assert: (simulator memory at: 16rF5 + 1) equals: 16r100 - 43. + self assert: (simulator memory at: 16rF6 + 1) equals: 16r100 - 44. + self assert: (simulator memory at: 16rF7 + 1) equals: 16r100 - 45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSbNegativeOffset (in category 'tests - memory') ----- + testSbNegativeOffset + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sbR: A1 base: A0 offset: -4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 A085FFFC sb a1, -4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator call: 0 with: 16rE8 with: 42 with: 0 with: 0. + simulator call: 0 with: 16rE9 with: 43 with: 0 with: 0. + simulator call: 0 with: 16rEA with: 44 with: 0 with: 0. + simulator call: 0 with: 16rEB with: 45 with: 0 with: 0. + simulator call: 0 with: 16rF8 with: -42 with: 0 with: 0. + simulator call: 0 with: 16rF9 with: -43 with: 0 with: 0. + simulator call: 0 with: 16rFA with: -44 with: 0 with: 0. + simulator call: 0 with: 16rFB with: -45 with: 0 with: 0. + self assert: (simulator memory at: 16rE4 + 1) equals: 42. + self assert: (simulator memory at: 16rE5 + 1) equals: 43. + self assert: (simulator memory at: 16rE6 + 1) equals: 44. + self assert: (simulator memory at: 16rE7 + 1) equals: 45. + self assert: (simulator memory at: 16rF4 + 1) equals: 16r100 - 42. + self assert: (simulator memory at: 16rF5 + 1) equals: 16r100 - 43. + self assert: (simulator memory at: 16rF6 + 1) equals: 16r100 - 44. + self assert: (simulator memory at: 16rF7 + 1) equals: 16r100 - 45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSh (in category 'tests - memory') ----- + testSh + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler shR: A1 base: A0 offset: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 A4850004 sh a1, 4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator call: 0 with: 16rE0 with: 16r2B2A with: 0 with: 0. + self should: [simulator call: 0 with: 16rE1 with: 0 with: 0 with: 0] raise: Error. + simulator call: 0 with: 16rE2 with: 16r2D2C with: 0 with: 0. + self should: [simulator call: 0 with: 16rE3 with: 0 with: 0 with: 0] raise: Error. + simulator call: 0 with: 16rF0 with: -16r2A2A with: 0 with: 0. + self should: [simulator call: 0 with: 16rF1 with: 0 with: 0 with: 0] raise: Error. + simulator call: 0 with: 16rF2 with: -16r2C2C with: 0 with: 0. + self should: [simulator call: 0 with: 16rF3 with: 0 with: 0 with: 0] raise: Error. + self assert: (simulator memory at: 16rE4 + 1) equals: 42. + self assert: (simulator memory at: 16rE5 + 1) equals: 43. + self assert: (simulator memory at: 16rE6 + 1) equals: 44. + self assert: (simulator memory at: 16rE7 + 1) equals: 45. + self assert: (simulator memory at: 16rF4 + 1) equals: 16r100 - 42. + self assert: (simulator memory at: 16rF5 + 1) equals: 16r100 - 43. + self assert: (simulator memory at: 16rF6 + 1) equals: 16r100 - 44. + self assert: (simulator memory at: 16rF7 + 1) equals: 16r100 - 45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testShNegativeOffset (in category 'tests - memory') ----- + testShNegativeOffset + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler shR: A1 base: A0 offset: -4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 A485FFFC sh a1, -4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator call: 0 with: 16rE8 with: 16r2B2A with: 0 with: 0. + self should: [simulator call: 0 with: 16rE9 with: 0 with: 0 with: 0] raise: Error. + simulator call: 0 with: 16rEA with: 16r2D2C with: 0 with: 0. + self should: [simulator call: 0 with: 16rEB with: 0 with: 0 with: 0] raise: Error. + simulator call: 0 with: 16rF8 with: -16r2A2A with: 0 with: 0. + self should: [simulator call: 0 with: 16rF9 with: 0 with: 0 with: 0] raise: Error. + simulator call: 0 with: 16rFA with: -16r2C2C with: 0 with: 0. + self should: [simulator call: 0 with: 16rFB with: 0 with: 0 with: 0] raise: Error. + self assert: (simulator memory at: 16rE4 + 1) equals: 42. + self assert: (simulator memory at: 16rE5 + 1) equals: 43. + self assert: (simulator memory at: 16rE6 + 1) equals: 44. + self assert: (simulator memory at: 16rE7 + 1) equals: 45. + self assert: (simulator memory at: 16rF4 + 1) equals: 16r100 - 42. + self assert: (simulator memory at: 16rF5 + 1) equals: 16r100 - 43. + self assert: (simulator memory at: 16rF6 + 1) equals: 16r100 - 44. + self assert: (simulator memory at: 16rF7 + 1) equals: 16r100 - 45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSll (in category 'tests - arithmetic') ----- + testSll + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sllR: V0 R: A0 C: 2). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00041080 sll v0, a0, 2 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 42 with: 0 with: 0 with: 0. + self assert: result equals: 42 << 2. + result := simulator call: 0 with: -42 with: 0 with: 0 with: 0. + self assert: result equals: -42 << 2].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSllv (in category 'tests - arithmetic') ----- + testSllv + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sllvR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00A41004 sllv v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 42 with: 2 with: 0 with: 0. + self assert: result equals: 42 << 2. + result := simulator call: 0 with: -42 with: 2 with: 0 with: 0. + self assert: result equals: -42 << 2].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSlt (in category 'tests - arithmetic') ----- + testSlt + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sltR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 0085102A slt v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 3 with: 4 with: 0 with: 0. + self assert: result equals: 1. + result := simulator call: 0 with: 4 with: 3 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -3 with: 4 with: 0 with: 0. + self assert: result equals: 1. + result := simulator call: 0 with: 4 with: -3 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: 5 with: 5 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -5 with: -5 with: 0 with: 0. + self assert: result equals: 0].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSlti (in category 'tests - arithmetic') ----- + testSlti + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sltiR: V0 R: A0 C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 28820003 slti v0, a0, 3 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 3 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: 4 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -3 with: 0 with: 0 with: 0. + self assert: result equals: 1].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSltiNegative (in category 'tests - arithmetic') ----- + testSltiNegative + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sltiR: V0 R: A0 C: -3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 2882FFFD slti v0, a0, -3 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 3 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: 4 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -3 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -4 with: 0 with: 0 with: 0. + self assert: result equals: 1].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSltiu (in category 'tests - arithmetic') ----- + testSltiu + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sltiuR: V0 R: A0 C: 3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 2C820003 sltiu v0, a0, 3 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 2 with: 0 with: 0 with: 0. + self assert: result equals: 1. + result := simulator call: 0 with: 3 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: 4 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -3 with: 0 with: 0 with: 0. + self assert: result equals: 0].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSltiuNegative (in category 'tests - arithmetic') ----- + testSltiuNegative + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sltiuR: V0 R: A0 C: -3). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 2C82FFFD sltiu v0, a0, -3 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 2 with: 0 with: 0 with: 0. + self assert: result equals: 1. + result := simulator call: 0 with: 3 with: 0 with: 0 with: 0. + self assert: result equals: 1. + result := simulator call: 0 with: 4 with: 0 with: 0 with: 0. + self assert: result equals: 1. + result := simulator call: 0 with: -2 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -3 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -4 with: 0 with: 0 with: 0. + self assert: result equals: 1].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSltu (in category 'tests - arithmetic') ----- + testSltu + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sltuR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 0085102B sltu v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 3 with: 4 with: 0 with: 0. + self assert: result equals: 1. + result := simulator call: 0 with: 4 with: 3 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -3 with: 4 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: 4 with: -3 with: 0 with: 0. + self assert: result equals: 1. + result := simulator call: 0 with: 5 with: 5 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -5 with: -5 with: 0 with: 0. + self assert: result equals: 0].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSra (in category 'tests - arithmetic') ----- + testSra + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sraR: V0 R: A0 C: 2). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00041083 sra v0, a0, 2 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 42 with: 0 with: 0 with: 0. + self assert: result equals: 42 >> 2. + result := simulator call: 0 with: -42 with: 0 with: 0 with: 0. + self assert: result equals: -42 >> 2].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSrav (in category 'tests - arithmetic') ----- + testSrav + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sravR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00A41007 srav v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 42 with: 2 with: 0 with: 0. + self assert: result equals: 42 >> 2. + result := simulator call: 0 with: -42 with: 2 with: 0 with: 0. + self assert: result equals: -42 >> 2].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSrl (in category 'tests - arithmetic') ----- + testSrl + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler srlR: V0 R: A0 C: 2). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00041082 srl v0, a0, 2 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 42 with: 0 with: 0 with: 0. + self assert: result equals: 42 >> 2. + result := simulator call: 0 with: -42 with: 0 with: 0 with: 0. + self assert: result equals: (16r100000000 - 42) >> 2].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSrlv (in category 'tests - arithmetic') ----- + testSrlv + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler srlvR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00A41006 srlv v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 42 with: 2 with: 0 with: 0. + self assert: result equals: 42 >> 2. + result := simulator call: 0 with: -42 with: 2 with: 0 with: 0. + self assert: result equals: (16r100000000 - 42) >> 2].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSubu (in category 'tests - arithmetic') ----- + testSubu + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler subuR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00851023 subu v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 3 with: 4 with: 0 with: 0. + self assert: result equals: -1. + result := simulator call: 0 with: 3 with: -4 with: 0 with: 0. + self assert: result equals: 7. + result := simulator call: 0 with: -3 with: 4 with: 0 with: 0. + self assert: result equals: -7. + result := simulator call: 0 with: 16r7FFFFFFF with: -1 with: 0 with: 0. + self assert: result equals: (-1 << 31). + result := simulator call: 0 with: (-1 << 31) with: 1 with: 0 with: 0. + self assert: result equals: (1 << 31) - 1].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSw (in category 'tests - memory') ----- + testSw + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler swR: A1 base: A0 offset: 4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 AC850004 sw a1, 4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator call: 0 with: 16rE0 with: 16r2D2C2B2A with: 0 with: 0. + self should: [simulator call: 0 with: 16rE1 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rE2 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rE3 with: 0 with: 0 with: 0] raise: Error. + simulator call: 0 with: 16rF0 with: -16r2C2B2A2A with: 0 with: 0. + self should: [simulator call: 0 with: 16rF1 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rF2 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rF3 with: 0 with: 0 with: 0] raise: Error. + self assert: (simulator memory at: 16rE4 + 1) equals: 42. + self assert: (simulator memory at: 16rE5 + 1) equals: 43. + self assert: (simulator memory at: 16rE6 + 1) equals: 44. + self assert: (simulator memory at: 16rE7 + 1) equals: 45. + self assert: (simulator memory at: 16rF4 + 1) equals: 16r100 - 42. + self assert: (simulator memory at: 16rF5 + 1) equals: 16r100 - 43. + self assert: (simulator memory at: 16rF6 + 1) equals: 16r100 - 44. + self assert: (simulator memory at: 16rF7 + 1) equals: 16r100 - 45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSwNegativeOffset (in category 'tests - memory') ----- + testSwNegativeOffset + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler swR: A1 base: A0 offset: -4). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 AC85FFFC sw a1, -4(a0) + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + simulator call: 0 with: 16rE8 with: 16r2D2C2B2A with: 0 with: 0. + self should: [simulator call: 0 with: 16rE9 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rEA with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rEB with: 0 with: 0 with: 0] raise: Error. + simulator call: 0 with: 16rF8 with: -16r2C2B2A2A with: 0 with: 0. + self should: [simulator call: 0 with: 16rF9 with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rFA with: 0 with: 0 with: 0] raise: Error. + self should: [simulator call: 0 with: 16rFB with: 0 with: 0 with: 0] raise: Error. + self assert: (simulator memory at: 16rE4 + 1) equals: 42. + self assert: (simulator memory at: 16rE5 + 1) equals: 43. + self assert: (simulator memory at: 16rE6 + 1) equals: 44. + self assert: (simulator memory at: 16rE7 + 1) equals: 45. + self assert: (simulator memory at: 16rF4 + 1) equals: 16r100 - 42. + self assert: (simulator memory at: 16rF5 + 1) equals: 16r100 - 43. + self assert: (simulator memory at: 16rF6 + 1) equals: 16r100 - 44. + self assert: (simulator memory at: 16rF7 + 1) equals: 16r100 - 45].! Item was added: + ----- Method: MIPSELSimulatorTests>>testXor (in category 'tests - arithmetic') ----- + testXor + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler xorR: V0 R: A0 R: A1). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 00851026 xor v0, a0, a1 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 2r101 with: 2r011 with: 0 with: 0. + self assert: result equals: 2r110. + result := simulator call: 0 with: -1 with: 42 with: 0 with: 0. + self assert: result equals: 42 bitInvert].! Item was added: + ----- Method: MIPSELSimulatorTests>>testXori (in category 'tests - arithmetic') ----- + testXori + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler xoriR: V0 R: A0 C: 16rABCD). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 3882ABCD xori v0, a0, 43981 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 16rABCD. + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: -16rABCE].! Item was added: + Object subclass: #MIPSInstruction + instanceVariableNames: 'value' + classVariableNames: '' + poolDictionaries: 'MIPSConstants' + category: 'Cog-Processors'! + + !MIPSInstruction commentStamp: 'rmacnak 11/11/2015 20:31:24' prior: 0! + Wrapper for decoding MIPS instructions.! Item was added: + ----- Method: MIPSInstruction>>decodeFor: (in category 'as yet unclassified') ----- + decodeFor: visitor + | opcode | + opcode := self opcode. + opcode = SPECIAL ifTrue: [^self decodeSpecialFor: visitor]. + opcode = REGIMM ifTrue: [^self decodeRegImmFor: visitor]. + + opcode = J ifTrue: [^visitor jump: self]. + opcode = JAL ifTrue: [^visitor jumpAndLink: self]. + opcode = BEQ ifTrue: [^visitor branchEqual: self]. + opcode = BNE ifTrue: [^visitor branchNotEqual: self]. + opcode = BLEZ ifTrue: [^visitor branchLessEqualZero: self]. + opcode = BGTZ ifTrue: [^visitor branchGreaterThanZero: self]. + opcode = ADDIU ifTrue: [^visitor addImmediateUnsigned: self]. + opcode = SLTI ifTrue: [^visitor setOnLessThanImmediate: self]. + opcode = SLTIU ifTrue: [^visitor setOnLessThanImmediateUnsigned: self]. + opcode = ANDI ifTrue: [^visitor andImmediate: self]. + opcode = ORI ifTrue: [^visitor orImmediate: self]. + opcode = XORI ifTrue: [^visitor xorImmediate: self]. + opcode = LUI ifTrue: [^visitor loadUpperImmediate: self]. + opcode = LB ifTrue: [^visitor loadByte: self]. + opcode = LH ifTrue: [^visitor loadHalfword: self]. + opcode = LW ifTrue: [^visitor loadWord: self]. + opcode = LBU ifTrue: [^visitor loadByteUnsigned: self]. + opcode = LHU ifTrue: [^visitor loadHalfwordUnsigned: self]. + opcode = SB ifTrue: [^visitor storeByte: self]. + opcode = SH ifTrue: [^visitor storeHalfword: self]. + opcode = SW ifTrue: [^visitor storeWord: self]. + + self error: 'Unknown instruction'.! Item was added: + ----- Method: MIPSInstruction>>decodeRegImmFor: (in category 'as yet unclassified') ----- + decodeRegImmFor: visitor + | fn | + fn := self rt. + fn = BLTZ ifTrue: [^visitor branchLessThanZero: self]. + fn = BGEZ ifTrue: [^visitor branchGreaterEqualZero: self]. + + self error: 'Unknown instruction'.! Item was added: + ----- Method: MIPSInstruction>>decodeSpecialFor: (in category 'as yet unclassified') ----- + decodeSpecialFor: visitor + | function | + function := self function. + function = SLL ifTrue: [^visitor shiftLeftLogical: self]. + function = SRL ifTrue: [^visitor shiftRightLogical: self]. + function = SRA ifTrue: [^visitor shiftRightArithmetic: self]. + function = SLLV ifTrue: [^visitor shiftLeftLogicalVariable: self]. + function = SRLV ifTrue: [^visitor shiftRightLogicalVariable: self]. + function = SRAV ifTrue: [^visitor shiftRightArithmeticVariable: self]. + function = JR ifTrue: [^visitor jumpRegister: self]. + function = JALR ifTrue: [^visitor jumpAndLinkRegister: self]. + function = BREAK ifTrue: [^visitor break: self]. + function = ADDU ifTrue: [^visitor addUnsigned: self]. + function = SUBU ifTrue: [^visitor subtractUnsigned: self]. + function = AND ifTrue: [^visitor bitwiseAnd: self]. + function = OR ifTrue: [^visitor bitwiseOr: self]. + function = XOR ifTrue: [^visitor bitwiseXor: self]. + function = SLT ifTrue: [^visitor setOnLessThan: self]. + function = SLTU ifTrue: [^visitor setOnLessThanUnsigned: self]. + + self error: 'Unknown instruction'.! Item was added: + ----- Method: MIPSInstruction>>function (in category 'fields') ----- + function + ^value bitAnd: 63! Item was added: + ----- Method: MIPSInstruction>>opcode (in category 'fields') ----- + opcode + ^value >> 26! Item was added: + ----- Method: MIPSInstruction>>rd (in category 'fields') ----- + rd + ^(value >> 11) bitAnd: 31! Item was added: + ----- Method: MIPSInstruction>>rs (in category 'fields') ----- + rs + ^(value >> 21) bitAnd: 31! Item was added: + ----- Method: MIPSInstruction>>rt (in category 'fields') ----- + rt + ^(value >> 16) bitAnd: 31! Item was added: + ----- Method: MIPSInstruction>>sa (in category 'fields') ----- + sa + ^(value >> 6) bitAnd: 15! Item was added: + ----- Method: MIPSInstruction>>signedImmediate (in category 'fields') ----- + signedImmediate + ^self unsigned16ToSigned16: (self unsignedImmediate)! Item was added: + ----- Method: MIPSInstruction>>target (in category 'fields') ----- + target + ^value bitAnd: 16r3FFFFFF! Item was added: + ----- Method: MIPSInstruction>>unsigned16ToSigned16: (in category 'fields') ----- + unsigned16ToSigned16: unsignedValue + self assert: (unsignedValue between: 0 and: 16rFFFF). + unsignedValue >= 16r8000 ifTrue: [^unsignedValue - 16r10000]. + ^unsignedValue! Item was added: + ----- Method: MIPSInstruction>>unsignedImmediate (in category 'fields') ----- + unsignedImmediate + ^value bitAnd: 16rFFFF! Item was added: + ----- Method: MIPSInstruction>>value (in category 'as yet unclassified') ----- + value + ^value! Item was added: + ----- Method: MIPSInstruction>>value: (in category 'as yet unclassified') ----- + value: anInteger + self assert: (anInteger between: 0 and: 16rFFFFFFFF). + value := anInteger! Item was added: + Object subclass: #MIPSSimulator + instanceVariableNames: 'memory registers pc instructionCount inDelaySlot' + classVariableNames: 'EndSimulationPC' + poolDictionaries: 'MIPSConstants' + category: 'Cog-Processors'! + + !MIPSSimulator commentStamp: 'rmacnak 11/11/2015 20:33:00' prior: 0! + Simulator for 32-bit MIPS, without implementation of memory access.! Item was added: + ----- Method: MIPSSimulator class>>initialize (in category 'as yet unclassified') ----- + initialize + super initialize. + EndSimulationPC := 16rABABABAB. + OneInstruction := 4. + TwoInstructions := 8.! Item was added: + ----- Method: MIPSSimulator>>addImmediateUnsigned: (in category 'instructions - arithmetic') ----- + addImmediateUnsigned: instruction + "Unsigned here means the instruction doesn't generate exceptions, + not that the immediate is unsigned." + | rsValue immediate result | + rsValue := self unsignedRegister: instruction rs. + immediate := instruction signedImmediate. + result := rsValue + immediate bitAnd: 16rFFFFFFFF. "No exception on overflow" + self unsignedRegister: instruction rt put: result.! Item was added: + ----- Method: MIPSSimulator>>addUnsigned: (in category 'instructions - arithmetic') ----- + addUnsigned: instruction + "Unsigned here means the instruction doesn't generate exceptions." + | rsValue rtValue result | + rsValue := self unsignedRegister: instruction rs. + rtValue := self unsignedRegister: instruction rt. + result := rsValue + rtValue bitAnd: 16rFFFFFFFF. "No exception on overflow" + self unsignedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>andImmediate: (in category 'instructions - arithmetic') ----- + andImmediate: instruction + | rsValue immediate result | + rsValue := self unsignedRegister: instruction rs. + immediate := instruction unsignedImmediate. + result := rsValue bitAnd: immediate. + self unsignedRegister: instruction rt put: result.! Item was added: + ----- Method: MIPSSimulator>>bitwiseAnd: (in category 'instructions - arithmetic') ----- + bitwiseAnd: instruction + | rsValue rtValue result | + rsValue := self signedRegister: instruction rs. + rtValue := self signedRegister: instruction rt. + result := rsValue bitAnd: rtValue. + self signedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>bitwiseOr: (in category 'instructions - arithmetic') ----- + bitwiseOr: instruction + | rsValue rtValue result | + rsValue := self signedRegister: instruction rs. + rtValue := self signedRegister: instruction rt. + result := rsValue bitOr: rtValue. + self signedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>bitwiseXor: (in category 'instructions - arithmetic') ----- + bitwiseXor: instruction + | rsValue rtValue result | + rsValue := self signedRegister: instruction rs. + rtValue := self signedRegister: instruction rt. + result := rsValue bitXor: rtValue. + self signedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>branchEqual: (in category 'instructions - control') ----- + branchEqual: instruction + | rsValue rtValue | + self assert: inDelaySlot not. + rsValue := self signedRegister: instruction rs. + rtValue := self signedRegister: instruction rt. + self doBranch: rsValue = rtValue offset: instruction signedImmediate << 2.! Item was added: + ----- Method: MIPSSimulator>>branchGreaterEqualZero: (in category 'instructions - control') ----- + branchGreaterEqualZero: instruction + | rsValue | + self assert: inDelaySlot not. + rsValue := self signedRegister: instruction rs. + self doBranch: rsValue >= 0 offset: instruction signedImmediate << 2.! Item was added: + ----- Method: MIPSSimulator>>branchGreaterThanZero: (in category 'instructions - control') ----- + branchGreaterThanZero: instruction + | rsValue | + self assert: inDelaySlot not. + rsValue := self signedRegister: instruction rs. + self doBranch: rsValue > 0 offset: instruction signedImmediate << 2.! Item was added: + ----- Method: MIPSSimulator>>branchLessEqualZero: (in category 'instructions - control') ----- + branchLessEqualZero: instruction + | rsValue | + self assert: inDelaySlot not. + rsValue := self signedRegister: instruction rs. + self doBranch: rsValue <= 0 offset: instruction signedImmediate << 2.! Item was added: + ----- Method: MIPSSimulator>>branchLessThanZero: (in category 'instructions - control') ----- + branchLessThanZero: instruction + | rsValue | + self assert: inDelaySlot not. + rsValue := self signedRegister: instruction rs. + self doBranch: rsValue < 0 offset: instruction signedImmediate << 2.! Item was added: + ----- Method: MIPSSimulator>>branchNotEqual: (in category 'instructions - control') ----- + branchNotEqual: instruction + | rsValue rtValue | + self assert: inDelaySlot not. + rsValue := self signedRegister: instruction rs. + rtValue := self signedRegister: instruction rt. + self doBranch: rsValue ~= rtValue offset: instruction signedImmediate << 2.! Item was added: + ----- Method: MIPSSimulator>>break: (in category 'instructions - control') ----- + break: instruction + self error: 'Break!!'! Item was added: + ----- Method: MIPSSimulator>>call: (in category 'as yet unclassified') ----- + call: entryPC + | zapValue | + zapValue := self unsigned32ToSigned32: 16rBABABABA. + ^self call: entryPC with: zapValue with: zapValue with: zapValue with: zapValue! Item was added: + ----- Method: MIPSSimulator>>call:with:with:with:with: (in category 'as yet unclassified') ----- + call: entryPC with: arg0 with: arg1 with: arg2 with: arg3. + + pc := entryPC. + self unsignedRegister: RA put: EndSimulationPC. + self signedRegister: A0 put: arg0. + self signedRegister: A1 put: arg1. + self signedRegister: A2 put: arg2. + self signedRegister: A3 put: arg3. + + self execute. + + ^self signedRegister: V0.! Item was added: + ----- Method: MIPSSimulator>>disassembleFrom:to:in:for:labels:on: (in category 'processor api') ----- + disassembleFrom: startAddress to: endAddress in: memory for: aSymbolManager "<Cogit>" labels: labelDictionary on: aStream + MIPSDisassembler new + disassemble: memory + from: startAddress + to: endAddress + for: aSymbolManager + labels: labelDictionary + on: aStream.! Item was added: + ----- Method: MIPSSimulator>>doBranch:offset: (in category 'as yet unclassified') ----- + doBranch: taken offset: offset + | nextPC | + pc := pc + OneInstruction. + nextPC := pc + offset. "Branch target is relative to the delay slot." + self executeDelaySlot. + taken ifTrue: [pc := nextPC - OneInstruction "Account for general increment"].! Item was added: + ----- Method: MIPSSimulator>>endianness (in category 'as yet unclassified') ----- + endianness + ^#little! Item was added: + ----- Method: MIPSSimulator>>execute (in category 'as yet unclassified') ----- + execute + | instruction | + [pc ~= EndSimulationPC] whileTrue: + [instruction := MIPSInstruction new value: (self unsignedWord: pc). + instruction decodeFor: self. + pc := pc + OneInstruction].! Item was added: + ----- Method: MIPSSimulator>>executeDelaySlot (in category 'as yet unclassified') ----- + executeDelaySlot + | instruction | + self assert: inDelaySlot not. + inDelaySlot := true. + instruction := MIPSInstruction new value: (self unsignedWord: pc). + instruction decodeFor: self. + inDelaySlot := false.! Item was added: + ----- Method: MIPSSimulator>>flushICacheFrom:to: (in category 'processor api') ----- + flushICacheFrom: startAddress "<Integer>" to: endAddress "<Integer>"! Item was added: + ----- Method: MIPSSimulator>>fp (in category 'processor api') ----- + fp + ^self signedRegister: FP! Item was added: + ----- Method: MIPSSimulator>>initializeStackFor: (in category 'processor api') ----- + initializeStackFor: aCogit + self flag: #OABI. + aCogit setStackAlignment: 8 expectedSPOffset: 0 expectedFPOffset: 0. + self initializeWithMemory: ByteArray new. + ! Item was added: + ----- Method: MIPSSimulator>>initializeWithMemory: (in category 'as yet unclassified') ----- + initializeWithMemory: aByteArray + memory := aByteArray. + registers := Array new: 32 withAll: 0. + pc := 0. + inDelaySlot := false. + instructionCount := 0.! Item was added: + ----- Method: MIPSSimulator>>jump: (in category 'instructions - control') ----- + jump: instruction + | nextPC | + self assert: inDelaySlot not. + pc := pc + OneInstruction. + nextPC := (pc bitAnd: 16rF0000000) + (instruction target << 2). "Region is that of the delay slot." + self executeDelaySlot. + pc := nextPC - OneInstruction. "Account for general increment"! Item was added: + ----- Method: MIPSSimulator>>jumpAndLink: (in category 'instructions - control') ----- + jumpAndLink: instruction + | nextPC | + self assert: inDelaySlot not. + self unsignedRegister: RA put: pc + TwoInstructions. "Return past delay slot." + pc := pc + OneInstruction. + nextPC := (pc bitAnd: 16rF0000000) + (instruction target << 2). "Region is that of the delay slot." + self executeDelaySlot. + pc := nextPC - OneInstruction. "Account for general increment"! Item was added: + ----- Method: MIPSSimulator>>jumpAndLinkRegister: (in category 'instructions - control') ----- + jumpAndLinkRegister: instruction + | nextPC | + self assert: inDelaySlot not. + self unsignedRegister: instruction rd put: pc + TwoInstructions. "Return past delay slot." + nextPC := self unsignedRegister: instruction rs. + pc := pc + OneInstruction. + self executeDelaySlot. + pc := nextPC. + pc := pc - 4. "Account for general increment"! Item was added: + ----- Method: MIPSSimulator>>jumpRegister: (in category 'instructions - control') ----- + jumpRegister: instruction + | nextPC | + self assert: inDelaySlot not. + nextPC := self unsignedRegister: instruction rs. + pc := pc + OneInstruction. + self executeDelaySlot. + pc := nextPC. + pc := pc - 4. "Account for general increment"! Item was added: + ----- Method: MIPSSimulator>>loadByte: (in category 'instructions - memory') ----- + loadByte: instruction + | base address value | + base := self unsignedRegister: instruction rs. + address := base + instruction signedImmediate. + value := self signedByte: address. + self signedRegister: instruction rt put: value.! Item was added: + ----- Method: MIPSSimulator>>loadByteUnsigned: (in category 'instructions - memory') ----- + loadByteUnsigned: instruction + | base address value | + base := self unsignedRegister: instruction rs. + address := base + instruction signedImmediate. + value := self unsignedByte: address. + self unsignedRegister: instruction rt put: value.! Item was added: + ----- Method: MIPSSimulator>>loadHalfword: (in category 'instructions - memory') ----- + loadHalfword: instruction + | base address value | + base := self unsignedRegister: instruction rs. + address := base + instruction signedImmediate. + value := self signedHalfword: address. + self signedRegister: instruction rt put: value.! Item was added: + ----- Method: MIPSSimulator>>loadHalfwordUnsigned: (in category 'instructions - memory') ----- + loadHalfwordUnsigned: instruction + | base address value | + base := self unsignedRegister: instruction rs. + address := base + instruction signedImmediate. + value := self unsignedHalfword: address. + self unsignedRegister: instruction rt put: value.! Item was added: + ----- Method: MIPSSimulator>>loadUpperImmediate: (in category 'instructions - arithmetic') ----- + loadUpperImmediate: instruction + | result | + self assert: instruction rs = 0. + result := instruction signedImmediate << 16. + self signedRegister: instruction rt put: result.! Item was added: + ----- Method: MIPSSimulator>>loadWord: (in category 'instructions - memory') ----- + loadWord: instruction + | base address value | + base := self unsignedRegister: instruction rs. + address := base + instruction signedImmediate. + value := self signedWord: address. + self signedRegister: instruction rt put: value.! Item was added: + ----- Method: MIPSSimulator>>memory (in category 'as yet unclassified') ----- + memory + ^memory! Item was added: + ----- Method: MIPSSimulator>>orImmediate: (in category 'instructions - arithmetic') ----- + orImmediate: instruction + | rsValue immediate result | + rsValue := self unsignedRegister: instruction rs. + immediate := instruction unsignedImmediate. + result := rsValue bitOr: immediate. + self unsignedRegister: instruction rt put: result.! Item was added: + ----- Method: MIPSSimulator>>printOn: (in category 'as yet unclassified') ----- + printOn: stream + stream nextPutAll: self class name; nextPut: $:; cr. + 0 to: 31 do: + [:reg | | hex | + stream space. + stream nextPutAll: (MIPSConstants nameForRegister: reg). + stream space. + hex := (self unsignedRegister: reg) printStringBase: 16. + 8 - hex size timesRepeat: [stream nextPut: $0]. + stream nextPutAll: hex. + stream space. + (self signedRegister: reg) printOn: stream. + stream cr]. + ! Item was added: + ----- Method: MIPSSimulator>>setFramePointer:stackPointer: (in category 'processor api') ----- + setFramePointer: fp stackPointer: sp + self signedRegister: SP put: sp. + self signedRegister: FP put: fp.! Item was added: + ----- Method: MIPSSimulator>>setOnLessThan: (in category 'instructions - arithmetic') ----- + setOnLessThan: instruction + | rsValue rtValue result | + rsValue := self signedRegister: instruction rs. + rtValue := self signedRegister: instruction rt. + result := rsValue < rtValue ifTrue: [1] ifFalse: [0]. + self signedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>setOnLessThanImmediate: (in category 'instructions - arithmetic') ----- + setOnLessThanImmediate: instruction + | rsValue immediate result | + rsValue := self signedRegister: instruction rs. + immediate := instruction signedImmediate. + result := rsValue < immediate ifTrue: [1] ifFalse: [0]. + self signedRegister: instruction rt put: result.! Item was added: + ----- Method: MIPSSimulator>>setOnLessThanImmediateUnsigned: (in category 'instructions - arithmetic') ----- + setOnLessThanImmediateUnsigned: instruction + "The immediate is still sign-extended; it is the comparison that is unsigned." + | rsValue immediate result | + rsValue := self unsignedRegister: instruction rs. + immediate := self signed32ToUnsigned32: instruction signedImmediate. + result := rsValue < immediate ifTrue: [1] ifFalse: [0]. + self signedRegister: instruction rt put: result.! Item was added: + ----- Method: MIPSSimulator>>setOnLessThanUnsigned: (in category 'instructions - arithmetic') ----- + setOnLessThanUnsigned: instruction + | rsValue rtValue result | + rsValue := self unsignedRegister: instruction rs. + rtValue := self unsignedRegister: instruction rt. + result := rsValue < rtValue ifTrue: [1] ifFalse: [0]. + self signedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>shiftLeftLogical: (in category 'instructions - arithmetic') ----- + shiftLeftLogical: instruction + | result rtValue shiftAmount | + self assert: instruction rs = 0. + rtValue := self unsignedRegister: instruction rt. + shiftAmount := instruction sa. + result := (rtValue << shiftAmount) bitAnd: 16rFFFFFFFF. + self unsignedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>shiftLeftLogicalVariable: (in category 'instructions - arithmetic') ----- + shiftLeftLogicalVariable: instruction + | result rtValue shiftAmount | + rtValue := self unsignedRegister: instruction rt. + shiftAmount := self unsignedRegister: instruction rs. + (31 allMask: shiftAmount) ifFalse: + ["MIPS will use only the low 5 bits for this shift, but we probably + don't want to generate any code that hits this behavior." + self error]. + result := (rtValue << shiftAmount) bitAnd: 16rFFFFFFFF. + self unsignedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>shiftRightArithmetic: (in category 'instructions - arithmetic') ----- + shiftRightArithmetic: instruction + | result rtValue shiftAmount | + self assert: instruction rs = 0. + rtValue := self signedRegister: instruction rt. + shiftAmount := instruction sa. + result := rtValue >> shiftAmount. + self signedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>shiftRightArithmeticVariable: (in category 'instructions - arithmetic') ----- + shiftRightArithmeticVariable: instruction + | result rtValue shiftAmount | + rtValue := self signedRegister: instruction rt. + shiftAmount := self unsignedRegister: instruction rs. + (31 allMask: shiftAmount) ifFalse: + ["MIPS will use only the low 5 bits for this shift, but we probably + don't want to generate any code that hits this behavior." + self error]. + result := rtValue >> shiftAmount. + self signedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>shiftRightLogical: (in category 'instructions - arithmetic') ----- + shiftRightLogical: instruction + | result rtValue shiftAmount | + self assert: instruction rs = 0. + rtValue := self unsignedRegister: instruction rt. + shiftAmount := instruction sa. + result := rtValue >> shiftAmount. + self unsignedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>shiftRightLogicalVariable: (in category 'instructions - arithmetic') ----- + shiftRightLogicalVariable: instruction + | result rtValue shiftAmount | + rtValue := self unsignedRegister: instruction rt. + shiftAmount := self unsignedRegister: instruction rs. + (31 allMask: shiftAmount) ifFalse: + ["MIPS will use only the low 5 bits for this shift, but we probably + don't want to generate any code that hits this behavior." + self error]. + result := rtValue >> shiftAmount. + self unsignedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>signed32ToUnsigned32: (in category 'converting') ----- + signed32ToUnsigned32: signedValue + self assert: (signedValue between: -16r80000000 and: 16r7FFFFFFF). + signedValue < 0 ifTrue: [^signedValue + 16r100000000]. + ^signedValue! Item was added: + ----- Method: MIPSSimulator>>signedRegister: (in category 'registers') ----- + signedRegister: registerNumber + registerNumber == ZR ifTrue: [^0] ifFalse: [^registers at: registerNumber + 1].! Item was added: + ----- Method: MIPSSimulator>>signedRegister:put: (in category 'registers') ----- + signedRegister: registerNumber put: signedValue + self assert: (signedValue between: -16r80000000 and: 16r7FFFFFFF). + registerNumber == ZR ifFalse: [registers at: registerNumber + 1 put: signedValue].! Item was added: + ----- Method: MIPSSimulator>>sp (in category 'processor api') ----- + sp + ^self signedRegister: SP! Item was added: + ----- Method: MIPSSimulator>>storeByte: (in category 'instructions - memory') ----- + storeByte: instruction + | base address value | + base := self unsignedRegister: instruction rs. + address := base + instruction signedImmediate. + value := (self signedRegister: instruction rt) bitAnd: 16rFF. + self unsignedByte: address put: value.! Item was added: + ----- Method: MIPSSimulator>>storeHalfword: (in category 'instructions - memory') ----- + storeHalfword: instruction + | base address value | + base := self unsignedRegister: instruction rs. + address := base + instruction signedImmediate. + value := (self signedRegister: instruction rt) bitAnd: 16rFFFF. + self unsignedHalfword: address put: value.! Item was added: + ----- Method: MIPSSimulator>>storeWord: (in category 'instructions - memory') ----- + storeWord: instruction + | base address value | + base := self unsignedRegister: instruction rs. + address := base + instruction signedImmediate. + value := self signedRegister: instruction rt. + self signedWord: address put: value.! Item was added: + ----- Method: MIPSSimulator>>subtractUnsigned: (in category 'instructions - arithmetic') ----- + subtractUnsigned: instruction + "Unsigned here means the instruction doesn't generate exceptions." + | rsValue rtValue result | + rsValue := self unsignedRegister: instruction rs. + rtValue := self unsignedRegister: instruction rt. + result := rsValue - rtValue bitAnd: 16rFFFFFFFF. "No exception on overflow" + self unsignedRegister: instruction rd put: result.! Item was added: + ----- Method: MIPSSimulator>>unsigned32ToSigned32: (in category 'converting') ----- + unsigned32ToSigned32: unsignedValue + self assert: (unsignedValue between: 0 and: 16rFFFFFFFF). + unsignedValue >= 16r80000000 ifTrue: [^unsignedValue - 16r100000000]. + ^unsignedValue! Item was added: + ----- Method: MIPSSimulator>>unsignedRegister: (in category 'registers') ----- + unsignedRegister: registerNumber + registerNumber == ZR + ifTrue: [^0] + ifFalse: [^self signed32ToUnsigned32: (registers at: registerNumber + 1)].! Item was added: + ----- Method: MIPSSimulator>>unsignedRegister:put: (in category 'registers') ----- + unsignedRegister: registerNumber put: unsignedValue + registerNumber == ZR ifFalse: + [registers at: registerNumber + 1 put: (self unsigned32ToSigned32: unsignedValue)].! Item was added: + ----- Method: MIPSSimulator>>xorImmediate: (in category 'instructions - arithmetic') ----- + xorImmediate: instruction + | rsValue immediate result | + rsValue := self unsignedRegister: instruction rs. + immediate := instruction unsignedImmediate. + result := rsValue bitXor: immediate. + self unsignedRegister: instruction rt put: result.!

1 0

[commit][3494] Fix the GdbARMPlugin build on Mac OS X 10.9/xcode 6.x
by commits＠squeakvm.org 12 Nov '15

12 Nov '15

Revision: 3494 Author: eliot Date: 2015-11-11 19:12:34 -0800 (Wed, 11 Nov 2015) Log Message: ----------- Fix the GdbARMPlugin build on Mac OS X 10.9/xcode 6.x Modified Paths: -------------- branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj Removed Paths: ------------- branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/build/ Modified: branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj 2015-11-12 02:18:21 UTC (rev 3493) +++ branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj 2015-11-12 03:12:34 UTC (rev 3494) @@ -13,7 +13,8 @@ 732788241AB7C73500BE5008 /* environ.c in Sources */ = {isa = PBXBuildFile; fileRef = 732787F11AB7A12A00BE5008 /* environ.c */; }; 737482B30EE7339F004E10F8 /* libopcodes.a in Frameworks */ = {isa = PBXBuildFile; fileRef = 737482B20EE7339F004E10F8 /* libopcodes.a */; }; 737482B50EE733BD004E10F8 /* libsim.a in Frameworks */ = {isa = PBXBuildFile; fileRef = 737482B40EE733BD004E10F8 /* libsim.a */; }; - 737482B70EE7343B004E10F8 /* sqGdbARMPlugin.c in Sources */ = {isa = PBXBuildFile; fileRef = 737482B60EE7343B004E10F8 /* sqGdbARMPlugin.c */; settings = {COMPILER_FLAGS = "-I../../../processors/ARM/mac/gdb-7.10/include -I../../../processors/ARM/mac/gdb-7.10/sim/arm -I../../../processors/ARM/mac/gdb-7.10/bfd -I../../gdbarm32/opcodes -I../../gdbarm32/bfd"; }; }; + 737482B70EE7343B004E10F8 /* sqGdbARMPlugin.c in Sources */ = {isa = PBXBuildFile; fileRef = 737482B60EE7343B004E10F8 /* sqGdbARMPlugin.c */; settings = {COMPILER_FLAGS = "-I../../../processors/ARM/gdb-7.10/include -I../../../processors/ARM/gdb-7.10/sim/arm -I../../../processors/ARM/gdb-7.10/bfd -I../../gdbarm32/bfd"; }; }; + 73A487F71BF43A8500A1166F /* libz.1.dylib in Frameworks */ = {isa = PBXBuildFile; fileRef = 73A487F61BF43A8500A1166F /* libz.1.dylib */; }; 8D01CCCE0486CAD60068D4B7 /* Carbon.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 08EA7FFBFE8413EDC02AAC07 /* Carbon.framework */; }; /* End PBXBuildFile section */ @@ -22,11 +23,12 @@ 73020E8C0EE714E60021D217 /* GdbARMPlugin.c */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.c; name = GdbARMPlugin.c; path = ../../../src/plugins/GdbARMPlugin/GdbARMPlugin.c; sourceTree = SOURCE_ROOT; }; 73020E8E0EE7158C0021D217 /* GdbARMPlugin.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; name = GdbARMPlugin.h; path = ../../../platforms/Cross/plugins/GdbARMPlugin/GdbARMPlugin.h; sourceTree = SOURCE_ROOT; }; 732787F11AB7A12A00BE5008 /* environ.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = environ.c; path = "../../../platforms/Mac OS/plugins/GdbARMPlugin/environ.c"; sourceTree = SOURCE_ROOT; }; - 732787F51AB7A40100BE5008 /* libiberty.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libiberty.a; path = "../../gdbarm32/libiberty/libiberty.a"; sourceTree = SOURCE_ROOT; }; - 737482B20EE7339F004E10F8 /* libopcodes.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libopcodes.a; path = "../../gdbarm32/opcodes/libopcodes.a"; sourceTree = SOURCE_ROOT; }; - 737482B40EE733BD004E10F8 /* libsim.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libsim.a; path = "../../gdbarm32/sim/arm/libsim.a"; sourceTree = SOURCE_ROOT; }; + 732787F51AB7A40100BE5008 /* libiberty.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libiberty.a; path = ../../gdbarm32/libiberty/libiberty.a; sourceTree = SOURCE_ROOT; }; + 737482B20EE7339F004E10F8 /* libopcodes.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libopcodes.a; path = ../../gdbarm32/opcodes/libopcodes.a; sourceTree = SOURCE_ROOT; }; + 737482B40EE733BD004E10F8 /* libsim.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libsim.a; path = ../../gdbarm32/sim/arm/libsim.a; sourceTree = SOURCE_ROOT; }; 737482B60EE7343B004E10F8 /* sqGdbARMPlugin.c */ = {isa = PBXFileReference; explicitFileType = sourcecode.c.c; fileEncoding = 30; name = sqGdbARMPlugin.c; path = ../../../platforms/Cross/plugins/GdbARMPlugin/sqGdbARMPlugin.c; sourceTree = SOURCE_ROOT; }; - 73ADAA901AB79ED50085DAA8 /* libbfd.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libbfd.a; path = "../../gdbarm32/bfd/libbfd.a"; sourceTree = SOURCE_ROOT; }; + 73A487F61BF43A8500A1166F /* libz.1.dylib */ = {isa = PBXFileReference; lastKnownFileType = "compiled.mach-o.dylib"; name = libz.1.dylib; path = /usr/lib/libz.1.dylib; sourceTree = "<absolute>"; }; + 73ADAA901AB79ED50085DAA8 /* libbfd.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libbfd.a; path = ../../gdbarm32/bfd/libbfd.a; sourceTree = SOURCE_ROOT; }; 8D01CCD10486CAD60068D4B7 /* Info.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist; path = Info.plist; sourceTree = "<group>"; }; 8D01CCD20486CAD60068D4B7 /* GdbARMPlugin.bundle */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = GdbARMPlugin.bundle; sourceTree = BUILT_PRODUCTS_DIR; }; DA3A20F50AA63CBF0050B983 /* interp.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; name = interp.h; path = ../../../spursrc/vm/interp.h; sourceTree = SOURCE_ROOT; }; @@ -47,6 +49,7 @@ 737482B50EE733BD004E10F8 /* libsim.a in Frameworks */, 732787F61AB7A40100BE5008 /* libiberty.a in Frameworks */, 732788161AB7BDAC00BE5008 /* libbfd.a in Frameworks */, + 73A487F71BF43A8500A1166F /* libz.1.dylib in Frameworks */, ); runOnlyForDeploymentPostprocessing = 0; }; @@ -71,6 +74,7 @@ isa = PBXGroup; children = ( 08EA7FFBFE8413EDC02AAC07 /* Carbon.framework */, + 73A487F61BF43A8500A1166F /* libz.1.dylib */, ); name = "External Frameworks and Libraries"; sourceTree = "<group>"; @@ -196,11 +200,11 @@ "$(LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_4)", "$(LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_5)", ); - LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_1 = "\"$(SRCROOT)/../../../processors/ARM/mac/gdb-7.6/opcodes\""; - LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_2 = "\"$(SRCROOT)/../../../processors/ARM/mac/gdb-7.6/sim/arm\""; - LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_3 = "\"$(SRCROOT)/../../../processors/ARM/mac/binutils-2.25/bfd\""; - LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_4 = "\"$(SRCROOT)/../../../processors/ARM/mac/binutils-2.25/libiberty\""; - LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_5 = "\"$(SRCROOT)/../../../processors/ARM/mac/binutils-2.25/bfd\""; + LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_1 = ../../gdbarm32/opcodes; + LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_2 = ../../gdbarm32/sim/arm; + LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_3 = ../../gdbarm32/bfd; + LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_4 = ../../gdbarm32/libiberty; + LIBRARY_SEARCH_PATHS_QUOTED_FOR_TARGET_5 = ../../gdbarm32/bfd; PRODUCT_NAME = GdbARMPlugin; WRAPPER_EXTENSION = bundle; ZERO_LINK = YES; @@ -237,6 +241,8 @@ isa = XCBuildConfiguration; buildSettings = { ALWAYS_SEARCH_USER_PATHS = NO; + ARCHS = "$(ARCHS_STANDARD_32_BIT_PRE_XCODE_3_1)"; + ARCHS_STANDARD_32_BIT_PRE_XCODE_3_1 = "ppc i386"; CONFIGURATION_BUILD_DIR = "$(BUILD_DIR)/$(CONFIGURATION)"; CONFIGURATION_TEMP_DIR = "$(PROJECT_TEMP_DIR)/$(CONFIGURATION)"; COPY_PHASE_STRIP = NO; @@ -245,9 +251,10 @@ GCC_WARN_ABOUT_RETURN_TYPE = YES; GCC_WARN_UNUSED_VARIABLE = YES; HEADER_SEARCH_PATHS = /Developer/Headers/FlatCarbon; + MACOSX_DEPLOYMENT_TARGET = 10.6; PREBINDING = NO; PRECOMPS_INCLUDE_HEADERS_FROM_BUILT_PRODUCTS_DIR = NO; - SDKROOT = /Developer/SDKs/MacOSX10.6.sdk; + SDKROOT = ""; STRIP_INSTALLED_PRODUCT = NO; USER_HEADER_SEARCH_PATHS = ""; USE_HEADERMAP = NO; @@ -258,6 +265,8 @@ isa = XCBuildConfiguration; buildSettings = { ALWAYS_SEARCH_USER_PATHS = YES; + ARCHS = "$(ARCHS_STANDARD_32_BIT_PRE_XCODE_3_1)"; + ARCHS_STANDARD_32_BIT_PRE_XCODE_3_1 = "ppc i386"; CONFIGURATION_BUILD_DIR = "$(BUILD_DIR)/$(CONFIGURATION)"; CONFIGURATION_TEMP_DIR = "$(PROJECT_TEMP_DIR)/$(CONFIGURATION)"; COPY_PHASE_STRIP = NO; @@ -265,9 +274,10 @@ GCC_WARN_ABOUT_RETURN_TYPE = YES; GCC_WARN_UNUSED_VARIABLE = YES; HEADER_SEARCH_PATHS = /Developer/Headers/FlatCarbon; + MACOSX_DEPLOYMENT_TARGET = 10.6; PREBINDING = NO; PRECOMPS_INCLUDE_HEADERS_FROM_BUILT_PRODUCTS_DIR = NO; - SDKROOT = /Developer/SDKs/MacOSX10.6.sdk; + SDKROOT = ""; USER_HEADER_SEARCH_PATHS = ""; USE_HEADERMAP = NO; };

1 0

[commit][3493] Fix a slip in the linux BochsIA32Plugin makefile.
by commits＠squeakvm.org 12 Nov '15

12 Nov '15

Revision: 3493 Author: eliot Date: 2015-11-11 18:18:21 -0800 (Wed, 11 Nov 2015) Log Message: ----------- Fix a slip in the linux BochsIA32Plugin makefile. Partially correct include paths in the Mac Spur GdbARMPlugin xcode project, but it still doesn't build. Modified Paths: -------------- branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj branches/Cog/platforms/unix/plugins/BochsIA32Plugin/Makefile.inc Modified: branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj 2015-11-12 01:53:26 UTC (rev 3492) +++ branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj 2015-11-12 02:18:21 UTC (rev 3493) @@ -13,7 +13,7 @@ 732788241AB7C73500BE5008 /* environ.c in Sources */ = {isa = PBXBuildFile; fileRef = 732787F11AB7A12A00BE5008 /* environ.c */; }; 737482B30EE7339F004E10F8 /* libopcodes.a in Frameworks */ = {isa = PBXBuildFile; fileRef = 737482B20EE7339F004E10F8 /* libopcodes.a */; }; 737482B50EE733BD004E10F8 /* libsim.a in Frameworks */ = {isa = PBXBuildFile; fileRef = 737482B40EE733BD004E10F8 /* libsim.a */; }; - 737482B70EE7343B004E10F8 /* sqGdbARMPlugin.c in Sources */ = {isa = PBXBuildFile; fileRef = 737482B60EE7343B004E10F8 /* sqGdbARMPlugin.c */; settings = {COMPILER_FLAGS = "-I../../../processors/ARM/mac/gdb-7.10/include -I../../../processors/ARM/mac/gdb-7.10/sim/arm -I../../../processors/ARM/mac/gdb-7.10/bfd"; }; }; + 737482B70EE7343B004E10F8 /* sqGdbARMPlugin.c in Sources */ = {isa = PBXBuildFile; fileRef = 737482B60EE7343B004E10F8 /* sqGdbARMPlugin.c */; settings = {COMPILER_FLAGS = "-I../../../processors/ARM/mac/gdb-7.10/include -I../../../processors/ARM/mac/gdb-7.10/sim/arm -I../../../processors/ARM/mac/gdb-7.10/bfd -I../../gdbarm32/opcodes -I../../gdbarm32/bfd"; }; }; 8D01CCCE0486CAD60068D4B7 /* Carbon.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 08EA7FFBFE8413EDC02AAC07 /* Carbon.framework */; }; /* End PBXBuildFile section */ Modified: branches/Cog/platforms/unix/plugins/BochsIA32Plugin/Makefile.inc =================================================================== --- branches/Cog/platforms/unix/plugins/BochsIA32Plugin/Makefile.inc 2015-11-12 01:53:26 UTC (rev 3492) +++ branches/Cog/platforms/unix/plugins/BochsIA32Plugin/Makefile.inc 2015-11-12 02:18:21 UTC (rev 3493) @@ -1,11 +1,11 @@ XCFLAGS=-m32 XCPPFLAGS= -m32 -DUSE_BOCHS_CONFIG_H=1 \ - -I../../../bochsx32 \ + -I../../../bochsx86 \ -I$(topdir)/processors/IA32/bochs \ -I$(topdir)/processors/IA32/bochs/instrument/stubs -XLDFLAGS= -L../../../bochsx32/cpu \ - -L../../../bochsx32/fpu \ - -L../../../bochsx32/disasm \ +XLDFLAGS= -L../../../bochsx86/cpu \ + -L../../../bochsx86/fpu \ + -L../../../bochsx86/disasm \ -lcpu -lfpu -ldisasm \ -lstdc++

1 0

[commit][3492] Use cd ./ $d in all makefoo files so as not to get confused by CDPATH.
by commits＠squeakvm.org 12 Nov '15

12 Nov '15

Revision: 3492 Author: eliot Date: 2015-11-11 17:53:26 -0800 (Wed, 11 Nov 2015) Log Message: ----------- Use cd ./$d in all makefoo files so as not to get confused by CDPATH. Modify the Linux and Mac OS X processor plugin builds to use the new "build support libraries under the platform's buiuld directory" scheme. Nuke some configuration artifacts in the ARM gdb 7.10 source tree. Modified Paths: -------------- branches/Cog/build.linux32ARM/makeall branches/Cog/build.linux32ARM/makeallclean branches/Cog/build.linux32ARM/makeallmakefiles branches/Cog/build.linux32ARM/makeproduct branches/Cog/build.linux32ARM/makeproductclean branches/Cog/build.linux32ARM/newspeak.cog.spur/makeallclean branches/Cog/build.linux32ARM/newspeak.cog.spur/makealldirty branches/Cog/build.linux32ARM/newspeak.stack.spur/makeallclean branches/Cog/build.linux32ARM/newspeak.stack.spur/makealldirty branches/Cog/build.linux32ARM/squeak.cog.spur/makeallclean branches/Cog/build.linux32ARM/squeak.cog.spur/makealldirty branches/Cog/build.linux32ARM/squeak.stack.spur/makeallclean branches/Cog/build.linux32ARM/squeak.stack.spur/makealldirty branches/Cog/build.linux32ARM/squeak.stack.v3/makeallclean branches/Cog/build.linux32ARM/squeak.stack.v3/makealldirty branches/Cog/build.linux32x86/gdbarm32/makeem branches/Cog/build.linux32x86/glue.cog.spur/makeallclean branches/Cog/build.linux32x86/glue.cog.spur/makealldirty branches/Cog/build.linux32x86/makeall branches/Cog/build.linux32x86/makeallclean branches/Cog/build.linux32x86/makeallmakefiles branches/Cog/build.linux32x86/makeproduct branches/Cog/build.linux32x86/makeproductclean branches/Cog/build.linux32x86/newspeak.cog.spur/makeallclean branches/Cog/build.linux32x86/newspeak.cog.spur/makealldirty branches/Cog/build.linux32x86/newspeak.sista.spur/makeallclean branches/Cog/build.linux32x86/newspeak.sista.spur/makealldirty branches/Cog/build.linux32x86/newspeak.stack.spur/makeallclean branches/Cog/build.linux32x86/newspeak.stack.spur/makealldirty branches/Cog/build.linux32x86/squeak.cog.spur/makeallclean branches/Cog/build.linux32x86/squeak.cog.spur/makealldirty branches/Cog/build.linux32x86/squeak.cog.v3/makeallclean branches/Cog/build.linux32x86/squeak.cog.v3/makealldirty branches/Cog/build.linux32x86/squeak.sista.spur/makeallclean branches/Cog/build.linux32x86/squeak.sista.spur/makealldirty branches/Cog/build.linux32x86/squeak.stack.spur/makeallclean branches/Cog/build.linux32x86/squeak.stack.spur/makealldirty branches/Cog/build.linux32x86/squeak.stack.v3/makeallclean branches/Cog/build.linux32x86/squeak.stack.v3/makealldirty branches/Cog/build.linux64x64/makeall branches/Cog/build.linux64x64/makeallclean branches/Cog/build.linux64x64/makeallmakefiles branches/Cog/build.linux64x64/makeproduct branches/Cog/build.linux64x64/makeproductclean branches/Cog/build.linux64x64/newspeak.cog.spur/makeallclean branches/Cog/build.linux64x64/newspeak.cog.spur/makealldirty branches/Cog/build.linux64x64/newspeak.sista.spur/makeallclean branches/Cog/build.linux64x64/newspeak.sista.spur/makealldirty branches/Cog/build.linux64x64/newspeak.stack.spur/makeallclean branches/Cog/build.linux64x64/newspeak.stack.spur/makealldirty branches/Cog/build.linux64x64/squeak.cog.spur/makeallclean branches/Cog/build.linux64x64/squeak.cog.spur/makealldirty branches/Cog/build.linux64x64/squeak.sista.spur/makeallclean branches/Cog/build.linux64x64/squeak.sista.spur/makealldirty branches/Cog/build.linux64x64/squeak.stack.spur/makeallclean branches/Cog/build.linux64x64/squeak.stack.spur/makealldirty branches/Cog/build.macos32x86/gdbarm32/makeem branches/Cog/build.macos32x86/makeall branches/Cog/build.macos32x86/makeallinstall branches/Cog/build.macos32x86/makeproduct branches/Cog/build.macos32x86/makeproductinstall branches/Cog/build.macos32x86/makesista branches/Cog/build.macos32x86/makespur branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm branches/Cog/build.macos32x86/squeak.cog.spur/makevm branches/Cog/build.macos64x64/makeall branches/Cog/build.macos64x64/makeallinstall branches/Cog/build.macos64x64/makeproduct branches/Cog/build.macos64x64/makeproductinstall branches/Cog/build.macos64x64/makesista branches/Cog/build.macos64x64/makespur branches/Cog/build.win32x86/makeall branches/Cog/build.win32x86/makeallinstall branches/Cog/build.win32x86/makeproduct branches/Cog/build.win32x86/makeproductinstall branches/Cog/platforms/unix/plugins/GdbARMPlugin/HowToBuild branches/Cog/platforms/unix/plugins/GdbARMPlugin/Makefile.inc branches/Cog/platforms/unix/plugins/GdbARMPlugin/acinclude.m4 Added Paths: ----------- branches/Cog/build.linux32x86/gdbarm32/ branches/Cog/platforms/unix/plugins/BochsIA32Plugin/HowToBuild branches/Cog/platforms/unix/plugins/BochsIA32Plugin/acinclude.m4 branches/Cog/platforms/unix/plugins/BochsX64Plugin/HowToBuild branches/Cog/platforms/unix/plugins/BochsX64Plugin/acinclude.m4 Removed Paths: ------------- branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ branches/Cog/processors/ARM/gdb-7.10/opcodes/Makefile branches/Cog/processors/ARM/gdb-7.10/opcodes/config.h branches/Cog/processors/ARM/gdb-7.10/opcodes/config.log branches/Cog/processors/ARM/gdb-7.10/opcodes/config.status branches/Cog/processors/ARM/gdb-7.10/opcodes/libtool branches/Cog/processors/ARM/gdb-7.10/opcodes/po/Makefile branches/Cog/processors/ARM/gdb-7.10/opcodes/po/Makefile.in branches/Cog/processors/ARM/gdb-7.10/opcodes/po/POTFILES branches/Cog/processors/ARM/gdb-7.10/opcodes/stamp-h1 branches/Cog/processors/ARM/gdb-7.10/opcodes/stamp-lib Property Changed: ---------------- branches/Cog/build.linux32x86/bochsx64/ branches/Cog/build.linux32x86/bochsx86/ Modified: branches/Cog/build.linux32ARM/makeall =================================================================== --- branches/Cog/build.linux32ARM/makeall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/makeall 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.* squeak.*; do if test -d "$d"; then - (cd $d;./makealldirty "$@") + (cd ./$d;./makealldirty "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux32ARM/makeallclean =================================================================== --- branches/Cog/build.linux32ARM/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.* squeak.*; do if test -d "$d"; then - (cd $d;./makeallclean "$@") + (cd ./$d;./makeallclean "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux32ARM/makeallmakefiles =================================================================== --- branches/Cog/build.linux32ARM/makeallmakefiles 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/makeallmakefiles 2015-11-12 01:53:26 UTC (rev 3492) @@ -3,7 +3,7 @@ for td in *.v3 *.spur; do for d in $td/build*; do if test -d "$d"; then - (cd $d;../../../platforms/unix/config/mkmf) + (cd ./$d;../../../platforms/unix/config/mkmf) else echo no $d directory found fi Modified: branches/Cog/build.linux32ARM/makeproduct =================================================================== --- branches/Cog/build.linux32ARM/makeproduct 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/makeproduct 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.spur squeak.cog.spur squeak.cog.v3 squeak.stack.spur squeak.stack.v3; do if test -d "$d"; then - (cd $d;./makealldirty "$@") + (cd ./$d;./makealldirty "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux32ARM/makeproductclean =================================================================== --- branches/Cog/build.linux32ARM/makeproductclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/makeproductclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.spur squeak.cog.spur squeak.cog.v3 squeak.stack.spur squeak.stack.v3; do if test -d "$d"; then - (cd $d;./makeallclean "$@") + (cd ./$d;./makeallclean "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux32ARM/newspeak.cog.spur/makeallclean =================================================================== --- branches/Cog/build.linux32ARM/newspeak.cog.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/newspeak.cog.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32ARM/newspeak.cog.spur/makealldirty =================================================================== --- branches/Cog/build.linux32ARM/newspeak.cog.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/newspeak.cog.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32ARM/newspeak.stack.spur/makeallclean =================================================================== --- branches/Cog/build.linux32ARM/newspeak.stack.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/newspeak.stack.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32ARM/newspeak.stack.spur/makealldirty =================================================================== --- branches/Cog/build.linux32ARM/newspeak.stack.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/newspeak.stack.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32ARM/squeak.cog.spur/makeallclean =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32ARM/squeak.cog.spur/makealldirty =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32ARM/squeak.stack.spur/makeallclean =================================================================== --- branches/Cog/build.linux32ARM/squeak.stack.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/squeak.stack.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32ARM/squeak.stack.spur/makealldirty =================================================================== --- branches/Cog/build.linux32ARM/squeak.stack.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/squeak.stack.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32ARM/squeak.stack.v3/makeallclean =================================================================== --- branches/Cog/build.linux32ARM/squeak.stack.v3/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/squeak.stack.v3/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32ARM/squeak.stack.v3/makealldirty =================================================================== --- branches/Cog/build.linux32ARM/squeak.stack.v3/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32ARM/squeak.stack.v3/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Property changes on: branches/Cog/build.linux32x86/bochsx64 ___________________________________________________________________ Added: svn:ignore + * Property changes on: branches/Cog/build.linux32x86/bochsx86 ___________________________________________________________________ Added: svn:ignore + * Modified: branches/Cog/build.linux32x86/gdbarm32/makeem =================================================================== --- branches/Cog/build.macos32x86/gdbarm32/makeem 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/gdbarm32/makeem 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,4 +1,4 @@ #!/bin/sh for d in zlib bfd libiberty opcodes sim/arm; do - (cd $d; make COG=1) + (cd ./$d; make COG=1) done Modified: branches/Cog/build.linux32x86/glue.cog.spur/makeallclean =================================================================== --- branches/Cog/build.linux32x86/glue.cog.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/glue.cog.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32x86/glue.cog.spur/makealldirty =================================================================== --- branches/Cog/build.linux32x86/glue.cog.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/glue.cog.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32x86/makeall =================================================================== --- branches/Cog/build.linux32x86/makeall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/makeall 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.* newspeak.stack.* squeak.*; do if test -d "$d"; then - (cd $d;./makealldirty "$@") + (cd ./$d;./makealldirty "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux32x86/makeallclean =================================================================== --- branches/Cog/build.linux32x86/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.* newspeak.stack.* squeak.*; do if test -d "$d"; then - (cd $d;./makeallclean "$@") + (cd ./$d;./makeallclean "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux32x86/makeallmakefiles =================================================================== --- branches/Cog/build.linux32x86/makeallmakefiles 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/makeallmakefiles 2015-11-12 01:53:26 UTC (rev 3492) @@ -3,7 +3,7 @@ for td in *.v3 *.spur; do for d in $td/build*; do if test -d "$d"; then - (cd $d;../../../platforms/unix/config/mkmf) + (cd ./$d;../../../platforms/unix/config/mkmf) else echo no $d directory found fi Modified: branches/Cog/build.linux32x86/makeproduct =================================================================== --- branches/Cog/build.linux32x86/makeproduct 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/makeproduct 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.spur squeak.cog.spur squeak.cog.v3; do if test -d "$d"; then - (cd $d;./makealldirty "$@") + (cd ./$d;./makealldirty "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux32x86/makeproductclean =================================================================== --- branches/Cog/build.linux32x86/makeproductclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/makeproductclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.spur squeak.cog.spur squeak.cog.v3; do if test -d "$d"; then - (cd $d;./makeallclean "$@") + (cd ./$d;./makeallclean "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux32x86/newspeak.cog.spur/makeallclean =================================================================== --- branches/Cog/build.linux32x86/newspeak.cog.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/newspeak.cog.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32x86/newspeak.cog.spur/makealldirty =================================================================== --- branches/Cog/build.linux32x86/newspeak.cog.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/newspeak.cog.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32x86/newspeak.sista.spur/makeallclean =================================================================== --- branches/Cog/build.linux32x86/newspeak.sista.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/newspeak.sista.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32x86/newspeak.sista.spur/makealldirty =================================================================== --- branches/Cog/build.linux32x86/newspeak.sista.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/newspeak.sista.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32x86/newspeak.stack.spur/makeallclean =================================================================== --- branches/Cog/build.linux32x86/newspeak.stack.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/newspeak.stack.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32x86/newspeak.stack.spur/makealldirty =================================================================== --- branches/Cog/build.linux32x86/newspeak.stack.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/newspeak.stack.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32x86/squeak.cog.spur/makeallclean =================================================================== --- branches/Cog/build.linux32x86/squeak.cog.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.cog.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32x86/squeak.cog.spur/makealldirty =================================================================== --- branches/Cog/build.linux32x86/squeak.cog.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.cog.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32x86/squeak.cog.v3/makeallclean =================================================================== --- branches/Cog/build.linux32x86/squeak.cog.v3/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.cog.v3/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32x86/squeak.cog.v3/makealldirty =================================================================== --- branches/Cog/build.linux32x86/squeak.cog.v3/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.cog.v3/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32x86/squeak.sista.spur/makeallclean =================================================================== --- branches/Cog/build.linux32x86/squeak.sista.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.sista.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32x86/squeak.sista.spur/makealldirty =================================================================== --- branches/Cog/build.linux32x86/squeak.sista.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.sista.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32x86/squeak.stack.spur/makeallclean =================================================================== --- branches/Cog/build.linux32x86/squeak.stack.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.stack.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32x86/squeak.stack.spur/makealldirty =================================================================== --- branches/Cog/build.linux32x86/squeak.stack.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.stack.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux32x86/squeak.stack.v3/makeallclean =================================================================== --- branches/Cog/build.linux32x86/squeak.stack.v3/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.stack.v3/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux32x86/squeak.stack.v3/makealldirty =================================================================== --- branches/Cog/build.linux32x86/squeak.stack.v3/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux32x86/squeak.stack.v3/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux64x64/makeall =================================================================== --- branches/Cog/build.linux64x64/makeall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/makeall 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.* newspeak.stack.* squeak.*; do if test -d "$d"; then - (cd $d;./makealldirty "$@") + (cd ./$d;./makealldirty "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux64x64/makeallclean =================================================================== --- branches/Cog/build.linux64x64/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.* newspeak.stack.* squeak.*; do if test -d "$d"; then - (cd $d;./makeallclean "$@") + (cd ./$d;./makeallclean "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux64x64/makeallmakefiles =================================================================== --- branches/Cog/build.linux64x64/makeallmakefiles 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/makeallmakefiles 2015-11-12 01:53:26 UTC (rev 3492) @@ -3,7 +3,7 @@ for td in *.v3 *.spur; do for d in $td/build*; do if test -d "$d"; then - (cd $d;../../../platforms/unix/config/mkmf) + (cd ./$d;../../../platforms/unix/config/mkmf) else echo no $d directory found fi Modified: branches/Cog/build.linux64x64/makeproduct =================================================================== --- branches/Cog/build.linux64x64/makeproduct 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/makeproduct 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.spur squeak.cog.spur; do if test -d "$d"; then - (cd $d;./makealldirty "$@") + (cd ./$d;./makealldirty "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux64x64/makeproductclean =================================================================== --- branches/Cog/build.linux64x64/makeproductclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/makeproductclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.spur squeak.cog.spur; do if test -d "$d"; then - (cd $d;./makeallclean "$@") + (cd ./$d;./makeallclean "$@") else echo no $d directory found fi Modified: branches/Cog/build.linux64x64/newspeak.cog.spur/makeallclean =================================================================== --- branches/Cog/build.linux64x64/newspeak.cog.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/newspeak.cog.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux64x64/newspeak.cog.spur/makealldirty =================================================================== --- branches/Cog/build.linux64x64/newspeak.cog.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/newspeak.cog.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux64x64/newspeak.sista.spur/makeallclean =================================================================== --- branches/Cog/build.linux64x64/newspeak.sista.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/newspeak.sista.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux64x64/newspeak.sista.spur/makealldirty =================================================================== --- branches/Cog/build.linux64x64/newspeak.sista.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/newspeak.sista.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux64x64/newspeak.stack.spur/makeallclean =================================================================== --- branches/Cog/build.linux64x64/newspeak.stack.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/newspeak.stack.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux64x64/newspeak.stack.spur/makealldirty =================================================================== --- branches/Cog/build.linux64x64/newspeak.stack.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/newspeak.stack.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux64x64/squeak.cog.spur/makeallclean =================================================================== --- branches/Cog/build.linux64x64/squeak.cog.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/squeak.cog.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux64x64/squeak.cog.spur/makealldirty =================================================================== --- branches/Cog/build.linux64x64/squeak.cog.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/squeak.cog.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux64x64/squeak.sista.spur/makeallclean =================================================================== --- branches/Cog/build.linux64x64/squeak.sista.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/squeak.sista.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux64x64/squeak.sista.spur/makealldirty =================================================================== --- branches/Cog/build.linux64x64/squeak.sista.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/squeak.sista.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.linux64x64/squeak.stack.spur/makeallclean =================================================================== --- branches/Cog/build.linux64x64/squeak.stack.spur/makeallclean 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/squeak.stack.spur/makeallclean 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo y | ./mvm "$@") & done wait Modified: branches/Cog/build.linux64x64/squeak.stack.spur/makealldirty =================================================================== --- branches/Cog/build.linux64x64/squeak.stack.spur/makealldirty 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.linux64x64/squeak.stack.spur/makealldirty 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,6 @@ #!/bin/sh trap 'exit 2' HUP INT PIPE TERM for d in `dirname $0`/build*; do - (cd $d + (cd ./$d echo n | ./mvm "$@") done Modified: branches/Cog/build.macos32x86/gdbarm32/makeem =================================================================== --- branches/Cog/build.macos32x86/gdbarm32/makeem 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/gdbarm32/makeem 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,4 +1,4 @@ #!/bin/sh for d in zlib bfd libiberty opcodes sim/arm; do - (cd $d; make COG=1) + (cd ./$d; make COG=1) done Modified: branches/Cog/build.macos32x86/makeall =================================================================== --- branches/Cog/build.macos32x86/makeall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/makeall 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.* squeak.*; do if test -d "$d"; then - (cd $d;./mvm -A) + (cd ./$d;./mvm -A) else echo no $d directory found fi Modified: branches/Cog/build.macos32x86/makeallinstall =================================================================== --- branches/Cog/build.macos32x86/makeallinstall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/makeallinstall 2015-11-12 01:53:26 UTC (rev 3492) @@ -11,7 +11,7 @@ d=$td/installer PRODUCT=$1-$TAG.dmg if test -d "$d"; then - (cd $d;make) + (cd ./$d;make) test -f $d/$PRODUCT && mv $d/$PRODUCT ../products else echo no $d directory found Modified: branches/Cog/build.macos32x86/makeproduct =================================================================== --- branches/Cog/build.macos32x86/makeproduct 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/makeproduct 2015-11-12 01:53:26 UTC (rev 3492) @@ -3,7 +3,7 @@ PRODUCTDIRS="newspeak.cog.spur squeak.cog.spur squeak.cog.v3" for d in $PRODUCTDIRS; do if test -d "$d"; then - (cd $d;./mvm -A) + (cd ./$d;./mvm -A) else echo no $d directory found fi Modified: branches/Cog/build.macos32x86/makeproductinstall =================================================================== --- branches/Cog/build.macos32x86/makeproductinstall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/makeproductinstall 2015-11-12 01:53:26 UTC (rev 3492) @@ -10,7 +10,7 @@ d=$td/installer PRODUCT=$1-$TAG.dmg if test -d "$d"; then - (cd $d;make) + (cd ./$d;make) test -f $d/$PRODUCT && mv $d/$PRODUCT ../products else echo no $d directory found Modified: branches/Cog/build.macos32x86/makesista =================================================================== --- branches/Cog/build.macos32x86/makesista 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/makesista 2015-11-12 01:53:26 UTC (rev 3492) @@ -3,7 +3,7 @@ DIRS="squeak.sista.spur" for d in $DIRS; do if test -d "$d"; then - (cd $d;./mvm -A) + (cd ./$d;./mvm -A) else echo no $d directory found fi Modified: branches/Cog/build.macos32x86/makespur =================================================================== --- branches/Cog/build.macos32x86/makespur 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/makespur 2015-11-12 01:53:26 UTC (rev 3492) @@ -3,7 +3,7 @@ DIRS="newspeak.cog.spur newspeak.stack.spur squeak.cog.spur squeak.sista.spur squeak.stack.spur" for d in $DIRS; do if test -d "$d"; then - (cd $d;./mvm -A) + (cd ./$d;./mvm -A) else echo no $d directory found fi Modified: branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/GdbARMPlugin.xcodeproj/project.pbxproj 2015-11-12 01:53:26 UTC (rev 3492) @@ -13,7 +13,7 @@ 732788241AB7C73500BE5008 /* environ.c in Sources */ = {isa = PBXBuildFile; fileRef = 732787F11AB7A12A00BE5008 /* environ.c */; }; 737482B30EE7339F004E10F8 /* libopcodes.a in Frameworks */ = {isa = PBXBuildFile; fileRef = 737482B20EE7339F004E10F8 /* libopcodes.a */; }; 737482B50EE733BD004E10F8 /* libsim.a in Frameworks */ = {isa = PBXBuildFile; fileRef = 737482B40EE733BD004E10F8 /* libsim.a */; }; - 737482B70EE7343B004E10F8 /* sqGdbARMPlugin.c in Sources */ = {isa = PBXBuildFile; fileRef = 737482B60EE7343B004E10F8 /* sqGdbARMPlugin.c */; settings = {COMPILER_FLAGS = "-I../../../processors/ARM/mac/gdb-7.6/include -I../../../processors/ARM/mac/gdb-7.6/sim/arm -I../../../processors/ARM/mac/gdb-7.6/bfd"; }; }; + 737482B70EE7343B004E10F8 /* sqGdbARMPlugin.c in Sources */ = {isa = PBXBuildFile; fileRef = 737482B60EE7343B004E10F8 /* sqGdbARMPlugin.c */; settings = {COMPILER_FLAGS = "-I../../../processors/ARM/mac/gdb-7.10/include -I../../../processors/ARM/mac/gdb-7.10/sim/arm -I../../../processors/ARM/mac/gdb-7.10/bfd"; }; }; 8D01CCCE0486CAD60068D4B7 /* Carbon.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 08EA7FFBFE8413EDC02AAC07 /* Carbon.framework */; }; /* End PBXBuildFile section */ @@ -22,11 +22,11 @@ 73020E8C0EE714E60021D217 /* GdbARMPlugin.c */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.c; name = GdbARMPlugin.c; path = ../../../src/plugins/GdbARMPlugin/GdbARMPlugin.c; sourceTree = SOURCE_ROOT; }; 73020E8E0EE7158C0021D217 /* GdbARMPlugin.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; name = GdbARMPlugin.h; path = ../../../platforms/Cross/plugins/GdbARMPlugin/GdbARMPlugin.h; sourceTree = SOURCE_ROOT; }; 732787F11AB7A12A00BE5008 /* environ.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = environ.c; path = "../../../platforms/Mac OS/plugins/GdbARMPlugin/environ.c"; sourceTree = SOURCE_ROOT; }; - 732787F51AB7A40100BE5008 /* libiberty.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libiberty.a; path = "../../../processors/ARM/mac/binutils-2.25/libiberty/libiberty.a"; sourceTree = SOURCE_ROOT; }; - 737482B20EE7339F004E10F8 /* libopcodes.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libopcodes.a; path = "../../../processors/ARM/mac/gdb-7.6/opcodes/libopcodes.a"; sourceTree = SOURCE_ROOT; }; - 737482B40EE733BD004E10F8 /* libsim.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libsim.a; path = "../../../processors/ARM/mac/gdb-7.6/sim/arm/libsim.a"; sourceTree = SOURCE_ROOT; }; + 732787F51AB7A40100BE5008 /* libiberty.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libiberty.a; path = "../../gdbarm32/libiberty/libiberty.a"; sourceTree = SOURCE_ROOT; }; + 737482B20EE7339F004E10F8 /* libopcodes.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libopcodes.a; path = "../../gdbarm32/opcodes/libopcodes.a"; sourceTree = SOURCE_ROOT; }; + 737482B40EE733BD004E10F8 /* libsim.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libsim.a; path = "../../gdbarm32/sim/arm/libsim.a"; sourceTree = SOURCE_ROOT; }; 737482B60EE7343B004E10F8 /* sqGdbARMPlugin.c */ = {isa = PBXFileReference; explicitFileType = sourcecode.c.c; fileEncoding = 30; name = sqGdbARMPlugin.c; path = ../../../platforms/Cross/plugins/GdbARMPlugin/sqGdbARMPlugin.c; sourceTree = SOURCE_ROOT; }; - 73ADAA901AB79ED50085DAA8 /* libbfd.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libbfd.a; path = "../../../processors/ARM/mac/binutils-2.25/bfd/libbfd.a"; sourceTree = SOURCE_ROOT; }; + 73ADAA901AB79ED50085DAA8 /* libbfd.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libbfd.a; path = "../../gdbarm32/bfd/libbfd.a"; sourceTree = SOURCE_ROOT; }; 8D01CCD10486CAD60068D4B7 /* Info.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist; path = Info.plist; sourceTree = "<group>"; }; 8D01CCD20486CAD60068D4B7 /* GdbARMPlugin.bundle */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = GdbARMPlugin.bundle; sourceTree = BUILT_PRODUCTS_DIR; }; DA3A20F50AA63CBF0050B983 /* interp.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; name = interp.h; path = ../../../spursrc/vm/interp.h; sourceTree = SOURCE_ROOT; }; Modified: branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm 2015-11-12 01:53:26 UTC (rev 3492) @@ -134,9 +134,9 @@ fi # Build the GdbARMPlugin -# N.B. To build the plugin you also have to build the gdb ARM sim libraries in -# ../../processors/ARM/mac. -if test -f ../../processors/ARM/mac/gdb-7.6/opcodes/libopcodes.a; then +# N.B. To build the plugin you also have to build the gdb ARM sim +# libraries in ../gdbarm32. cd ../gdbarm32. Run conf.COG & makeem. +if test -f ../gdbarm32/opcodes/libopcodes.a; then echo GdbARMPlugin xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project GdbARMPlugin/GdbARMPlugin.xcodeproj xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project GdbARMPlugin/GdbARMPlugin.xcodeproj rm -rf "$DEST/Contents/Resources/GdbARMPlugin.bundle" Modified: branches/Cog/build.macos32x86/squeak.cog.spur/makevm =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/makevm 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos32x86/squeak.cog.spur/makevm 2015-11-12 01:53:26 UTC (rev 3492) @@ -138,9 +138,9 @@ fi # Build the GdbARMPlugin -# N.B. To build the plugin you also have to build the gdb ARM sim libraries in -# ../../processors/ARM/mac. -if test -f ../../processors/ARM/mac/gdb-7.6/opcodes/libopcodes.a; then +# N.B. To build the plugin you also have to build the gdb ARM sim +# libraries in ../gdbarm32. cd ../gdbarm32. Run conf.COG & makeem. +if test -f ../gdbarm32/opcodes/libopcodes.a; then echo GdbARMPlugin xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project GdbARMPlugin/GdbARMPlugin.xcodeproj xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project GdbARMPlugin/GdbARMPlugin.xcodeproj rm -rf "$DEST/Contents/Resources/GdbARMPlugin.bundle" Modified: branches/Cog/build.macos64x64/makeall =================================================================== --- branches/Cog/build.macos64x64/makeall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos64x64/makeall 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.* squeak.*; do if test -d "$d"; then - (cd $d;./mvm -A) + (cd ./$d;./mvm -A) else echo no $d directory found fi Modified: branches/Cog/build.macos64x64/makeallinstall =================================================================== --- branches/Cog/build.macos64x64/makeallinstall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos64x64/makeallinstall 2015-11-12 01:53:26 UTC (rev 3492) @@ -11,7 +11,7 @@ d=$td/installer PRODUCT=$1-$TAG.dmg if test -d "$d"; then - (cd $d;make) + (cd ./$d;make) test -f $d/$PRODUCT && mv $d/$PRODUCT ../products else echo no $d directory found Modified: branches/Cog/build.macos64x64/makeproduct =================================================================== --- branches/Cog/build.macos64x64/makeproduct 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos64x64/makeproduct 2015-11-12 01:53:26 UTC (rev 3492) @@ -3,7 +3,7 @@ PRODUCTDIRS="newspeak.cog.spur squeak.cog.spur" for d in $PRODUCTDIRS; do if test -d "$d"; then - (cd $d;./mvm -A) + (cd ./$d;./mvm -A) else echo no $d directory found fi Modified: branches/Cog/build.macos64x64/makeproductinstall =================================================================== --- branches/Cog/build.macos64x64/makeproductinstall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos64x64/makeproductinstall 2015-11-12 01:53:26 UTC (rev 3492) @@ -10,7 +10,7 @@ d=$td/installer PRODUCT=$1-$TAG.dmg if test -d "$d"; then - (cd $d;make) + (cd ./$d;make) test -f $d/$PRODUCT && mv $d/$PRODUCT ../products else echo no $d directory found Modified: branches/Cog/build.macos64x64/makesista =================================================================== --- branches/Cog/build.macos64x64/makesista 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos64x64/makesista 2015-11-12 01:53:26 UTC (rev 3492) @@ -3,7 +3,7 @@ DIRS="squeak.sista.spur" for d in $DIRS; do if test -d "$d"; then - (cd $d;./mvm -A) + (cd ./$d;./mvm -A) else echo no $d directory found fi Modified: branches/Cog/build.macos64x64/makespur =================================================================== --- branches/Cog/build.macos64x64/makespur 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.macos64x64/makespur 2015-11-12 01:53:26 UTC (rev 3492) @@ -3,7 +3,7 @@ DIRS="newspeak.cog.spur newspeak.stack.spur squeak.cog.spur squeak.sista.spur squeak.stack.spur" for d in $DIRS; do if test -d "$d"; then - (cd $d;./mvm -A) + (cd ./$d;./mvm -A) else echo no $d directory found fi Modified: branches/Cog/build.win32x86/makeall =================================================================== --- branches/Cog/build.win32x86/makeall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.win32x86/makeall 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.* squeak.*; do if test -d "$d"; then - (cd $d;./mvm) + (cd ./$d;./mvm) else echo no $d directory found fi Modified: branches/Cog/build.win32x86/makeallinstall =================================================================== --- branches/Cog/build.win32x86/makeallinstall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.win32x86/makeallinstall 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.*/installer squeak.*/installer; do if test -d "$d"; then - (cd $d;make) + (cd ./$d;make) else echo no $d directory found fi Modified: branches/Cog/build.win32x86/makeproduct =================================================================== --- branches/Cog/build.win32x86/makeproduct 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.win32x86/makeproduct 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.spur squeak.cog.spur squeak.cog.v3; do if test -d "$d"; then - (cd $d;./mvm) + (cd ./$d;./mvm) else echo no $d directory found fi Modified: branches/Cog/build.win32x86/makeproductinstall =================================================================== --- branches/Cog/build.win32x86/makeproductinstall 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/build.win32x86/makeproductinstall 2015-11-12 01:53:26 UTC (rev 3492) @@ -2,7 +2,7 @@ trap 'exit 2' HUP INT PIPE TERM for d in newspeak.cog.spur/installer; do if test -d "$d"; then - (cd $d;make) + (cd ./$d;make) else echo no $d directory found fi Added: branches/Cog/platforms/unix/plugins/BochsIA32Plugin/HowToBuild =================================================================== --- branches/Cog/platforms/unix/plugins/BochsIA32Plugin/HowToBuild (rev 0) +++ branches/Cog/platforms/unix/plugins/BochsIA32Plugin/HowToBuild 2015-11-12 01:53:26 UTC (rev 3492) @@ -0,0 +1,13 @@ +Building the BochsIA32Plugin +------------------------------ + +Building on Linux and Mac OS X +------------------------------ +(so far tried on CentOS 6.5 32-bit, Ubuntu 12.04 LTS 32bit, Mac OS X 10.9) + +cd to the bochsx86 buld directory under the relevant linux or macos platform +build directory, e.g. build.linux32x86/bochsx86, or build.macos32x86/bochsx86. + +run conf.COG + +run ../../processors/IA32/bochs/makeem Property changes on: branches/Cog/platforms/unix/plugins/BochsIA32Plugin/HowToBuild ___________________________________________________________________ Added: svn:executable + * Added: branches/Cog/platforms/unix/plugins/BochsIA32Plugin/acinclude.m4 =================================================================== --- branches/Cog/platforms/unix/plugins/BochsIA32Plugin/acinclude.m4 (rev 0) +++ branches/Cog/platforms/unix/plugins/BochsIA32Plugin/acinclude.m4 2015-11-12 01:53:26 UTC (rev 3492) @@ -0,0 +1,9 @@ +# To build the BochsIA32Plugin one must build the Bochs support libraries +if test -f ../../bochsx86/cpu/libcpu.a \ + -a -f ../../bochsx86/disasm/libdisasm.a \ + -a -f ../../bochsx86/fpu/libfpu.a; then + echo "bochs support libraries have been built; building BochsIA32Plugin" +else + echo "../../bochsx86 libraries have not been built; not building BochsIA32Plugin" + AC_PLUGIN_DISABLE +fi Added: branches/Cog/platforms/unix/plugins/BochsX64Plugin/HowToBuild =================================================================== --- branches/Cog/platforms/unix/plugins/BochsX64Plugin/HowToBuild (rev 0) +++ branches/Cog/platforms/unix/plugins/BochsX64Plugin/HowToBuild 2015-11-12 01:53:26 UTC (rev 3492) @@ -0,0 +1,13 @@ +Building the BochsX64Plugin +------------------------------ + +Building on Linux and Mac OS X +------------------------------ +(so far tried on CentOS 6.5 32-bit, Ubuntu 12.04 LTS 32bit, Mac OS X 10.9) + +cd to the bochsx86 buld directory under the relevant linux or macos platform +build directory, e.g. build.linux32x86/bochsx64, or build.macos32x86/bochsx64. + +run conf.COG + +run ../../processors/IA32/bochs/makeem Property changes on: branches/Cog/platforms/unix/plugins/BochsX64Plugin/HowToBuild ___________________________________________________________________ Added: svn:executable + * Added: branches/Cog/platforms/unix/plugins/BochsX64Plugin/acinclude.m4 =================================================================== --- branches/Cog/platforms/unix/plugins/BochsX64Plugin/acinclude.m4 (rev 0) +++ branches/Cog/platforms/unix/plugins/BochsX64Plugin/acinclude.m4 2015-11-12 01:53:26 UTC (rev 3492) @@ -0,0 +1,9 @@ +# To build the BochsX64Plugin one must build the Bochs support libraries +if test -f ../../bochsx64/cpu/libcpu.a \ + -a -f ../../bochsx64/disasm/libdisasm.a \ + -a -f ../../bochsx64/fpu/libfpu.a; then + echo "bochs support libraries have been built; building BochsX64Plugin" +else + echo "../../bochsx64 libraries have not been built; not building BochsX64Plugin" + AC_PLUGIN_DISABLE +fi Modified: branches/Cog/platforms/unix/plugins/GdbARMPlugin/HowToBuild =================================================================== --- branches/Cog/platforms/unix/plugins/GdbARMPlugin/HowToBuild 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/platforms/unix/plugins/GdbARMPlugin/HowToBuild 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,6 +1,7 @@ Building the GdbARMPlugin ------------------------------ +Ignore this section if not using the standard Cog source tree: Build the normal VM on your Platform. Consult Cog/{cygwinbuild|unixbuild|macbuild}/HowToBuild for additional information. When generating sources, update to the latest @@ -13,7 +14,19 @@ the return in the false block, in order to skip when a plugin is not found, instead of aborting the generation process. +:Ignopre preceding section if not using the standard Cog source tree. +Building on Linux +------------------------------ +(so far tried on CentOS 6.5 32-bit, Ubuntu 12.04 LTS 32bit) + +cd to the gdbarm32 buld directory under the relevant linux platform build +directory, e.g. build.linux32x86/gdbarm32. + +run conf.COG + +run makeem + Building on Windows ------------------------------ (so far tried with Windows 7 64bit unsing mingw/MSYS 32bit) @@ -53,10 +66,6 @@ Change <cog>/cygwinbuild/plugins.ext to include GdbARMPlugin. Change to gcc 3, then build the VM (again). -Building on Linux ------------------------------- -(so far tried on Ubuntu 12.04 LTS 32bit) - Download the gdb sources (http://ftp.gnu.org/gnu/gdb) and unpack them. Change Makefile and Makefile.unix, setting GDBBUILDFOLDER to the correct place. Modified: branches/Cog/platforms/unix/plugins/GdbARMPlugin/Makefile.inc =================================================================== --- branches/Cog/platforms/unix/plugins/GdbARMPlugin/Makefile.inc 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/platforms/unix/plugins/GdbARMPlugin/Makefile.inc 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,11 +1,11 @@ -# This assumes you untar the gdb 7.6 source in processors/ARM/gdb-7.6/ -GDBBUILDFOLDER = ../../../../processors/ARM/gdb-7.6/ +GDBBUILDFOLDER = ../../../gdbarm32 +GDBSOURCEFOLDER = ../../../../processors/ARM/gdb-7.6/ XCFLAGS = -m32 -DNEED_UI_LOOP_HOOK -XINCLUDES += -I$(GDBBUILDFOLDER)/include -XINCLUDES += -I$(GDBBUILDFOLDER)/sim/arm +XINCLUDES += -I$(GDBSOURCEFOLDER)/include +XINCLUDES += -I$(GDBSOURCEFOLDER)/sim/arm XLDFLAGS= $(GDBBUILDFOLDER)/sim/arm/libsim.a \ - $(GDBBUILDFOLDER)/opcodes/libopcodes.a \ - -lbfd -liberty \ - -Wl + $(GDBBUILDFOLDER)/opcodes/libopcodes.a \ + -lbfd -liberty \ + -Wl Modified: branches/Cog/platforms/unix/plugins/GdbARMPlugin/acinclude.m4 =================================================================== --- branches/Cog/platforms/unix/plugins/GdbARMPlugin/acinclude.m4 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/platforms/unix/plugins/GdbARMPlugin/acinclude.m4 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,7 +1,7 @@ # To build the GdbARMPlugin one must build libsim.a from gdb -if test -f ../../../processors/ARM/gdb-7.6/sim/arm/libsim.a; then +if test -f ../../gdbarm32/sim/arm/libsim.a; then echo "libsim.a has been built; building GdbARMPlugin" else - echo "/processors/ARM/gdb-7.6/sim/arm/libsim.a has not been built; not building GdbARMPlugin" + echo "../../gdbarm32/sim/arm/libsim.a has not been built; not building GdbARMPlugin" AC_PLUGIN_DISABLE fi Deleted: branches/Cog/processors/ARM/gdb-7.10/opcodes/Makefile =================================================================== --- branches/Cog/processors/ARM/gdb-7.10/opcodes/Makefile 2015-11-11 22:48:34 UTC (rev 3491) +++ branches/Cog/processors/ARM/gdb-7.10/opcodes/Makefile 2015-11-12 01:53:26 UTC (rev 3492) @@ -1,1490 +0,0 @@ -# Makefile.in generated by automake 1.11.1 from Makefile.am. -# Makefile. Generated from Makefile.in by configure. - -# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, -# Inc. -# This Makefile.in is free software; the Free Software Foundation -# gives unlimited permission to copy and/or distribute it, -# with or without modifications, as long as this notice is preserved. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY, to the extent permitted by law; without -# even the implied warranty of MERCHANTABILITY or FITNESS FOR A -# PARTICULAR PURPOSE. - - - -# -# Copyright (C) 2012-2015 Free Software Foundation, Inc. -# -# This file is free software; you can redistribute it and/or modify @@ Diff output truncated at 50000 characters. @@

1 0

[commit][3491] Add Tim Olson's gdb-7. 10-based armsim work that adds floating point support.
by commits＠squeakvm.org 11 Nov '15

11 Nov '15

Revision: 3491 Author: eliot Date: 2015-11-11 14:48:34 -0800 (Wed, 11 Nov 2015) Log Message: ----------- Add Tim Olson's gdb-7.10-based armsim work that adds floating point support. Add a build directory to build.macos32x86 to build the libs for that platform. Modified Paths: -------------- branches/Cog/processors/ARM/README Added Paths: ----------- branches/Cog/build.macos32x86/gdbarm32/ branches/Cog/build.macos32x86/gdbarm32/conf.COG branches/Cog/build.macos32x86/gdbarm32/makeem branches/Cog/processors/ARM/TODO branches/Cog/processors/ARM/gdb-7.10/ branches/Cog/processors/ARM/gdb-7.10/COPYING branches/Cog/processors/ARM/gdb-7.10/COPYING.LIB branches/Cog/processors/ARM/gdb-7.10/COPYING3 branches/Cog/processors/ARM/gdb-7.10/COPYING3.LIB branches/Cog/processors/ARM/gdb-7.10/ChangeLog branches/Cog/processors/ARM/gdb-7.10/MAINTAINERS branches/Cog/processors/ARM/gdb-7.10/Makefile.def branches/Cog/processors/ARM/gdb-7.10/Makefile.in branches/Cog/processors/ARM/gdb-7.10/Makefile.tpl branches/Cog/processors/ARM/gdb-7.10/README branches/Cog/processors/ARM/gdb-7.10/README-maintainer-mode branches/Cog/processors/ARM/gdb-7.10/bfd/ branches/Cog/processors/ARM/gdb-7.10/bfd/.gitignore branches/Cog/processors/ARM/gdb-7.10/bfd/COPYING branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-0001 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-0203 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2004 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2005 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2006 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2007 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2008 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2009 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2010 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2011 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2012 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2013 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-2014 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-9193 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-9495 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-9697 branches/Cog/processors/ARM/gdb-7.10/bfd/ChangeLog-9899 branches/Cog/processors/ARM/gdb-7.10/bfd/MAINTAINERS branches/Cog/processors/ARM/gdb-7.10/bfd/Makefile.am branches/Cog/processors/ARM/gdb-7.10/bfd/Makefile.in branches/Cog/processors/ARM/gdb-7.10/bfd/PORTING branches/Cog/processors/ARM/gdb-7.10/bfd/README branches/Cog/processors/ARM/gdb-7.10/bfd/TODO branches/Cog/processors/ARM/gdb-7.10/bfd/acinclude.m4 branches/Cog/processors/ARM/gdb-7.10/bfd/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/bfd/aix386-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/aix5ppc-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/aout-adobe.c branches/Cog/processors/ARM/gdb-7.10/bfd/aout-arm.c branches/Cog/processors/ARM/gdb-7.10/bfd/aout-cris.c branches/Cog/processors/ARM/gdb-7.10/bfd/aout-ns32k.c branches/Cog/processors/ARM/gdb-7.10/bfd/aout-sparcle.c branches/Cog/processors/ARM/gdb-7.10/bfd/aout-target.h branches/Cog/processors/ARM/gdb-7.10/bfd/aout-tic30.c branches/Cog/processors/ARM/gdb-7.10/bfd/aout0.c branches/Cog/processors/ARM/gdb-7.10/bfd/aout32.c branches/Cog/processors/ARM/gdb-7.10/bfd/aout64.c branches/Cog/processors/ARM/gdb-7.10/bfd/aoutf1.h branches/Cog/processors/ARM/gdb-7.10/bfd/aoutx.h branches/Cog/processors/ARM/gdb-7.10/bfd/archive.c branches/Cog/processors/ARM/gdb-7.10/bfd/archive64.c branches/Cog/processors/ARM/gdb-7.10/bfd/archures.c branches/Cog/processors/ARM/gdb-7.10/bfd/armnetbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/bfd-in.h branches/Cog/processors/ARM/gdb-7.10/bfd/bfd-in2.h branches/Cog/processors/ARM/gdb-7.10/bfd/bfd.c branches/Cog/processors/ARM/gdb-7.10/bfd/bfd.m4 branches/Cog/processors/ARM/gdb-7.10/bfd/bfdio.c branches/Cog/processors/ARM/gdb-7.10/bfd/bfdwin.c branches/Cog/processors/ARM/gdb-7.10/bfd/binary.c branches/Cog/processors/ARM/gdb-7.10/bfd/bout.c branches/Cog/processors/ARM/gdb-7.10/bfd/cache.c branches/Cog/processors/ARM/gdb-7.10/bfd/cf-i386lynx.c branches/Cog/processors/ARM/gdb-7.10/bfd/cf-sparclynx.c branches/Cog/processors/ARM/gdb-7.10/bfd/cisco-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-alpha.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-apollo.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-arm.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-aux.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-bfd.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-bfd.h branches/Cog/processors/ARM/gdb-7.10/bfd/coff-go32.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-h8300.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-h8500.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-i386.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-i860.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-i960.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-ia64.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-m68k.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-m88k.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-mcore.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-mips.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-ppc.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-rs6000.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-sh.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-sparc.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-stgo32.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-svm68k.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-tic30.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-tic4x.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-tic54x.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-tic80.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-u68k.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-w65.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-we32k.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-x86_64.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-z80.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff-z8k.c branches/Cog/processors/ARM/gdb-7.10/bfd/coff64-rs6000.c branches/Cog/processors/ARM/gdb-7.10/bfd/coffcode.h branches/Cog/processors/ARM/gdb-7.10/bfd/coffgen.c branches/Cog/processors/ARM/gdb-7.10/bfd/cofflink.c branches/Cog/processors/ARM/gdb-7.10/bfd/coffswap.h branches/Cog/processors/ARM/gdb-7.10/bfd/compress.c branches/Cog/processors/ARM/gdb-7.10/bfd/config.bfd branches/Cog/processors/ARM/gdb-7.10/bfd/config.in branches/Cog/processors/ARM/gdb-7.10/bfd/configure branches/Cog/processors/ARM/gdb-7.10/bfd/configure.ac branches/Cog/processors/ARM/gdb-7.10/bfd/configure.com branches/Cog/processors/ARM/gdb-7.10/bfd/configure.host branches/Cog/processors/ARM/gdb-7.10/bfd/corefile.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-aarch64.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-alpha.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-arc.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-arm.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-avr.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-bfin.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-cr16.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-cr16c.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-cris.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-crx.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-d10v.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-d30v.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-dlx.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-epiphany.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-fr30.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-frv.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-ft32.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-h8300.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-h8500.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-hppa.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-i370.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-i386.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-i860.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-i960.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-ia64-opc.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-ia64.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-iamcu.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-ip2k.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-iq2000.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-k1om.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-l1om.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-lm32.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m10200.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m10300.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m32c.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m32r.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m68hc11.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m68hc12.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m68k.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m88k.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m9s12x.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-m9s12xg.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-mcore.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-mep.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-metag.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-microblaze.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-mips.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-mmix.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-moxie.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-msp430.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-mt.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-nds32.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-nios2.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-ns32k.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-or1k.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-pdp11.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-pj.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-plugin.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-powerpc.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-rl78.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-rs6000.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-rx.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-s390.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-score.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-sh.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-sparc.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-spu.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-tic30.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-tic4x.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-tic54x.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-tic6x.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-tic80.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-tilegx.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-tilepro.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-v850.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-v850_rh850.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-vax.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-visium.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-w65.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-we32k.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-xc16x.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-xgate.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-xstormy16.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-xtensa.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-z80.c branches/Cog/processors/ARM/gdb-7.10/bfd/cpu-z8k.c branches/Cog/processors/ARM/gdb-7.10/bfd/demo64.c branches/Cog/processors/ARM/gdb-7.10/bfd/dep-in.sed branches/Cog/processors/ARM/gdb-7.10/bfd/development.sh branches/Cog/processors/ARM/gdb-7.10/bfd/doc/ branches/Cog/processors/ARM/gdb-7.10/bfd/doc/ChangeLog branches/Cog/processors/ARM/gdb-7.10/bfd/doc/ChangeLog-9103 branches/Cog/processors/ARM/gdb-7.10/bfd/doc/Makefile.am branches/Cog/processors/ARM/gdb-7.10/bfd/doc/Makefile.in branches/Cog/processors/ARM/gdb-7.10/bfd/doc/aoutx.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/archive.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/archures.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/bfd.info branches/Cog/processors/ARM/gdb-7.10/bfd/doc/bfd.texinfo branches/Cog/processors/ARM/gdb-7.10/bfd/doc/bfdint.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/bfdio.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/bfdsumm.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/bfdt.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/bfdver.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/bfdwin.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/cache.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/chew.c branches/Cog/processors/ARM/gdb-7.10/bfd/doc/chw8494 branches/Cog/processors/ARM/gdb-7.10/bfd/doc/coffcode.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/core.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/doc.str branches/Cog/processors/ARM/gdb-7.10/bfd/doc/elf.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/elfcode.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/fdl.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/format.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/hash.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/header.sed branches/Cog/processors/ARM/gdb-7.10/bfd/doc/init.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/libbfd.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/linker.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/makefile.vms branches/Cog/processors/ARM/gdb-7.10/bfd/doc/mmo.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/opncls.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/proto.str branches/Cog/processors/ARM/gdb-7.10/bfd/doc/reloc.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/section.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/syms.texi branches/Cog/processors/ARM/gdb-7.10/bfd/doc/targets.texi branches/Cog/processors/ARM/gdb-7.10/bfd/dwarf1.c branches/Cog/processors/ARM/gdb-7.10/bfd/dwarf2.c branches/Cog/processors/ARM/gdb-7.10/bfd/ecoff.c branches/Cog/processors/ARM/gdb-7.10/bfd/ecofflink.c branches/Cog/processors/ARM/gdb-7.10/bfd/ecoffswap.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf-attrs.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf-bfd.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf-eh-frame.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf-hppa.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf-ifunc.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf-linux-psinfo.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf-m10200.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf-m10300.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf-nacl.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf-nacl.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf-s390-common.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf-strtab.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf-vxworks.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf-vxworks.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-am33lin.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-arc.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-arm.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-avr.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-avr.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-bfin.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-cr16.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-cr16c.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-cris.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-crx.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-d10v.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-d30v.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-dlx.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-epiphany.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-fr30.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-frv.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-ft32.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-gen.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-h8300.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-hppa.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-hppa.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-i370.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-i386.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-i860.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-i960.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-ip2k.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-iq2000.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-lm32.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-m32c.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-m32r.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-m68hc11.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-m68hc12.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-m68hc1x.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-m68hc1x.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-m68k.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-m88k.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-mcore.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-mep.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-metag.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-metag.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-microblaze.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-mips.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-moxie.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-msp430.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-mt.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-nds32.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-nds32.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-nios2.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-nios2.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-or1k.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-pj.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-ppc.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-ppc.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-rl78.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-rx.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-rx.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-s390.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-score.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-score.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-score7.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-sh-relocs.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-sh-symbian.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-sh.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-sh64-com.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-sh64.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-sh64.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-sparc.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-spu.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-spu.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-tic6x.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-tic6x.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-tilegx.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-tilegx.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-tilepro.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-tilepro.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-v850.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-vax.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-visium.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-xc16x.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-xgate.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-xgate.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-xstormy16.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32-xtensa.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf32.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-alpha.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-gen.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-hppa.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-hppa.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-ia64-vms.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-mips.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-mmix.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-ppc.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-ppc.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-s390.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-sh64.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-sparc.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-tilegx.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-tilegx.h branches/Cog/processors/ARM/gdb-7.10/bfd/elf64-x86-64.c branches/Cog/processors/ARM/gdb-7.10/bfd/elf64.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfcode.h branches/Cog/processors/ARM/gdb-7.10/bfd/elfcore.h branches/Cog/processors/ARM/gdb-7.10/bfd/elflink.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfn32-mips.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfnn-aarch64.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfnn-ia64.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-aarch64.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-aarch64.h branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-ia64.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-ia64.h branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-mips.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-mips.h branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-sparc.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-sparc.h branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-target.h branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-tilegx.c branches/Cog/processors/ARM/gdb-7.10/bfd/elfxx-tilegx.h branches/Cog/processors/ARM/gdb-7.10/bfd/epoc-pe-arm.c branches/Cog/processors/ARM/gdb-7.10/bfd/epoc-pei-arm.c branches/Cog/processors/ARM/gdb-7.10/bfd/format.c branches/Cog/processors/ARM/gdb-7.10/bfd/freebsd.h branches/Cog/processors/ARM/gdb-7.10/bfd/gen-aout.c branches/Cog/processors/ARM/gdb-7.10/bfd/genlink.h branches/Cog/processors/ARM/gdb-7.10/bfd/go32stub.h branches/Cog/processors/ARM/gdb-7.10/bfd/hash.c branches/Cog/processors/ARM/gdb-7.10/bfd/host-aout.c branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/ branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/alphalinux.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/alphavms.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/decstation.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/delta68.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/dpx2.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/hp300bsd.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/i386bsd.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/i386linux.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/i386mach3.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/i386sco.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/i860mach3.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/m68kaux.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/m68klinux.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/m88kmach3.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/mipsbsd.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/mipsmach3.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/news-mips.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/news.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/pc532mach.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/riscos.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/symmetry.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/tahoe.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/vaxbsd.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/vaxlinux.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/vaxult.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/vaxult2.h branches/Cog/processors/ARM/gdb-7.10/bfd/hosts/x86-64linux.h branches/Cog/processors/ARM/gdb-7.10/bfd/hp300bsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/hp300hpux.c branches/Cog/processors/ARM/gdb-7.10/bfd/hppabsd-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/hpux-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386aout.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386bsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386dynix.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386freebsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386linux.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386lynx.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386mach3.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386msdos.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386netbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/i386os9k.c branches/Cog/processors/ARM/gdb-7.10/bfd/ieee.c branches/Cog/processors/ARM/gdb-7.10/bfd/ihex.c branches/Cog/processors/ARM/gdb-7.10/bfd/init.c branches/Cog/processors/ARM/gdb-7.10/bfd/irix-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/libaout.h branches/Cog/processors/ARM/gdb-7.10/bfd/libbfd-in.h branches/Cog/processors/ARM/gdb-7.10/bfd/libbfd.c branches/Cog/processors/ARM/gdb-7.10/bfd/libbfd.h branches/Cog/processors/ARM/gdb-7.10/bfd/libcoff-in.h branches/Cog/processors/ARM/gdb-7.10/bfd/libcoff.h branches/Cog/processors/ARM/gdb-7.10/bfd/libecoff.h branches/Cog/processors/ARM/gdb-7.10/bfd/libhppa.h branches/Cog/processors/ARM/gdb-7.10/bfd/libieee.h branches/Cog/processors/ARM/gdb-7.10/bfd/libnlm.h branches/Cog/processors/ARM/gdb-7.10/bfd/liboasys.h branches/Cog/processors/ARM/gdb-7.10/bfd/libpei.h branches/Cog/processors/ARM/gdb-7.10/bfd/libxcoff.h branches/Cog/processors/ARM/gdb-7.10/bfd/linker.c branches/Cog/processors/ARM/gdb-7.10/bfd/lynx-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/m68k4knetbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/m68klinux.c branches/Cog/processors/ARM/gdb-7.10/bfd/m68knetbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/m88kmach3.c branches/Cog/processors/ARM/gdb-7.10/bfd/m88kopenbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/mach-o-i386.c branches/Cog/processors/ARM/gdb-7.10/bfd/mach-o-target.c branches/Cog/processors/ARM/gdb-7.10/bfd/mach-o-x86-64.c branches/Cog/processors/ARM/gdb-7.10/bfd/mach-o.c branches/Cog/processors/ARM/gdb-7.10/bfd/mach-o.h branches/Cog/processors/ARM/gdb-7.10/bfd/makefile.vms branches/Cog/processors/ARM/gdb-7.10/bfd/mep-relocs.pl branches/Cog/processors/ARM/gdb-7.10/bfd/merge.c branches/Cog/processors/ARM/gdb-7.10/bfd/mipsbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/mmo.c branches/Cog/processors/ARM/gdb-7.10/bfd/netbsd-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/netbsd.h branches/Cog/processors/ARM/gdb-7.10/bfd/newsos3.c branches/Cog/processors/ARM/gdb-7.10/bfd/nlm-target.h branches/Cog/processors/ARM/gdb-7.10/bfd/nlm.c branches/Cog/processors/ARM/gdb-7.10/bfd/nlm32-alpha.c branches/Cog/processors/ARM/gdb-7.10/bfd/nlm32-i386.c branches/Cog/processors/ARM/gdb-7.10/bfd/nlm32-ppc.c branches/Cog/processors/ARM/gdb-7.10/bfd/nlm32-sparc.c branches/Cog/processors/ARM/gdb-7.10/bfd/nlm32.c branches/Cog/processors/ARM/gdb-7.10/bfd/nlm64.c branches/Cog/processors/ARM/gdb-7.10/bfd/nlmcode.h branches/Cog/processors/ARM/gdb-7.10/bfd/nlmswap.h branches/Cog/processors/ARM/gdb-7.10/bfd/ns32k.h branches/Cog/processors/ARM/gdb-7.10/bfd/ns32knetbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/oasys.c branches/Cog/processors/ARM/gdb-7.10/bfd/opncls.c branches/Cog/processors/ARM/gdb-7.10/bfd/osf-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/pc532-mach.c branches/Cog/processors/ARM/gdb-7.10/bfd/pdp11.c branches/Cog/processors/ARM/gdb-7.10/bfd/pe-arm-wince.c branches/Cog/processors/ARM/gdb-7.10/bfd/pe-arm.c branches/Cog/processors/ARM/gdb-7.10/bfd/pe-i386.c branches/Cog/processors/ARM/gdb-7.10/bfd/pe-mcore.c branches/Cog/processors/ARM/gdb-7.10/bfd/pe-mips.c branches/Cog/processors/ARM/gdb-7.10/bfd/pe-ppc.c branches/Cog/processors/ARM/gdb-7.10/bfd/pe-sh.c branches/Cog/processors/ARM/gdb-7.10/bfd/pe-x86_64.c branches/Cog/processors/ARM/gdb-7.10/bfd/peXXigen.c branches/Cog/processors/ARM/gdb-7.10/bfd/pef-traceback.h branches/Cog/processors/ARM/gdb-7.10/bfd/pef.c branches/Cog/processors/ARM/gdb-7.10/bfd/pef.h branches/Cog/processors/ARM/gdb-7.10/bfd/pei-arm-wince.c branches/Cog/processors/ARM/gdb-7.10/bfd/pei-arm.c branches/Cog/processors/ARM/gdb-7.10/bfd/pei-i386.c branches/Cog/processors/ARM/gdb-7.10/bfd/pei-ia64.c branches/Cog/processors/ARM/gdb-7.10/bfd/pei-mcore.c branches/Cog/processors/ARM/gdb-7.10/bfd/pei-mips.c branches/Cog/processors/ARM/gdb-7.10/bfd/pei-ppc.c branches/Cog/processors/ARM/gdb-7.10/bfd/pei-sh.c branches/Cog/processors/ARM/gdb-7.10/bfd/pei-x86_64.c branches/Cog/processors/ARM/gdb-7.10/bfd/peicode.h branches/Cog/processors/ARM/gdb-7.10/bfd/plugin.c branches/Cog/processors/ARM/gdb-7.10/bfd/plugin.h branches/Cog/processors/ARM/gdb-7.10/bfd/po/ branches/Cog/processors/ARM/gdb-7.10/bfd/po/BLD-POTFILES.in branches/Cog/processors/ARM/gdb-7.10/bfd/po/Make-in branches/Cog/processors/ARM/gdb-7.10/bfd/po/SRC-POTFILES.in branches/Cog/processors/ARM/gdb-7.10/bfd/po/bfd.pot branches/Cog/processors/ARM/gdb-7.10/bfd/po/da.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/da.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/es.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/es.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/fi.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/fi.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/fr.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/fr.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/id.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/id.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/ja.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/ja.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/ro.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/ro.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/ru.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/ru.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/rw.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/rw.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/sv.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/sv.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/tr.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/tr.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/uk.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/uk.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/vi.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/vi.po branches/Cog/processors/ARM/gdb-7.10/bfd/po/zh_CN.gmo branches/Cog/processors/ARM/gdb-7.10/bfd/po/zh_CN.po branches/Cog/processors/ARM/gdb-7.10/bfd/ppcboot.c branches/Cog/processors/ARM/gdb-7.10/bfd/ptrace-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/reloc.c branches/Cog/processors/ARM/gdb-7.10/bfd/reloc16.c branches/Cog/processors/ARM/gdb-7.10/bfd/riscix.c branches/Cog/processors/ARM/gdb-7.10/bfd/rs6000-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/sco5-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/section.c branches/Cog/processors/ARM/gdb-7.10/bfd/simple.c branches/Cog/processors/ARM/gdb-7.10/bfd/som.c branches/Cog/processors/ARM/gdb-7.10/bfd/som.h branches/Cog/processors/ARM/gdb-7.10/bfd/sparclinux.c branches/Cog/processors/ARM/gdb-7.10/bfd/sparclynx.c branches/Cog/processors/ARM/gdb-7.10/bfd/sparcnetbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/srec.c branches/Cog/processors/ARM/gdb-7.10/bfd/stab-syms.c branches/Cog/processors/ARM/gdb-7.10/bfd/stabs.c branches/Cog/processors/ARM/gdb-7.10/bfd/stamp-h.in branches/Cog/processors/ARM/gdb-7.10/bfd/sunos.c branches/Cog/processors/ARM/gdb-7.10/bfd/syms.c branches/Cog/processors/ARM/gdb-7.10/bfd/sysdep.h branches/Cog/processors/ARM/gdb-7.10/bfd/targets.c branches/Cog/processors/ARM/gdb-7.10/bfd/targmatch.sed branches/Cog/processors/ARM/gdb-7.10/bfd/tekhex.c branches/Cog/processors/ARM/gdb-7.10/bfd/trad-core.c branches/Cog/processors/ARM/gdb-7.10/bfd/vax1knetbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/vaxbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/vaxnetbsd.c branches/Cog/processors/ARM/gdb-7.10/bfd/verilog.c branches/Cog/processors/ARM/gdb-7.10/bfd/versados.c branches/Cog/processors/ARM/gdb-7.10/bfd/version.h branches/Cog/processors/ARM/gdb-7.10/bfd/version.m4 branches/Cog/processors/ARM/gdb-7.10/bfd/vms-alpha.c branches/Cog/processors/ARM/gdb-7.10/bfd/vms-lib.c branches/Cog/processors/ARM/gdb-7.10/bfd/vms-misc.c branches/Cog/processors/ARM/gdb-7.10/bfd/vms.h branches/Cog/processors/ARM/gdb-7.10/bfd/warning.m4 branches/Cog/processors/ARM/gdb-7.10/bfd/xcofflink.c branches/Cog/processors/ARM/gdb-7.10/bfd/xsym.c branches/Cog/processors/ARM/gdb-7.10/bfd/xsym.h branches/Cog/processors/ARM/gdb-7.10/bfd/xtensa-isa.c branches/Cog/processors/ARM/gdb-7.10/bfd/xtensa-modules.c branches/Cog/processors/ARM/gdb-7.10/compile branches/Cog/processors/ARM/gdb-7.10/config/ branches/Cog/processors/ARM/gdb-7.10/config/ChangeLog branches/Cog/processors/ARM/gdb-7.10/config/acinclude.m4 branches/Cog/processors/ARM/gdb-7.10/config/acx.m4 branches/Cog/processors/ARM/gdb-7.10/config/asmcfi.m4 branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-O1.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-O3.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-asan.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-debug-big.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-debug-ckovw.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-debug-lean.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-debug-lib.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-debug.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-lto.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-time.mk branches/Cog/processors/ARM/gdb-7.10/config/bootstrap-ubsan.mk branches/Cog/processors/ARM/gdb-7.10/config/codeset.m4 branches/Cog/processors/ARM/gdb-7.10/config/depstand.m4 branches/Cog/processors/ARM/gdb-7.10/config/dfp.m4 branches/Cog/processors/ARM/gdb-7.10/config/elf.m4 branches/Cog/processors/ARM/gdb-7.10/config/enable.m4 branches/Cog/processors/ARM/gdb-7.10/config/extensions.m4 branches/Cog/processors/ARM/gdb-7.10/config/futex.m4 branches/Cog/processors/ARM/gdb-7.10/config/gc++filt.m4 branches/Cog/processors/ARM/gdb-7.10/config/gettext-sister.m4 branches/Cog/processors/ARM/gdb-7.10/config/gettext.m4 branches/Cog/processors/ARM/gdb-7.10/config/glibc21.m4 branches/Cog/processors/ARM/gdb-7.10/config/gthr.m4 branches/Cog/processors/ARM/gdb-7.10/config/gxx-include-dir.m4 branches/Cog/processors/ARM/gdb-7.10/config/iconv.m4 branches/Cog/processors/ARM/gdb-7.10/config/intdiv0.m4 branches/Cog/processors/ARM/gdb-7.10/config/inttypes-pri.m4 branches/Cog/processors/ARM/gdb-7.10/config/inttypes.m4 branches/Cog/processors/ARM/gdb-7.10/config/inttypes_h.m4 branches/Cog/processors/ARM/gdb-7.10/config/isl.m4 branches/Cog/processors/ARM/gdb-7.10/config/largefile.m4 branches/Cog/processors/ARM/gdb-7.10/config/lcmessage.m4 branches/Cog/processors/ARM/gdb-7.10/config/ld-symbolic.m4 branches/Cog/processors/ARM/gdb-7.10/config/lead-dot.m4 branches/Cog/processors/ARM/gdb-7.10/config/lib-ld.m4 branches/Cog/processors/ARM/gdb-7.10/config/lib-link.m4 branches/Cog/processors/ARM/gdb-7.10/config/lib-prefix.m4 branches/Cog/processors/ARM/gdb-7.10/config/libstdc++-raw-cxx.m4 branches/Cog/processors/ARM/gdb-7.10/config/lthostflags.m4 branches/Cog/processors/ARM/gdb-7.10/config/math.m4 branches/Cog/processors/ARM/gdb-7.10/config/mh-cygwin branches/Cog/processors/ARM/gdb-7.10/config/mh-darwin branches/Cog/processors/ARM/gdb-7.10/config/mh-djgpp branches/Cog/processors/ARM/gdb-7.10/config/mh-mingw branches/Cog/processors/ARM/gdb-7.10/config/mh-pa branches/Cog/processors/ARM/gdb-7.10/config/mh-pa-hpux10 branches/Cog/processors/ARM/gdb-7.10/config/mh-ppc-aix branches/Cog/processors/ARM/gdb-7.10/config/mmap.m4 branches/Cog/processors/ARM/gdb-7.10/config/mt-alphaieee branches/Cog/processors/ARM/gdb-7.10/config/mt-d30v branches/Cog/processors/ARM/gdb-7.10/config/mt-gnu branches/Cog/processors/ARM/gdb-7.10/config/mt-mips-elfoabi branches/Cog/processors/ARM/gdb-7.10/config/mt-mips-gnu branches/Cog/processors/ARM/gdb-7.10/config/mt-mips16-compat branches/Cog/processors/ARM/gdb-7.10/config/mt-nios2-elf branches/Cog/processors/ARM/gdb-7.10/config/mt-ospace branches/Cog/processors/ARM/gdb-7.10/config/mt-sde branches/Cog/processors/ARM/gdb-7.10/config/mt-spu branches/Cog/processors/ARM/gdb-7.10/config/multi.m4 branches/Cog/processors/ARM/gdb-7.10/config/nls.m4 branches/Cog/processors/ARM/gdb-7.10/config/no-executables.m4 branches/Cog/processors/ARM/gdb-7.10/config/override.m4 branches/Cog/processors/ARM/gdb-7.10/config/picflag.m4 branches/Cog/processors/ARM/gdb-7.10/config/plugins.m4 branches/Cog/processors/ARM/gdb-7.10/config/po.m4 branches/Cog/processors/ARM/gdb-7.10/config/proginstall.m4 branches/Cog/processors/ARM/gdb-7.10/config/progtest.m4 branches/Cog/processors/ARM/gdb-7.10/config/stdint.m4 branches/Cog/processors/ARM/gdb-7.10/config/stdint_h.m4 branches/Cog/processors/ARM/gdb-7.10/config/tcl.m4 branches/Cog/processors/ARM/gdb-7.10/config/tls.m4 branches/Cog/processors/ARM/gdb-7.10/config/uintmax_t.m4 branches/Cog/processors/ARM/gdb-7.10/config/ulonglong.m4 branches/Cog/processors/ARM/gdb-7.10/config/unwind_ipinfo.m4 branches/Cog/processors/ARM/gdb-7.10/config/warnings.m4 branches/Cog/processors/ARM/gdb-7.10/config/weakref.m4 branches/Cog/processors/ARM/gdb-7.10/config/zlib.m4 branches/Cog/processors/ARM/gdb-7.10/config-ml.in branches/Cog/processors/ARM/gdb-7.10/config.guess branches/Cog/processors/ARM/gdb-7.10/config.rpath branches/Cog/processors/ARM/gdb-7.10/config.sub branches/Cog/processors/ARM/gdb-7.10/configure branches/Cog/processors/ARM/gdb-7.10/configure.ac branches/Cog/processors/ARM/gdb-7.10/depcomp branches/Cog/processors/ARM/gdb-7.10/include/ branches/Cog/processors/ARM/gdb-7.10/include/COPYING branches/Cog/processors/ARM/gdb-7.10/include/COPYING3 branches/Cog/processors/ARM/gdb-7.10/include/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/ChangeLog-9103 branches/Cog/processors/ARM/gdb-7.10/include/MAINTAINERS branches/Cog/processors/ARM/gdb-7.10/include/alloca-conf.h branches/Cog/processors/ARM/gdb-7.10/include/ansidecl.h branches/Cog/processors/ARM/gdb-7.10/include/aout/ branches/Cog/processors/ARM/gdb-7.10/include/aout/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/aout/adobe.h branches/Cog/processors/ARM/gdb-7.10/include/aout/aout64.h branches/Cog/processors/ARM/gdb-7.10/include/aout/ar.h branches/Cog/processors/ARM/gdb-7.10/include/aout/dynix3.h branches/Cog/processors/ARM/gdb-7.10/include/aout/encap.h branches/Cog/processors/ARM/gdb-7.10/include/aout/host.h branches/Cog/processors/ARM/gdb-7.10/include/aout/hp.h branches/Cog/processors/ARM/gdb-7.10/include/aout/hp300hpux.h branches/Cog/processors/ARM/gdb-7.10/include/aout/hppa.h branches/Cog/processors/ARM/gdb-7.10/include/aout/ranlib.h branches/Cog/processors/ARM/gdb-7.10/include/aout/reloc.h branches/Cog/processors/ARM/gdb-7.10/include/aout/stab.def branches/Cog/processors/ARM/gdb-7.10/include/aout/stab_gnu.h branches/Cog/processors/ARM/gdb-7.10/include/aout/sun4.h branches/Cog/processors/ARM/gdb-7.10/include/bfdlink.h branches/Cog/processors/ARM/gdb-7.10/include/binary-io.h branches/Cog/processors/ARM/gdb-7.10/include/bout.h branches/Cog/processors/ARM/gdb-7.10/include/cgen/ branches/Cog/processors/ARM/gdb-7.10/include/cgen/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/cgen/basic-modes.h branches/Cog/processors/ARM/gdb-7.10/include/cgen/basic-ops.h branches/Cog/processors/ARM/gdb-7.10/include/cgen/bitset.h branches/Cog/processors/ARM/gdb-7.10/include/coff/ branches/Cog/processors/ARM/gdb-7.10/include/coff/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/coff/ChangeLog-9103 branches/Cog/processors/ARM/gdb-7.10/include/coff/alpha.h branches/Cog/processors/ARM/gdb-7.10/include/coff/apollo.h branches/Cog/processors/ARM/gdb-7.10/include/coff/arm.h branches/Cog/processors/ARM/gdb-7.10/include/coff/aux-coff.h branches/Cog/processors/ARM/gdb-7.10/include/coff/ecoff.h branches/Cog/processors/ARM/gdb-7.10/include/coff/external.h branches/Cog/processors/ARM/gdb-7.10/include/coff/go32exe.h branches/Cog/processors/ARM/gdb-7.10/include/coff/h8300.h branches/Cog/processors/ARM/gdb-7.10/include/coff/h8500.h branches/Cog/processors/ARM/gdb-7.10/include/coff/i386.h branches/Cog/processors/ARM/gdb-7.10/include/coff/i860.h branches/Cog/processors/ARM/gdb-7.10/include/coff/i960.h branches/Cog/processors/ARM/gdb-7.10/include/coff/ia64.h branches/Cog/processors/ARM/gdb-7.10/include/coff/internal.h branches/Cog/processors/ARM/gdb-7.10/include/coff/m68k.h branches/Cog/processors/ARM/gdb-7.10/include/coff/m88k.h branches/Cog/processors/ARM/gdb-7.10/include/coff/mcore.h branches/Cog/processors/ARM/gdb-7.10/include/coff/mips.h branches/Cog/processors/ARM/gdb-7.10/include/coff/mipspe.h branches/Cog/processors/ARM/gdb-7.10/include/coff/pe.h branches/Cog/processors/ARM/gdb-7.10/include/coff/powerpc.h branches/Cog/processors/ARM/gdb-7.10/include/coff/rs6000.h branches/Cog/processors/ARM/gdb-7.10/include/coff/rs6k64.h branches/Cog/processors/ARM/gdb-7.10/include/coff/sh.h branches/Cog/processors/ARM/gdb-7.10/include/coff/sparc.h branches/Cog/processors/ARM/gdb-7.10/include/coff/sym.h branches/Cog/processors/ARM/gdb-7.10/include/coff/symconst.h branches/Cog/processors/ARM/gdb-7.10/include/coff/ti.h branches/Cog/processors/ARM/gdb-7.10/include/coff/tic30.h branches/Cog/processors/ARM/gdb-7.10/include/coff/tic4x.h branches/Cog/processors/ARM/gdb-7.10/include/coff/tic54x.h branches/Cog/processors/ARM/gdb-7.10/include/coff/tic80.h branches/Cog/processors/ARM/gdb-7.10/include/coff/w65.h branches/Cog/processors/ARM/gdb-7.10/include/coff/we32k.h branches/Cog/processors/ARM/gdb-7.10/include/coff/x86_64.h branches/Cog/processors/ARM/gdb-7.10/include/coff/xcoff.h branches/Cog/processors/ARM/gdb-7.10/include/coff/z80.h branches/Cog/processors/ARM/gdb-7.10/include/coff/z8k.h branches/Cog/processors/ARM/gdb-7.10/include/demangle.h branches/Cog/processors/ARM/gdb-7.10/include/dis-asm.h branches/Cog/processors/ARM/gdb-7.10/include/dwarf2.def branches/Cog/processors/ARM/gdb-7.10/include/dwarf2.h branches/Cog/processors/ARM/gdb-7.10/include/dyn-string.h branches/Cog/processors/ARM/gdb-7.10/include/elf/ branches/Cog/processors/ARM/gdb-7.10/include/elf/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/elf/ChangeLog-9103 branches/Cog/processors/ARM/gdb-7.10/include/elf/aarch64.h branches/Cog/processors/ARM/gdb-7.10/include/elf/alpha.h branches/Cog/processors/ARM/gdb-7.10/include/elf/arc.h branches/Cog/processors/ARM/gdb-7.10/include/elf/arm.h branches/Cog/processors/ARM/gdb-7.10/include/elf/avr.h branches/Cog/processors/ARM/gdb-7.10/include/elf/bfin.h branches/Cog/processors/ARM/gdb-7.10/include/elf/common.h branches/Cog/processors/ARM/gdb-7.10/include/elf/cr16.h branches/Cog/processors/ARM/gdb-7.10/include/elf/cr16c.h branches/Cog/processors/ARM/gdb-7.10/include/elf/cris.h branches/Cog/processors/ARM/gdb-7.10/include/elf/crx.h branches/Cog/processors/ARM/gdb-7.10/include/elf/d10v.h branches/Cog/processors/ARM/gdb-7.10/include/elf/d30v.h branches/Cog/processors/ARM/gdb-7.10/include/elf/dlx.h branches/Cog/processors/ARM/gdb-7.10/include/elf/dwarf.h branches/Cog/processors/ARM/gdb-7.10/include/elf/epiphany.h branches/Cog/processors/ARM/gdb-7.10/include/elf/external.h branches/Cog/processors/ARM/gdb-7.10/include/elf/fr30.h branches/Cog/processors/ARM/gdb-7.10/include/elf/frv.h branches/Cog/processors/ARM/gdb-7.10/include/elf/ft32.h branches/Cog/processors/ARM/gdb-7.10/include/elf/h8.h branches/Cog/processors/ARM/gdb-7.10/include/elf/hppa.h branches/Cog/processors/ARM/gdb-7.10/include/elf/i370.h branches/Cog/processors/ARM/gdb-7.10/include/elf/i386.h branches/Cog/processors/ARM/gdb-7.10/include/elf/i860.h branches/Cog/processors/ARM/gdb-7.10/include/elf/i960.h branches/Cog/processors/ARM/gdb-7.10/include/elf/ia64.h branches/Cog/processors/ARM/gdb-7.10/include/elf/internal.h branches/Cog/processors/ARM/gdb-7.10/include/elf/ip2k.h branches/Cog/processors/ARM/gdb-7.10/include/elf/iq2000.h branches/Cog/processors/ARM/gdb-7.10/include/elf/lm32.h branches/Cog/processors/ARM/gdb-7.10/include/elf/m32c.h branches/Cog/processors/ARM/gdb-7.10/include/elf/m32r.h branches/Cog/processors/ARM/gdb-7.10/include/elf/m68hc11.h branches/Cog/processors/ARM/gdb-7.10/include/elf/m68k.h branches/Cog/processors/ARM/gdb-7.10/include/elf/mcore.h branches/Cog/processors/ARM/gdb-7.10/include/elf/mep.h branches/Cog/processors/ARM/gdb-7.10/include/elf/metag.h branches/Cog/processors/ARM/gdb-7.10/include/elf/microblaze.h branches/Cog/processors/ARM/gdb-7.10/include/elf/mips.h branches/Cog/processors/ARM/gdb-7.10/include/elf/mmix.h branches/Cog/processors/ARM/gdb-7.10/include/elf/mn10200.h branches/Cog/processors/ARM/gdb-7.10/include/elf/mn10300.h branches/Cog/processors/ARM/gdb-7.10/include/elf/moxie.h branches/Cog/processors/ARM/gdb-7.10/include/elf/msp430.h branches/Cog/processors/ARM/gdb-7.10/include/elf/mt.h branches/Cog/processors/ARM/gdb-7.10/include/elf/nds32.h branches/Cog/processors/ARM/gdb-7.10/include/elf/nios2.h branches/Cog/processors/ARM/gdb-7.10/include/elf/or1k.h branches/Cog/processors/ARM/gdb-7.10/include/elf/pj.h branches/Cog/processors/ARM/gdb-7.10/include/elf/ppc.h branches/Cog/processors/ARM/gdb-7.10/include/elf/ppc64.h branches/Cog/processors/ARM/gdb-7.10/include/elf/reloc-macros.h branches/Cog/processors/ARM/gdb-7.10/include/elf/rl78.h branches/Cog/processors/ARM/gdb-7.10/include/elf/rx.h branches/Cog/processors/ARM/gdb-7.10/include/elf/s390.h branches/Cog/processors/ARM/gdb-7.10/include/elf/score.h branches/Cog/processors/ARM/gdb-7.10/include/elf/sh.h branches/Cog/processors/ARM/gdb-7.10/include/elf/sparc.h branches/Cog/processors/ARM/gdb-7.10/include/elf/spu.h branches/Cog/processors/ARM/gdb-7.10/include/elf/tic6x-attrs.h branches/Cog/processors/ARM/gdb-7.10/include/elf/tic6x.h branches/Cog/processors/ARM/gdb-7.10/include/elf/tilegx.h branches/Cog/processors/ARM/gdb-7.10/include/elf/tilepro.h branches/Cog/processors/ARM/gdb-7.10/include/elf/v850.h branches/Cog/processors/ARM/gdb-7.10/include/elf/vax.h branches/Cog/processors/ARM/gdb-7.10/include/elf/visium.h branches/Cog/processors/ARM/gdb-7.10/include/elf/vxworks.h branches/Cog/processors/ARM/gdb-7.10/include/elf/x86-64.h branches/Cog/processors/ARM/gdb-7.10/include/elf/xc16x.h branches/Cog/processors/ARM/gdb-7.10/include/elf/xgate.h branches/Cog/processors/ARM/gdb-7.10/include/elf/xstormy16.h branches/Cog/processors/ARM/gdb-7.10/include/elf/xtensa.h branches/Cog/processors/ARM/gdb-7.10/include/fibheap.h branches/Cog/processors/ARM/gdb-7.10/include/filenames.h branches/Cog/processors/ARM/gdb-7.10/include/floatformat.h branches/Cog/processors/ARM/gdb-7.10/include/fnmatch.h branches/Cog/processors/ARM/gdb-7.10/include/fopen-bin.h branches/Cog/processors/ARM/gdb-7.10/include/fopen-same.h branches/Cog/processors/ARM/gdb-7.10/include/fopen-vms.h branches/Cog/processors/ARM/gdb-7.10/include/gcc-c-fe.def branches/Cog/processors/ARM/gdb-7.10/include/gcc-c-interface.h branches/Cog/processors/ARM/gdb-7.10/include/gcc-interface.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/ branches/Cog/processors/ARM/gdb-7.10/include/gdb/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/gdb/callback.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/fileio.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/gdb-index.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/remote-sim.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/section-scripts.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/signals.def branches/Cog/processors/ARM/gdb-7.10/include/gdb/signals.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-arm.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-bfin.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-cr16.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-d10v.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-frv.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-ft32.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-h8300.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-lm32.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-m32c.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-ppc.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-rl78.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-rx.h branches/Cog/processors/ARM/gdb-7.10/include/gdb/sim-sh.h branches/Cog/processors/ARM/gdb-7.10/include/getopt.h branches/Cog/processors/ARM/gdb-7.10/include/hashtab.h branches/Cog/processors/ARM/gdb-7.10/include/hp-symtab.h branches/Cog/processors/ARM/gdb-7.10/include/ieee.h branches/Cog/processors/ARM/gdb-7.10/include/leb128.h branches/Cog/processors/ARM/gdb-7.10/include/libiberty.h branches/Cog/processors/ARM/gdb-7.10/include/longlong.h branches/Cog/processors/ARM/gdb-7.10/include/lto-symtab.h branches/Cog/processors/ARM/gdb-7.10/include/mach-o/ branches/Cog/processors/ARM/gdb-7.10/include/mach-o/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/mach-o/arm.h branches/Cog/processors/ARM/gdb-7.10/include/mach-o/codesign.h branches/Cog/processors/ARM/gdb-7.10/include/mach-o/external.h branches/Cog/processors/ARM/gdb-7.10/include/mach-o/loader.h branches/Cog/processors/ARM/gdb-7.10/include/mach-o/reloc.h branches/Cog/processors/ARM/gdb-7.10/include/mach-o/unwind.h branches/Cog/processors/ARM/gdb-7.10/include/mach-o/x86-64.h branches/Cog/processors/ARM/gdb-7.10/include/md5.h branches/Cog/processors/ARM/gdb-7.10/include/nlm/ branches/Cog/processors/ARM/gdb-7.10/include/nlm/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/nlm/alpha-ext.h branches/Cog/processors/ARM/gdb-7.10/include/nlm/common.h branches/Cog/processors/ARM/gdb-7.10/include/nlm/external.h branches/Cog/processors/ARM/gdb-7.10/include/nlm/i386-ext.h branches/Cog/processors/ARM/gdb-7.10/include/nlm/internal.h branches/Cog/processors/ARM/gdb-7.10/include/nlm/ppc-ext.h branches/Cog/processors/ARM/gdb-7.10/include/nlm/sparc32-ext.h branches/Cog/processors/ARM/gdb-7.10/include/oasys.h branches/Cog/processors/ARM/gdb-7.10/include/objalloc.h branches/Cog/processors/ARM/gdb-7.10/include/obstack.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/ branches/Cog/processors/ARM/gdb-7.10/include/opcode/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/opcode/ChangeLog-9103 branches/Cog/processors/ARM/gdb-7.10/include/opcode/aarch64.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/alpha.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/arc.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/arm.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/avr.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/bfin.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/cgen.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/convex.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/cr16.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/cris.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/crx.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/d10v.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/d30v.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/dlx.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/ft32.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/h8300.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/hppa.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/i370.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/i386.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/i860.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/i960.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/ia64.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/m68hc11.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/m68k.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/m88k.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/metag.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/mips.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/mmix.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/mn10200.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/mn10300.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/moxie.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/msp430-decode.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/msp430.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/nds32.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/nios2.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/nios2r1.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/nios2r2.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/np1.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/ns32k.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/pdp11.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/pj.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/pn.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/ppc.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/pyr.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/rl78.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/rx.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/s390.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/score-datadep.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/score-inst.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/sparc.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/spu-insns.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/spu.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tahoe.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tic30.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tic4x.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tic54x.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tic6x-control-registers.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tic6x-insn-formats.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tic6x-opcode-table.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tic6x.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tic80.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tilegx.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/tilepro.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/v850.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/vax.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/visium.h branches/Cog/processors/ARM/gdb-7.10/include/opcode/xgate.h branches/Cog/processors/ARM/gdb-7.10/include/os9k.h branches/Cog/processors/ARM/gdb-7.10/include/partition.h branches/Cog/processors/ARM/gdb-7.10/include/plugin-api.h branches/Cog/processors/ARM/gdb-7.10/include/progress.h branches/Cog/processors/ARM/gdb-7.10/include/safe-ctype.h branches/Cog/processors/ARM/gdb-7.10/include/sha1.h branches/Cog/processors/ARM/gdb-7.10/include/simple-object.h branches/Cog/processors/ARM/gdb-7.10/include/som/ branches/Cog/processors/ARM/gdb-7.10/include/som/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/som/aout.h branches/Cog/processors/ARM/gdb-7.10/include/som/clock.h branches/Cog/processors/ARM/gdb-7.10/include/som/internal.h branches/Cog/processors/ARM/gdb-7.10/include/som/lst.h branches/Cog/processors/ARM/gdb-7.10/include/som/reloc.h branches/Cog/processors/ARM/gdb-7.10/include/sort.h branches/Cog/processors/ARM/gdb-7.10/include/splay-tree.h branches/Cog/processors/ARM/gdb-7.10/include/symcat.h branches/Cog/processors/ARM/gdb-7.10/include/timeval-utils.h branches/Cog/processors/ARM/gdb-7.10/include/vms/ branches/Cog/processors/ARM/gdb-7.10/include/vms/ChangeLog branches/Cog/processors/ARM/gdb-7.10/include/vms/dcx.h branches/Cog/processors/ARM/gdb-7.10/include/vms/dmt.h branches/Cog/processors/ARM/gdb-7.10/include/vms/dsc.h branches/Cog/processors/ARM/gdb-7.10/include/vms/dst.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eeom.h branches/Cog/processors/ARM/gdb-7.10/include/vms/egps.h branches/Cog/processors/ARM/gdb-7.10/include/vms/egsd.h branches/Cog/processors/ARM/gdb-7.10/include/vms/egst.h branches/Cog/processors/ARM/gdb-7.10/include/vms/egsy.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eiaf.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eicp.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eidc.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eiha.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eihd.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eihi.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eihs.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eihvn.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eisd.h branches/Cog/processors/ARM/gdb-7.10/include/vms/emh.h branches/Cog/processors/ARM/gdb-7.10/include/vms/eobjrec.h branches/Cog/processors/ARM/gdb-7.10/include/vms/esdf.h branches/Cog/processors/ARM/gdb-7.10/include/vms/esdfm.h branches/Cog/processors/ARM/gdb-7.10/include/vms/esdfv.h branches/Cog/processors/ARM/gdb-7.10/include/vms/esgps.h branches/Cog/processors/ARM/gdb-7.10/include/vms/esrf.h branches/Cog/processors/ARM/gdb-7.10/include/vms/etir.h branches/Cog/processors/ARM/gdb-7.10/include/vms/internal.h branches/Cog/processors/ARM/gdb-7.10/include/vms/lbr.h branches/Cog/processors/ARM/gdb-7.10/include/vms/prt.h branches/Cog/processors/ARM/gdb-7.10/include/vms/shl.h branches/Cog/processors/ARM/gdb-7.10/include/vtv-change-permission.h branches/Cog/processors/ARM/gdb-7.10/include/xregex.h branches/Cog/processors/ARM/gdb-7.10/include/xregex2.h branches/Cog/processors/ARM/gdb-7.10/include/xtensa-config.h branches/Cog/processors/ARM/gdb-7.10/include/xtensa-isa-internal.h branches/Cog/processors/ARM/gdb-7.10/include/xtensa-isa.h branches/Cog/processors/ARM/gdb-7.10/install-sh branches/Cog/processors/ARM/gdb-7.10/libiberty/ branches/Cog/processors/ARM/gdb-7.10/libiberty/.gitignore branches/Cog/processors/ARM/gdb-7.10/libiberty/COPYING.LIB branches/Cog/processors/ARM/gdb-7.10/libiberty/ChangeLog branches/Cog/processors/ARM/gdb-7.10/libiberty/ChangeLog.jit branches/Cog/processors/ARM/gdb-7.10/libiberty/Makefile.in branches/Cog/processors/ARM/gdb-7.10/libiberty/README branches/Cog/processors/ARM/gdb-7.10/libiberty/_doprnt.c branches/Cog/processors/ARM/gdb-7.10/libiberty/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/libiberty/alloca.c branches/Cog/processors/ARM/gdb-7.10/libiberty/argv.c branches/Cog/processors/ARM/gdb-7.10/libiberty/asprintf.c branches/Cog/processors/ARM/gdb-7.10/libiberty/at-file.texi branches/Cog/processors/ARM/gdb-7.10/libiberty/atexit.c branches/Cog/processors/ARM/gdb-7.10/libiberty/basename.c branches/Cog/processors/ARM/gdb-7.10/libiberty/bcmp.c branches/Cog/processors/ARM/gdb-7.10/libiberty/bcopy.c branches/Cog/processors/ARM/gdb-7.10/libiberty/bsearch.c branches/Cog/processors/ARM/gdb-7.10/libiberty/bzero.c branches/Cog/processors/ARM/gdb-7.10/libiberty/calloc.c branches/Cog/processors/ARM/gdb-7.10/libiberty/choose-temp.c branches/Cog/processors/ARM/gdb-7.10/libiberty/clock.c branches/Cog/processors/ARM/gdb-7.10/libiberty/concat.c branches/Cog/processors/ARM/gdb-7.10/libiberty/config/ branches/Cog/processors/ARM/gdb-7.10/libiberty/config/mh-aix branches/Cog/processors/ARM/gdb-7.10/libiberty/config/mh-cxux7 branches/Cog/processors/ARM/gdb-7.10/libiberty/config/mh-fbsd21 branches/Cog/processors/ARM/gdb-7.10/libiberty/config/mh-openedition branches/Cog/processors/ARM/gdb-7.10/libiberty/config/mh-windows branches/Cog/processors/ARM/gdb-7.10/libiberty/config.h-vms branches/Cog/processors/ARM/gdb-7.10/libiberty/config.in branches/Cog/processors/ARM/gdb-7.10/libiberty/configure branches/Cog/processors/ARM/gdb-7.10/libiberty/configure.ac branches/Cog/processors/ARM/gdb-7.10/libiberty/configure.com branches/Cog/processors/ARM/gdb-7.10/libiberty/copying-lib.texi branches/Cog/processors/ARM/gdb-7.10/libiberty/copysign.c branches/Cog/processors/ARM/gdb-7.10/libiberty/cp-demangle.c branches/Cog/processors/ARM/gdb-7.10/libiberty/cp-demangle.h branches/Cog/processors/ARM/gdb-7.10/libiberty/cp-demint.c branches/Cog/processors/ARM/gdb-7.10/libiberty/cplus-dem.c branches/Cog/processors/ARM/gdb-7.10/libiberty/crc32.c branches/Cog/processors/ARM/gdb-7.10/libiberty/d-demangle.c branches/Cog/processors/ARM/gdb-7.10/libiberty/dwarfnames.c branches/Cog/processors/ARM/gdb-7.10/libiberty/dyn-string.c branches/Cog/processors/ARM/gdb-7.10/libiberty/fdmatch.c branches/Cog/processors/ARM/gdb-7.10/libiberty/ffs.c branches/Cog/processors/ARM/gdb-7.10/libiberty/fibheap.c branches/Cog/processors/ARM/gdb-7.10/libiberty/filename_cmp.c branches/Cog/processors/ARM/gdb-7.10/libiberty/floatformat.c branches/Cog/processors/ARM/gdb-7.10/libiberty/fnmatch.c branches/Cog/processors/ARM/gdb-7.10/libiberty/fnmatch.txh branches/Cog/processors/ARM/gdb-7.10/libiberty/fopen_unlocked.c branches/Cog/processors/ARM/gdb-7.10/libiberty/functions.texi branches/Cog/processors/ARM/gdb-7.10/libiberty/gather-docs branches/Cog/processors/ARM/gdb-7.10/libiberty/getcwd.c branches/Cog/processors/ARM/gdb-7.10/libiberty/getopt.c branches/Cog/processors/ARM/gdb-7.10/libiberty/getopt1.c branches/Cog/processors/ARM/gdb-7.10/libiberty/getpagesize.c branches/Cog/processors/ARM/gdb-7.10/libiberty/getpwd.c branches/Cog/processors/ARM/gdb-7.10/libiberty/getruntime.c branches/Cog/processors/ARM/gdb-7.10/libiberty/gettimeofday.c branches/Cog/processors/ARM/gdb-7.10/libiberty/hashtab.c branches/Cog/processors/ARM/gdb-7.10/libiberty/hex.c branches/Cog/processors/ARM/gdb-7.10/libiberty/index.c branches/Cog/processors/ARM/gdb-7.10/libiberty/insque.c branches/Cog/processors/ARM/gdb-7.10/libiberty/lbasename.c branches/Cog/processors/ARM/gdb-7.10/libiberty/libiberty.texi branches/Cog/processors/ARM/gdb-7.10/libiberty/lrealpath.c branches/Cog/processors/ARM/gdb-7.10/libiberty/maint-tool branches/Cog/processors/ARM/gdb-7.10/libiberty/make-relative-prefix.c branches/Cog/processors/ARM/gdb-7.10/libiberty/make-temp-file.c branches/Cog/processors/ARM/gdb-7.10/libiberty/makefile.vms branches/Cog/processors/ARM/gdb-7.10/libiberty/md5.c branches/Cog/processors/ARM/gdb-7.10/libiberty/memchr.c branches/Cog/processors/ARM/gdb-7.10/libiberty/memcmp.c branches/Cog/processors/ARM/gdb-7.10/libiberty/memcpy.c branches/Cog/processors/ARM/gdb-7.10/libiberty/memmem.c branches/Cog/processors/ARM/gdb-7.10/libiberty/memmove.c branches/Cog/processors/ARM/gdb-7.10/libiberty/mempcpy.c branches/Cog/processors/ARM/gdb-7.10/libiberty/memset.c branches/Cog/processors/ARM/gdb-7.10/libiberty/mkstemps.c branches/Cog/processors/ARM/gdb-7.10/libiberty/msdos.c branches/Cog/processors/ARM/gdb-7.10/libiberty/objalloc.c branches/Cog/processors/ARM/gdb-7.10/libiberty/obstack.c branches/Cog/processors/ARM/gdb-7.10/libiberty/obstacks.texi branches/Cog/processors/ARM/gdb-7.10/libiberty/partition.c branches/Cog/processors/ARM/gdb-7.10/libiberty/pex-common.c branches/Cog/processors/ARM/gdb-7.10/libiberty/pex-common.h branches/Cog/processors/ARM/gdb-7.10/libiberty/pex-djgpp.c branches/Cog/processors/ARM/gdb-7.10/libiberty/pex-msdos.c branches/Cog/processors/ARM/gdb-7.10/libiberty/pex-one.c branches/Cog/processors/ARM/gdb-7.10/libiberty/pex-unix.c branches/Cog/processors/ARM/gdb-7.10/libiberty/pex-win32.c branches/Cog/processors/ARM/gdb-7.10/libiberty/pexecute.c branches/Cog/processors/ARM/gdb-7.10/libiberty/pexecute.txh branches/Cog/processors/ARM/gdb-7.10/libiberty/physmem.c branches/Cog/processors/ARM/gdb-7.10/libiberty/putenv.c branches/Cog/processors/ARM/gdb-7.10/libiberty/random.c branches/Cog/processors/ARM/gdb-7.10/libiberty/regex.c branches/Cog/processors/ARM/gdb-7.10/libiberty/rename.c branches/Cog/processors/ARM/gdb-7.10/libiberty/rindex.c branches/Cog/processors/ARM/gdb-7.10/libiberty/safe-ctype.c branches/Cog/processors/ARM/gdb-7.10/libiberty/setenv.c branches/Cog/processors/ARM/gdb-7.10/libiberty/setproctitle.c branches/Cog/processors/ARM/gdb-7.10/libiberty/sha1.c branches/Cog/processors/ARM/gdb-7.10/libiberty/sigsetmask.c branches/Cog/processors/ARM/gdb-7.10/libiberty/simple-object-coff.c branches/Cog/processors/ARM/gdb-7.10/libiberty/simple-object-common.h branches/Cog/processors/ARM/gdb-7.10/libiberty/simple-object-elf.c branches/Cog/processors/ARM/gdb-7.10/libiberty/simple-object-mach-o.c branches/Cog/processors/ARM/gdb-7.10/libiberty/simple-object-xcoff.c branches/Cog/processors/ARM/gdb-7.10/libiberty/simple-object.c branches/Cog/processors/ARM/gdb-7.10/libiberty/simple-object.txh branches/Cog/processors/ARM/gdb-7.10/libiberty/snprintf.c branches/Cog/processors/ARM/gdb-7.10/libiberty/sort.c branches/Cog/processors/ARM/gdb-7.10/libiberty/spaces.c branches/Cog/processors/ARM/gdb-7.10/libiberty/splay-tree.c branches/Cog/processors/ARM/gdb-7.10/libiberty/stack-limit.c branches/Cog/processors/ARM/gdb-7.10/libiberty/stpcpy.c branches/Cog/processors/ARM/gdb-7.10/libiberty/stpncpy.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strcasecmp.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strchr.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strdup.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strerror.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strncasecmp.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strncmp.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strndup.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strnlen.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strrchr.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strsignal.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strstr.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strtod.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strtol.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strtoll.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strtoul.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strtoull.c branches/Cog/processors/ARM/gdb-7.10/libiberty/strverscmp.c branches/Cog/processors/ARM/gdb-7.10/libiberty/testsuite/ branches/Cog/processors/ARM/gdb-7.10/libiberty/testsuite/Makefile.in branches/Cog/processors/ARM/gdb-7.10/libiberty/testsuite/d-demangle-expected branches/Cog/processors/ARM/gdb-7.10/libiberty/testsuite/demangle-expected branches/Cog/processors/ARM/gdb-7.10/libiberty/testsuite/demangler-fuzzer.c branches/Cog/processors/ARM/gdb-7.10/libiberty/testsuite/test-demangle.c branches/Cog/processors/ARM/gdb-7.10/libiberty/testsuite/test-expandargv.c branches/Cog/processors/ARM/gdb-7.10/libiberty/testsuite/test-pexecute.c branches/Cog/processors/ARM/gdb-7.10/libiberty/testsuite/test-strtol.c branches/Cog/processors/ARM/gdb-7.10/libiberty/timeval-utils.c branches/Cog/processors/ARM/gdb-7.10/libiberty/tmpnam.c branches/Cog/processors/ARM/gdb-7.10/libiberty/unlink-if-ordinary.c branches/Cog/processors/ARM/gdb-7.10/libiberty/vasprintf.c branches/Cog/processors/ARM/gdb-7.10/libiberty/vfork.c branches/Cog/processors/ARM/gdb-7.10/libiberty/vfprintf.c branches/Cog/processors/ARM/gdb-7.10/libiberty/vprintf-support.c branches/Cog/processors/ARM/gdb-7.10/libiberty/vprintf-support.h branches/Cog/processors/ARM/gdb-7.10/libiberty/vprintf.c branches/Cog/processors/ARM/gdb-7.10/libiberty/vsnprintf.c branches/Cog/processors/ARM/gdb-7.10/libiberty/vsprintf.c branches/Cog/processors/ARM/gdb-7.10/libiberty/waitpid.c branches/Cog/processors/ARM/gdb-7.10/libiberty/xasprintf.c branches/Cog/processors/ARM/gdb-7.10/libiberty/xatexit.c branches/Cog/processors/ARM/gdb-7.10/libiberty/xexit.c branches/Cog/processors/ARM/gdb-7.10/libiberty/xmalloc.c branches/Cog/processors/ARM/gdb-7.10/libiberty/xmemdup.c branches/Cog/processors/ARM/gdb-7.10/libiberty/xstrdup.c branches/Cog/processors/ARM/gdb-7.10/libiberty/xstrerror.c branches/Cog/processors/ARM/gdb-7.10/libiberty/xstrndup.c branches/Cog/processors/ARM/gdb-7.10/libiberty/xvasprintf.c branches/Cog/processors/ARM/gdb-7.10/ltmain.sh branches/Cog/processors/ARM/gdb-7.10/md5.sum branches/Cog/processors/ARM/gdb-7.10/missing branches/Cog/processors/ARM/gdb-7.10/mkdep branches/Cog/processors/ARM/gdb-7.10/mkinstalldirs branches/Cog/processors/ARM/gdb-7.10/move-if-change branches/Cog/processors/ARM/gdb-7.10/opcodes/ branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/aarch64-asm-2.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/aarch64-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/aarch64-dis-2.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/aarch64-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/aarch64-opc-2.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/aarch64-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/alpha-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/alpha-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/arc-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/arc-ext.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/arc-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/arm-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/avr-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/bfin-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/cgen-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/cgen-bitset.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/cgen-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/cgen-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/cr16-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/cr16-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/cris-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/cris-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/crx-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/crx-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/d10v-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/d10v-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/d30v-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/d30v-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/dis-buf.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/dis-init.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/disassemble.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/dlx-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/epiphany-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/epiphany-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/epiphany-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/epiphany-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/epiphany-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/fr30-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/fr30-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/fr30-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/fr30-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/fr30-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/frv-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/frv-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/frv-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/frv-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/frv-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ft32-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ft32-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/h8300-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/h8500-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/hppa-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/i370-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/i370-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/i386-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/i386-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/i860-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/i960-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ia64-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ia64-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ip2k-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ip2k-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ip2k-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ip2k-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ip2k-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/iq2000-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/iq2000-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/iq2000-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/iq2000-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/iq2000-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/lm32-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/lm32-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/lm32-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/lm32-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/lm32-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/lm32-opinst.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m10200-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m10200-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m10300-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m10300-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32c-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32c-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32c-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32c-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32c-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32r-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32r-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32r-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32r-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32r-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m32r-opinst.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m68hc11-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m68hc11-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m68k-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m68k-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/m88k-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mcore-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mep-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mep-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mep-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mep-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mep-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/metag-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/microblaze-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/micromips-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mips-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mips-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mips16-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mmix-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mmix-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/moxie-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/moxie-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/msp430-decode.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/msp430-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mt-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mt-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mt-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mt-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/mt-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/nds32-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/nds32-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/nios2-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/nios2-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ns32k-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/or1k-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/or1k-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/or1k-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/or1k-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/or1k-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/pdp11-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/pdp11-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/pj-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/pj-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ppc-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/ppc-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/rl78-decode.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/rl78-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/rx-decode.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/rx-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/s390-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/s390-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/score-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/score7-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/sh-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/sh64-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/sh64-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/sparc-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/sparc-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/spu-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/spu-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tic30-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tic4x-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tic54x-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tic54x-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tic6x-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tic80-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tic80-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tilegx-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tilegx-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tilepro-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/tilepro-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/v850-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/v850-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/vax-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/visium-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/visium-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/w65-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xc16x-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xc16x-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xc16x-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xc16x-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xc16x-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xgate-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xgate-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xstormy16-asm.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xstormy16-desc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xstormy16-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xstormy16-ibld.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xstormy16-opc.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/xtensa-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/z80-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.deps/z8k-dis.Plo branches/Cog/processors/ARM/gdb-7.10/opcodes/.gitignore branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-0001 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-0203 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2004 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2005 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2006 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2007 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2008 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2009 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2010 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2011 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2012 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2013 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-2014 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-9297 branches/Cog/processors/ARM/gdb-7.10/opcodes/ChangeLog-9899 branches/Cog/processors/ARM/gdb-7.10/opcodes/MAINTAINERS branches/Cog/processors/ARM/gdb-7.10/opcodes/Makefile branches/Cog/processors/ARM/gdb-7.10/opcodes/Makefile.am branches/Cog/processors/ARM/gdb-7.10/opcodes/Makefile.in branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-asm-2.c branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-asm.h branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-dis-2.c branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-dis.h branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-gen.c branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-opc-2.c branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/aarch64-tbl.h branches/Cog/processors/ARM/gdb-7.10/opcodes/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/opcodes/alpha-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/alpha-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/arc-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/arc-dis.h branches/Cog/processors/ARM/gdb-7.10/opcodes/arc-ext.c branches/Cog/processors/ARM/gdb-7.10/opcodes/arc-ext.h branches/Cog/processors/ARM/gdb-7.10/opcodes/arc-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/arm-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/avr-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/bfin-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/cgen-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/cgen-asm.in branches/Cog/processors/ARM/gdb-7.10/opcodes/cgen-bitset.c branches/Cog/processors/ARM/gdb-7.10/opcodes/cgen-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/cgen-dis.in branches/Cog/processors/ARM/gdb-7.10/opcodes/cgen-ibld.in branches/Cog/processors/ARM/gdb-7.10/opcodes/cgen-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/cgen.sh branches/Cog/processors/ARM/gdb-7.10/opcodes/config.h branches/Cog/processors/ARM/gdb-7.10/opcodes/config.in branches/Cog/processors/ARM/gdb-7.10/opcodes/config.log branches/Cog/processors/ARM/gdb-7.10/opcodes/config.status branches/Cog/processors/ARM/gdb-7.10/opcodes/configure branches/Cog/processors/ARM/gdb-7.10/opcodes/configure.ac branches/Cog/processors/ARM/gdb-7.10/opcodes/configure.com branches/Cog/processors/ARM/gdb-7.10/opcodes/cr16-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/cr16-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/cris-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/cris-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/crx-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/crx-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/d10v-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/d10v-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/d30v-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/d30v-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/dep-in.sed branches/Cog/processors/ARM/gdb-7.10/opcodes/dis-buf.c branches/Cog/processors/ARM/gdb-7.10/opcodes/dis-init.c branches/Cog/processors/ARM/gdb-7.10/opcodes/disassemble.c branches/Cog/processors/ARM/gdb-7.10/opcodes/dlx-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/epiphany-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/epiphany-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/epiphany-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/epiphany-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/epiphany-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/epiphany-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/epiphany-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/fr30-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/fr30-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/fr30-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/fr30-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/fr30-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/fr30-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/fr30-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/frv-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/frv-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/frv-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/frv-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/frv-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/frv-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/frv-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/ft32-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ft32-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/h8300-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/h8500-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/h8500-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/hppa-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/i370-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/i370-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/i386-dis-evex.h branches/Cog/processors/ARM/gdb-7.10/opcodes/i386-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/i386-gen.c branches/Cog/processors/ARM/gdb-7.10/opcodes/i386-init.h branches/Cog/processors/ARM/gdb-7.10/opcodes/i386-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/i386-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/i386-opc.tbl branches/Cog/processors/ARM/gdb-7.10/opcodes/i386-reg.tbl branches/Cog/processors/ARM/gdb-7.10/opcodes/i386-tbl.h branches/Cog/processors/ARM/gdb-7.10/opcodes/i860-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/i960-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-asmtab.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-asmtab.h branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-gen.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-ic.tbl branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-opc-a.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-opc-b.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-opc-d.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-opc-f.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-opc-i.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-opc-m.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-opc-x.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-raw.tbl branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-war.tbl branches/Cog/processors/ARM/gdb-7.10/opcodes/ia64-waw.tbl branches/Cog/processors/ARM/gdb-7.10/opcodes/ip2k-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ip2k-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ip2k-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/ip2k-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ip2k-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ip2k-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ip2k-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/iq2000-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/iq2000-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/iq2000-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/iq2000-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/iq2000-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/iq2000-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/iq2000-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/libtool branches/Cog/processors/ARM/gdb-7.10/opcodes/lm32-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/lm32-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/lm32-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/lm32-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/lm32-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/lm32-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/lm32-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/lm32-opinst.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m10200-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m10200-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m10300-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m10300-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32c-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32c-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32c-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/m32c-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32c-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32c-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32c-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/m32r-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32r-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32r-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/m32r-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32r-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32r-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m32r-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/m32r-opinst.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m68hc11-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m68hc11-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m68k-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m68k-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/m88k-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/makefile.vms branches/Cog/processors/ARM/gdb-7.10/opcodes/mcore-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mcore-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/mep-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mep-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mep-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/mep-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mep-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mep-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mep-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/metag-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/microblaze-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/microblaze-dis.h branches/Cog/processors/ARM/gdb-7.10/opcodes/microblaze-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/microblaze-opcm.h branches/Cog/processors/ARM/gdb-7.10/opcodes/micromips-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mips-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mips-formats.h branches/Cog/processors/ARM/gdb-7.10/opcodes/mips-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mips16-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mmix-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mmix-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/moxie-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/moxie-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/msp430-decode.c branches/Cog/processors/ARM/gdb-7.10/opcodes/msp430-decode.opc branches/Cog/processors/ARM/gdb-7.10/opcodes/msp430-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mt-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mt-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mt-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/mt-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mt-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mt-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/mt-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/nds32-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/nds32-asm.h branches/Cog/processors/ARM/gdb-7.10/opcodes/nds32-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/nds32-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/nios2-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/nios2-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ns32k-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/opc2c.c branches/Cog/processors/ARM/gdb-7.10/opcodes/opintl.h branches/Cog/processors/ARM/gdb-7.10/opcodes/or1k-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/or1k-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/or1k-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/or1k-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/or1k-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/or1k-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/or1k-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/or1k-opinst.c branches/Cog/processors/ARM/gdb-7.10/opcodes/pdp11-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/pdp11-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/pj-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/pj-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/po/ branches/Cog/processors/ARM/gdb-7.10/opcodes/po/Make-in branches/Cog/processors/ARM/gdb-7.10/opcodes/po/Makefile branches/Cog/processors/ARM/gdb-7.10/opcodes/po/Makefile.in branches/Cog/processors/ARM/gdb-7.10/opcodes/po/POTFILES branches/Cog/processors/ARM/gdb-7.10/opcodes/po/POTFILES.in branches/Cog/processors/ARM/gdb-7.10/opcodes/po/da.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/da.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/de.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/de.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/es.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/es.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/fi.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/fi.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/fr.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/fr.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/ga.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/ga.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/id.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/id.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/it.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/it.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/nl.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/nl.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/opcodes.pot branches/Cog/processors/ARM/gdb-7.10/opcodes/po/pt_BR.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/pt_BR.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/ro.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/ro.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/sv.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/sv.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/tr.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/tr.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/uk.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/uk.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/vi.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/vi.po branches/Cog/processors/ARM/gdb-7.10/opcodes/po/zh_CN.gmo branches/Cog/processors/ARM/gdb-7.10/opcodes/po/zh_CN.po branches/Cog/processors/ARM/gdb-7.10/opcodes/ppc-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/ppc-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/rl78-decode.c branches/Cog/processors/ARM/gdb-7.10/opcodes/rl78-decode.opc branches/Cog/processors/ARM/gdb-7.10/opcodes/rl78-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/rx-decode.c branches/Cog/processors/ARM/gdb-7.10/opcodes/rx-decode.opc branches/Cog/processors/ARM/gdb-7.10/opcodes/rx-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/s390-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/s390-mkopc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/s390-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/s390-opc.txt branches/Cog/processors/ARM/gdb-7.10/opcodes/score-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/score-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/score7-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/sh-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/sh-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/sh64-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/sh64-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/sh64-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/sparc-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/sparc-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/spu-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/spu-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/stamp-h.in branches/Cog/processors/ARM/gdb-7.10/opcodes/stamp-h1 branches/Cog/processors/ARM/gdb-7.10/opcodes/stamp-lib branches/Cog/processors/ARM/gdb-7.10/opcodes/sysdep.h branches/Cog/processors/ARM/gdb-7.10/opcodes/tic30-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tic4x-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tic54x-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tic54x-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tic6x-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tic80-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tic80-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tilegx-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tilegx-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tilepro-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/tilepro-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/v850-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/v850-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/vax-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/visium-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/visium-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/w65-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/w65-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/xc16x-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xc16x-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xc16x-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/xc16x-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xc16x-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xc16x-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xc16x-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/xgate-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xgate-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xstormy16-asm.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xstormy16-desc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xstormy16-desc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/xstormy16-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xstormy16-ibld.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xstormy16-opc.c branches/Cog/processors/ARM/gdb-7.10/opcodes/xstormy16-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/xtensa-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/z80-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/z8k-dis.c branches/Cog/processors/ARM/gdb-7.10/opcodes/z8k-opc.h branches/Cog/processors/ARM/gdb-7.10/opcodes/z8kgen.c branches/Cog/processors/ARM/gdb-7.10/sim/ branches/Cog/processors/ARM/gdb-7.10/sim/.gitignore branches/Cog/processors/ARM/gdb-7.10/sim/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/MAINTAINERS branches/Cog/processors/ARM/gdb-7.10/sim/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/README-HACKING branches/Cog/processors/ARM/gdb-7.10/sim/arm/ branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/ branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/armcopro.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/arminit.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/armos.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/armsupp.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/armulmem.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/armvirt.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/bag.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/callback.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/iwmmxt.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/maverick.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/nrun.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-arange.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-bits.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-command.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-config.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-core.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-cpu.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-endian.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-engine.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-events.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-fpu.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-hload.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-hrw.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-info.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-io.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-load.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-memopt.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-module.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-options.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-profile.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-signal.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-syscall.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-trace.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-utils.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/sim-watch.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/syscall.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/targ-map.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/thumbemu.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/version.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/.deps/wrapper.Po branches/Cog/processors/ARM/gdb-7.10/sim/arm/COPYING branches/Cog/processors/ARM/gdb-7.10/sim/arm/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/arm/GdbARMPlugin.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/arm/README branches/Cog/processors/ARM/gdb-7.10/sim/arm/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/arm/armcopro.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/armdefs.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/armemu.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/armemu.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/armfpe.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/arminit.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/armopts.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/armos.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/armos.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/armrdi.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/armsupp.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/armulmem.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/armvirt.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/bag.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/bag.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/communicate.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/communicate.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/config.in branches/Cog/processors/ARM/gdb-7.10/sim/arm/configure branches/Cog/processors/ARM/gdb-7.10/sim/arm/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/arm/dbg_conf.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/dbg_cp.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/dbg_hif.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/dbg_rdi.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/gdbhost.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/gdbhost.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/hw-config.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/iwmmxt.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/iwmmxt.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/kid.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/libtool branches/Cog/processors/ARM/gdb-7.10/sim/arm/main.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/maverick.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/parent.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/arm/thumbemu.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/version.c branches/Cog/processors/ARM/gdb-7.10/sim/arm/wrapper.c branches/Cog/processors/ARM/gdb-7.10/sim/avr/ branches/Cog/processors/ARM/gdb-7.10/sim/avr/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/avr/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/avr/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/avr/config.in branches/Cog/processors/ARM/gdb-7.10/sim/avr/configure branches/Cog/processors/ARM/gdb-7.10/sim/avr/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/avr/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/avr/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/ branches/Cog/processors/ARM/gdb-7.10/sim/bfin/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/bfin/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/bfin/TODO branches/Cog/processors/ARM/gdb-7.10/sim/bfin/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfin-sim.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfin-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/ branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/all.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf50x-0.0.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf51x-0.0.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf51x-0.1.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf51x-0.2.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf526-0.0.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf526-0.1.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf526-0.2.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf527-0.0.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf527-0.1.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf527-0.2.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf533-0.1.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf533-0.2.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf533-0.3.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf537-0.0.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf537-0.1.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf537-0.3.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf538-0.0.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf54x-0.0.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf54x-0.1.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf54x-0.2.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf54x-0.4.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf54x_l1-0.0.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf54x_l1-0.1.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf54x_l1-0.2.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf54x_l1-0.4.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf561-0.5.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf59x-0.0.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/bfroms/bf59x_l1-0.1.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/config.in branches/Cog/processors/ARM/gdb-7.10/sim/bfin/configure branches/Cog/processors/ARM/gdb-7.10/sim/bfin/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/bfin/devices.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/devices.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_cec.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_cec.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ctimer.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ctimer.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_dma.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_dma.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_dmac.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_dmac.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ebiu_amc.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ebiu_amc.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ebiu_ddrc.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ebiu_ddrc.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ebiu_sdc.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ebiu_sdc.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_emac.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_emac.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_eppi.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_eppi.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_evt.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_evt.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_gpio.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_gpio.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_gpio2.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_gpio2.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_gptimer.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_gptimer.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_jtag.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_jtag.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_mmu.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_mmu.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_nfc.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_nfc.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_otp.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_otp.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_pfmon.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_pfmon.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_pint.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_pint.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_pll.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_pll.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ppi.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_ppi.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_rtc.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_rtc.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_sic.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_sic.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_spi.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_spi.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_trace.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_trace.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_twi.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_twi.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_uart.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_uart.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_uart2.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_uart2.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_wdog.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_wdog.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_wp.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-bfin_wp.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/dv-eth_phy.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/gui.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/gui.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/insn_list.def branches/Cog/processors/ARM/gdb-7.10/sim/bfin/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/linux-fixed-code.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/linux-fixed-code.s branches/Cog/processors/ARM/gdb-7.10/sim/bfin/linux-targ-map.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/machs.c branches/Cog/processors/ARM/gdb-7.10/sim/bfin/machs.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/proc_list.def branches/Cog/processors/ARM/gdb-7.10/sim/bfin/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/bfin/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/common/ branches/Cog/processors/ARM/gdb-7.10/sim/common/.deps/ branches/Cog/processors/ARM/gdb-7.10/sim/common/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/common/Make-common.in branches/Cog/processors/ARM/gdb-7.10/sim/common/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/common/acinclude.m4 branches/Cog/processors/ARM/gdb-7.10/sim/common/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/common/callback.c branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-accfp.c branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-defs.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-engine.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-fpu.c branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-fpu.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-mem.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-ops.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-par.c branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-par.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-run.c branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-scache.c branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-scache.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-trace.c branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-trace.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-types.h branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen-utils.c branches/Cog/processors/ARM/gdb-7.10/sim/common/cgen.sh branches/Cog/processors/ARM/gdb-7.10/sim/common/config.in branches/Cog/processors/ARM/gdb-7.10/sim/common/configure branches/Cog/processors/ARM/gdb-7.10/sim/common/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/common/dv-cfi.c branches/Cog/processors/ARM/gdb-7.10/sim/common/dv-cfi.h branches/Cog/processors/ARM/gdb-7.10/sim/common/dv-core.c branches/Cog/processors/ARM/gdb-7.10/sim/common/dv-glue.c branches/Cog/processors/ARM/gdb-7.10/sim/common/dv-pal.c branches/Cog/processors/ARM/gdb-7.10/sim/common/dv-sockser.c branches/Cog/processors/ARM/gdb-7.10/sim/common/dv-sockser.h branches/Cog/processors/ARM/gdb-7.10/sim/common/gdbinit.in branches/Cog/processors/ARM/gdb-7.10/sim/common/genmloop.sh branches/Cog/processors/ARM/gdb-7.10/sim/common/gennltvals.sh branches/Cog/processors/ARM/gdb-7.10/sim/common/gentmap.c branches/Cog/processors/ARM/gdb-7.10/sim/common/gentvals.sh branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-alloc.c branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-alloc.h branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-base.c branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-base.h branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-device.c branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-device.h branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-events.c branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-events.h branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-handles.c branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-handles.h branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-instances.c branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-instances.h branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-main.h branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-ports.c branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-ports.h branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-properties.c branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-properties.h branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-tree.c branches/Cog/processors/ARM/gdb-7.10/sim/common/hw-tree.h branches/Cog/processors/ARM/gdb-7.10/sim/common/libtool branches/Cog/processors/ARM/gdb-7.10/sim/common/nltvals.def branches/Cog/processors/ARM/gdb-7.10/sim/common/nrun.c branches/Cog/processors/ARM/gdb-7.10/sim/common/run.1 branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-abort.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-alu.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-arange.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-arange.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-assert.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-base.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-basics.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-bits.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-bits.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-command.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-config.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-config.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-core.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-core.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-endian.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-endian.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-engine.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-engine.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-events.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-events.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-fpu.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-fpu.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-hload.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-hrw.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-hw.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-hw.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-info.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-inline.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-inline.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-io.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-io.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-load.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-memopt.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-memopt.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-model.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-model.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-module.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-module.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-n-bits.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-n-core.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-n-endian.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-options.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-options.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-profile.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-profile.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-reason.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-reg.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-resume.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-run.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-signal.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-signal.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-stop.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-syscall.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-syscall.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-trace.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-trace.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-types.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-utils.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-utils.h branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-watch.c branches/Cog/processors/ARM/gdb-7.10/sim/common/sim-watch.h branches/Cog/processors/ARM/gdb-7.10/sim/common/syscall.c branches/Cog/processors/ARM/gdb-7.10/sim/common/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/common/version.h branches/Cog/processors/ARM/gdb-7.10/sim/configure branches/Cog/processors/ARM/gdb-7.10/sim/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/configure.tgt branches/Cog/processors/ARM/gdb-7.10/sim/cr16/ branches/Cog/processors/ARM/gdb-7.10/sim/cr16/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/cr16/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/cr16/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/cr16/config.in branches/Cog/processors/ARM/gdb-7.10/sim/cr16/configure branches/Cog/processors/ARM/gdb-7.10/sim/cr16/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/cr16/cr16_sim.h branches/Cog/processors/ARM/gdb-7.10/sim/cr16/endian.c branches/Cog/processors/ARM/gdb-7.10/sim/cr16/gencode.c branches/Cog/processors/ARM/gdb-7.10/sim/cr16/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/cr16/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/cr16/simops.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/ branches/Cog/processors/ARM/gdb-7.10/sim/cris/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/cris/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/cris/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/cris/arch.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/arch.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/config.in branches/Cog/processors/ARM/gdb-7.10/sim/cris/configure branches/Cog/processors/ARM/gdb-7.10/sim/cris/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/cris/cpuall.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/cpuv10.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/cpuv10.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/cpuv32.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/cpuv32.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/cris-desc.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/cris-desc.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/cris-opc.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/cris-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/cris-tmpl.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/crisv10f.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/crisv32f.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/decodev10.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/decodev10.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/decodev32.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/decodev32.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/devices.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/dv-cris.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/dv-rv.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/mloop.in branches/Cog/processors/ARM/gdb-7.10/sim/cris/modelv10.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/modelv32.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/rvdummy.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/semcrisv10f-switch.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/semcrisv32f-switch.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/sim-if.c branches/Cog/processors/ARM/gdb-7.10/sim/cris/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/cris/traps.c branches/Cog/processors/ARM/gdb-7.10/sim/d10v/ branches/Cog/processors/ARM/gdb-7.10/sim/d10v/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/d10v/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/d10v/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/d10v/config.in branches/Cog/processors/ARM/gdb-7.10/sim/d10v/configure branches/Cog/processors/ARM/gdb-7.10/sim/d10v/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/d10v/d10v_sim.h branches/Cog/processors/ARM/gdb-7.10/sim/d10v/endian.c branches/Cog/processors/ARM/gdb-7.10/sim/d10v/gencode.c branches/Cog/processors/ARM/gdb-7.10/sim/d10v/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/d10v/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/d10v/simops.c branches/Cog/processors/ARM/gdb-7.10/sim/erc32/ branches/Cog/processors/ARM/gdb-7.10/sim/erc32/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/erc32/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/erc32/NEWS branches/Cog/processors/ARM/gdb-7.10/sim/erc32/README.erc32 branches/Cog/processors/ARM/gdb-7.10/sim/erc32/README.gdb branches/Cog/processors/ARM/gdb-7.10/sim/erc32/README.sis branches/Cog/processors/ARM/gdb-7.10/sim/erc32/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/erc32/config.in branches/Cog/processors/ARM/gdb-7.10/sim/erc32/configure branches/Cog/processors/ARM/gdb-7.10/sim/erc32/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/erc32/erc32.c branches/Cog/processors/ARM/gdb-7.10/sim/erc32/exec.c branches/Cog/processors/ARM/gdb-7.10/sim/erc32/float.c branches/Cog/processors/ARM/gdb-7.10/sim/erc32/func.c branches/Cog/processors/ARM/gdb-7.10/sim/erc32/help.c branches/Cog/processors/ARM/gdb-7.10/sim/erc32/interf.c branches/Cog/processors/ARM/gdb-7.10/sim/erc32/sis.c branches/Cog/processors/ARM/gdb-7.10/sim/erc32/sis.h branches/Cog/processors/ARM/gdb-7.10/sim/erc32/startsim branches/Cog/processors/ARM/gdb-7.10/sim/frv/ branches/Cog/processors/ARM/gdb-7.10/sim/frv/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/frv/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/frv/README branches/Cog/processors/ARM/gdb-7.10/sim/frv/TODO branches/Cog/processors/ARM/gdb-7.10/sim/frv/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/frv/arch.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/arch.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/cache.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/cache.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/config.in branches/Cog/processors/ARM/gdb-7.10/sim/frv/configure branches/Cog/processors/ARM/gdb-7.10/sim/frv/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/frv/cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/cpuall.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/decode.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/decode.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/devices.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/frv-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/frv.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/interrupts.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/memory.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/mloop.in branches/Cog/processors/ARM/gdb-7.10/sim/frv/model.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/options.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/pipeline.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/profile-fr400.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/profile-fr400.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/profile-fr450.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/profile-fr500.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/profile-fr500.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/profile-fr550.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/profile-fr550.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/profile.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/profile.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/registers.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/registers.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/reset.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/sem.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/sim-if.c branches/Cog/processors/ARM/gdb-7.10/sim/frv/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/frv/traps.c branches/Cog/processors/ARM/gdb-7.10/sim/ft32/ branches/Cog/processors/ARM/gdb-7.10/sim/ft32/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/ft32/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/ft32/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/ft32/config.in branches/Cog/processors/ARM/gdb-7.10/sim/ft32/configure branches/Cog/processors/ARM/gdb-7.10/sim/ft32/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/ft32/ft32-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/ft32/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/ft32/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/h8300/ branches/Cog/processors/ARM/gdb-7.10/sim/h8300/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/h8300/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/h8300/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/h8300/compile.c branches/Cog/processors/ARM/gdb-7.10/sim/h8300/config.in branches/Cog/processors/ARM/gdb-7.10/sim/h8300/configure branches/Cog/processors/ARM/gdb-7.10/sim/h8300/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/h8300/inst.h branches/Cog/processors/ARM/gdb-7.10/sim/h8300/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/h8300/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/h8300/writecode.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/ branches/Cog/processors/ARM/gdb-7.10/sim/igen/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/igen/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/igen/compare_igen_models branches/Cog/processors/ARM/gdb-7.10/sim/igen/config.in branches/Cog/processors/ARM/gdb-7.10/sim/igen/configure branches/Cog/processors/ARM/gdb-7.10/sim/igen/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/igen/filter.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/filter.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/filter_host.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/filter_host.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-engine.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-engine.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-icache.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-icache.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-idecode.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-idecode.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-itable.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-itable.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-model.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-model.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-semantics.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-semantics.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-support.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen-support.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/gen.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/igen.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/igen.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/ld-cache.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/ld-cache.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/ld-decode.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/ld-decode.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/ld-insn.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/ld-insn.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/lf.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/lf.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/misc.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/misc.h branches/Cog/processors/ARM/gdb-7.10/sim/igen/table.c branches/Cog/processors/ARM/gdb-7.10/sim/igen/table.h branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/ branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/arch.c branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/arch.h branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/config.in branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/configure branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/cpuall.h branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/decode.c branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/decode.h branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/iq2000-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/iq2000.c branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/mloop.in branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/model.c branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/sem-switch.c branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/sem.c branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/sim-if.c branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/iq2000/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/lm32/ branches/Cog/processors/ARM/gdb-7.10/sim/lm32/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/lm32/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/lm32/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/lm32/arch.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/arch.h branches/Cog/processors/ARM/gdb-7.10/sim/lm32/config.in branches/Cog/processors/ARM/gdb-7.10/sim/lm32/configure branches/Cog/processors/ARM/gdb-7.10/sim/lm32/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/lm32/cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/lm32/cpuall.h branches/Cog/processors/ARM/gdb-7.10/sim/lm32/decode.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/decode.h branches/Cog/processors/ARM/gdb-7.10/sim/lm32/dv-lm32cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/dv-lm32timer.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/dv-lm32uart.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/lm32-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/lm32/lm32.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/mloop.in branches/Cog/processors/ARM/gdb-7.10/sim/lm32/model.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/sem-switch.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/sem.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/sim-if.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/lm32/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/lm32/traps.c branches/Cog/processors/ARM/gdb-7.10/sim/lm32/user.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/ branches/Cog/processors/ARM/gdb-7.10/sim/m32c/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/m32c/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/m32c/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/m32c/blinky.S branches/Cog/processors/ARM/gdb-7.10/sim/m32c/config.in branches/Cog/processors/ARM/gdb-7.10/sim/m32c/configure branches/Cog/processors/ARM/gdb-7.10/sim/m32c/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/m32c/cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/m32c/gdb-if.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/gloss.S branches/Cog/processors/ARM/gdb-7.10/sim/m32c/int.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/int.h branches/Cog/processors/ARM/gdb-7.10/sim/m32c/load.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/load.h branches/Cog/processors/ARM/gdb-7.10/sim/m32c/m32c.opc branches/Cog/processors/ARM/gdb-7.10/sim/m32c/main.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/mem.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/mem.h branches/Cog/processors/ARM/gdb-7.10/sim/m32c/misc.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/misc.h branches/Cog/processors/ARM/gdb-7.10/sim/m32c/opc2c.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/r8c.opc branches/Cog/processors/ARM/gdb-7.10/sim/m32c/reg.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/safe-fgets.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/safe-fgets.h branches/Cog/processors/ARM/gdb-7.10/sim/m32c/sample.S branches/Cog/processors/ARM/gdb-7.10/sim/m32c/sample.ld branches/Cog/processors/ARM/gdb-7.10/sim/m32c/sample2.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/srcdest.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/syscall.h branches/Cog/processors/ARM/gdb-7.10/sim/m32c/syscalls.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/syscalls.h branches/Cog/processors/ARM/gdb-7.10/sim/m32c/timer_a.h branches/Cog/processors/ARM/gdb-7.10/sim/m32c/trace.c branches/Cog/processors/ARM/gdb-7.10/sim/m32c/trace.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/ branches/Cog/processors/ARM/gdb-7.10/sim/m32r/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/m32r/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/m32r/README branches/Cog/processors/ARM/gdb-7.10/sim/m32r/TODO branches/Cog/processors/ARM/gdb-7.10/sim/m32r/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/m32r/arch.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/arch.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/config.in branches/Cog/processors/ARM/gdb-7.10/sim/m32r/configure branches/Cog/processors/ARM/gdb-7.10/sim/m32r/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/m32r/cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/cpu2.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/cpu2.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/cpuall.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/cpux.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/cpux.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/decode.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/decode.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/decode2.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/decode2.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/decodex.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/decodex.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/devices.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/m32r-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/m32r.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/m32r2.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/m32rx.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/mloop.in branches/Cog/processors/ARM/gdb-7.10/sim/m32r/mloop2.in branches/Cog/processors/ARM/gdb-7.10/sim/m32r/mloopx.in branches/Cog/processors/ARM/gdb-7.10/sim/m32r/model.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/model2.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/modelx.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/sem-switch.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/sem.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/sem2-switch.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/semx-switch.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/sim-if.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/syscall.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/m32r/traps-linux.c branches/Cog/processors/ARM/gdb-7.10/sim/m32r/traps.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/ branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/config.in branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/configure branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/dv-m68hc11.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/dv-m68hc11eepr.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/dv-m68hc11sio.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/dv-m68hc11spi.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/dv-m68hc11tim.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/dv-nvram.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/emulos.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/gencode.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/interrupts.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/interrupts.h branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/m68hc11_sim.c branches/Cog/processors/ARM/gdb-7.10/sim/m68hc11/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/mcore/ branches/Cog/processors/ARM/gdb-7.10/sim/mcore/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/mcore/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/mcore/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/mcore/config.in branches/Cog/processors/ARM/gdb-7.10/sim/mcore/configure branches/Cog/processors/ARM/gdb-7.10/sim/mcore/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/mcore/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/mcore/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/ branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/config.in branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/configure branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/microblaze.h branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/microblaze.isa branches/Cog/processors/ARM/gdb-7.10/sim/microblaze/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/mips/ branches/Cog/processors/ARM/gdb-7.10/sim/mips/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/mips/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/mips/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/mips/config.in branches/Cog/processors/ARM/gdb-7.10/sim/mips/configure branches/Cog/processors/ARM/gdb-7.10/sim/mips/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/mips/cp1.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/cp1.h branches/Cog/processors/ARM/gdb-7.10/sim/mips/dsp.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/dsp.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/dsp2.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/dv-tx3904cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/dv-tx3904irc.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/dv-tx3904sio.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/dv-tx3904tmr.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/m16.dc branches/Cog/processors/ARM/gdb-7.10/sim/mips/m16.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/m16e.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/m16run.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/mdmx.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/mdmx.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/mips.dc branches/Cog/processors/ARM/gdb-7.10/sim/mips/mips.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/mips3264r2.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/mips3d.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/sb1.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/sim-main.c branches/Cog/processors/ARM/gdb-7.10/sim/mips/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/mips/smartmips.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/mips/tx.igen branches/Cog/processors/ARM/gdb-7.10/sim/mips/vr.igen branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/ branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/am33-2.igen branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/am33.igen branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/config.in branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/configure branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/dv-mn103cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/dv-mn103int.c branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/dv-mn103iop.c branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/dv-mn103ser.c branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/dv-mn103tim.c branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/mn10300.dc branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/mn10300.igen branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/mn10300_sim.h branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/op_utils.c branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/sim-main.c branches/Cog/processors/ARM/gdb-7.10/sim/mn10300/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/moxie/ branches/Cog/processors/ARM/gdb-7.10/sim/moxie/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/moxie/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/moxie/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/moxie/config.in branches/Cog/processors/ARM/gdb-7.10/sim/moxie/configure branches/Cog/processors/ARM/gdb-7.10/sim/moxie/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/moxie/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/moxie/moxie-gdb.dts branches/Cog/processors/ARM/gdb-7.10/sim/moxie/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/msp430/ branches/Cog/processors/ARM/gdb-7.10/sim/msp430/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/msp430/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/msp430/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/msp430/config.in branches/Cog/processors/ARM/gdb-7.10/sim/msp430/configure branches/Cog/processors/ARM/gdb-7.10/sim/msp430/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/msp430/msp430-sim.c branches/Cog/processors/ARM/gdb-7.10/sim/msp430/msp430-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/msp430/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/msp430/trace.c branches/Cog/processors/ARM/gdb-7.10/sim/msp430/trace.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ branches/Cog/processors/ARM/gdb-7.10/sim/ppc/.gdbinit branches/Cog/processors/ARM/gdb-7.10/sim/ppc/BUGS branches/Cog/processors/ARM/gdb-7.10/sim/ppc/COPYING branches/Cog/processors/ARM/gdb-7.10/sim/ppc/COPYING.LIB branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ChangeLog.00 branches/Cog/processors/ARM/gdb-7.10/sim/ppc/INSTALL branches/Cog/processors/ARM/gdb-7.10/sim/ppc/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/ppc/README branches/Cog/processors/ARM/gdb-7.10/sim/ppc/RUN branches/Cog/processors/ARM/gdb-7.10/sim/ppc/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/ppc/altivec.igen branches/Cog/processors/ARM/gdb-7.10/sim/ppc/altivec_expression.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/altivec_registers.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/basics.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/bits.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/bits.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/cap.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/cap.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/config.in branches/Cog/processors/ARM/gdb-7.10/sim/ppc/configure branches/Cog/processors/ARM/gdb-7.10/sim/ppc/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/ppc/corefile-n.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/corefile.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/corefile.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/dc-complex branches/Cog/processors/ARM/gdb-7.10/sim/ppc/dc-simple branches/Cog/processors/ARM/gdb-7.10/sim/ppc/dc-stupid branches/Cog/processors/ARM/gdb-7.10/sim/ppc/dc-test.01 branches/Cog/processors/ARM/gdb-7.10/sim/ppc/dc-test.02 branches/Cog/processors/ARM/gdb-7.10/sim/ppc/debug.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/debug.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/device.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/device.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/device_table.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/device_table.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/dgen.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/double.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/dp-bit.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/e500.igen branches/Cog/processors/ARM/gdb-7.10/sim/ppc/e500_expression.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/e500_registers.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_bugapi.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_bugapi.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_chirp.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_chirp.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_generic.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_generic.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_netbsd.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_netbsd.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_unix.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/emul_unix.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/events.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/events.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/filter.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/filter.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/filter_filename.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/filter_filename.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gdb-sim.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-icache.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-icache.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-idecode.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-idecode.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-itable.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-itable.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-model.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-model.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-semantics.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-semantics.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-support.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/gen-support.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_com.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_core.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_disk.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_eeprom.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_glue.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_htab.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_ide.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_init.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_iobus.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_memory.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_nvram.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_opic.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_pal.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_phb.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_phb.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_register.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_sem.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_shm.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_trace.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/hw_vm.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/idecode_branch.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/idecode_expression.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/idecode_fields.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/igen.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/igen.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/inline.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/inline.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/interrupts.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/interrupts.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ld-cache.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ld-cache.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ld-decode.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ld-decode.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ld-insn.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ld-insn.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/lf.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/lf.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/main.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/misc.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/misc.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/mon.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/mon.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/options.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/options.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/os_emul.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/os_emul.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/pk_disklabel.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ppc-instructions branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ppc-spr-table branches/Cog/processors/ARM/gdb-7.10/sim/ppc/ppc.mt branches/Cog/processors/ARM/gdb-7.10/sim/ppc/psim.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/psim.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/psim.texinfo branches/Cog/processors/ARM/gdb-7.10/sim/ppc/registers.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/registers.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/sim-endian-n.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/sim-endian.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/sim-endian.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/sim_callbacks.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/sim_calls.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/std-config.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/table.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/table.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/tree.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/tree.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/vm.c branches/Cog/processors/ARM/gdb-7.10/sim/ppc/vm.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/vm_n.h branches/Cog/processors/ARM/gdb-7.10/sim/ppc/words.h branches/Cog/processors/ARM/gdb-7.10/sim/rl78/ branches/Cog/processors/ARM/gdb-7.10/sim/rl78/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/rl78/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/rl78/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/rl78/config.in branches/Cog/processors/ARM/gdb-7.10/sim/rl78/configure branches/Cog/processors/ARM/gdb-7.10/sim/rl78/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/rl78/cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/rl78/cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/rl78/gdb-if.c branches/Cog/processors/ARM/gdb-7.10/sim/rl78/load.c branches/Cog/processors/ARM/gdb-7.10/sim/rl78/load.h branches/Cog/processors/ARM/gdb-7.10/sim/rl78/main.c branches/Cog/processors/ARM/gdb-7.10/sim/rl78/mem.c branches/Cog/processors/ARM/gdb-7.10/sim/rl78/mem.h branches/Cog/processors/ARM/gdb-7.10/sim/rl78/rl78.c branches/Cog/processors/ARM/gdb-7.10/sim/rl78/trace.c branches/Cog/processors/ARM/gdb-7.10/sim/rl78/trace.h branches/Cog/processors/ARM/gdb-7.10/sim/rx/ branches/Cog/processors/ARM/gdb-7.10/sim/rx/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/rx/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/rx/README.txt branches/Cog/processors/ARM/gdb-7.10/sim/rx/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/rx/config.in branches/Cog/processors/ARM/gdb-7.10/sim/rx/configure branches/Cog/processors/ARM/gdb-7.10/sim/rx/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/rx/cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/rx/err.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/err.h branches/Cog/processors/ARM/gdb-7.10/sim/rx/fpu.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/fpu.h branches/Cog/processors/ARM/gdb-7.10/sim/rx/gdb-if.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/load.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/load.h branches/Cog/processors/ARM/gdb-7.10/sim/rx/main.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/mem.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/mem.h branches/Cog/processors/ARM/gdb-7.10/sim/rx/misc.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/misc.h branches/Cog/processors/ARM/gdb-7.10/sim/rx/reg.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/rx.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/syscall.h branches/Cog/processors/ARM/gdb-7.10/sim/rx/syscalls.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/syscalls.h branches/Cog/processors/ARM/gdb-7.10/sim/rx/trace.c branches/Cog/processors/ARM/gdb-7.10/sim/rx/trace.h branches/Cog/processors/ARM/gdb-7.10/sim/sh/ branches/Cog/processors/ARM/gdb-7.10/sim/sh/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/sh/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/sh/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/sh/config.in branches/Cog/processors/ARM/gdb-7.10/sim/sh/configure branches/Cog/processors/ARM/gdb-7.10/sim/sh/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/sh/gencode.c branches/Cog/processors/ARM/gdb-7.10/sim/sh/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/sh/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/sh/syscall.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/ branches/Cog/processors/ARM/gdb-7.10/sim/sh64/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/sh64/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/sh64/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/sh64/arch.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/arch.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/config.in branches/Cog/processors/ARM/gdb-7.10/sim/sh64/configure branches/Cog/processors/ARM/gdb-7.10/sim/sh64/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/sh64/cpu.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/cpu.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/cpuall.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/decode-compact.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/decode-compact.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/decode-media.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/decode-media.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/decode.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/defs-compact.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/defs-media.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/eng-compact.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/eng-media.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/eng.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/mloop-compact.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/mloop-media.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sem-compact-switch.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sem-compact.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sem-media-switch.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sem-media.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sh-desc.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sh-desc.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sh-opc.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sh64-sim.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sh64.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sim-if.c branches/Cog/processors/ARM/gdb-7.10/sim/sh64/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/sh64/tconfig.h branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/.gitignore branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/common/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/common/Make-common.in branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/common/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/common/alu-n-tst.h branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/common/alu-tst.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/common/bits-gen.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/common/bits-tst.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/common/fpu-tst.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/config/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/config/default.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/configure branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/configure branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/exit47.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/hello.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/loop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld-d.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld-i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld-id.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld-im.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld-ip.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld2w-d.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld2w-i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld2w-id.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld2w-im.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-ld2w-ip.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st-d.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st-i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st-id.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st-im.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st-ip.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st-is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st2w-d.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st2w-i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st2w-id.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st2w-im.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st2w-ip.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ae-st2w-is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-dbt.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-ld-st.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-mac.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-macros.i branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-mod-ld-pre.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-msbu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-mulxu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-mvtac.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-mvtc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-rac.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-rachi.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-rdt.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-rep.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-rie-xx.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-rte.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-sac.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-sachi.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-sadd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-slae.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-sp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-sub.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-sub2w.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-subi.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/d10v-elf/t-trap.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/cache.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/configure branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/exit47.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/grloop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/hello.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/frv-elf/loop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/lib/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/lib/sim-defs.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/m32r-elf/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/m32r-elf/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/m32r-elf/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/m32r-elf/configure branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/m32r-elf/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/m32r-elf/exit47.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/m32r-elf/hello.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/m32r-elf/loop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/mips64el-elf/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/mips64el-elf/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/mips64el-elf/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/mips64el-elf/configure branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/mips64el-elf/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/adc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/add.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/and.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/b.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/bic.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/bl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/bx.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/cmn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/cmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/eor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/hello.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/textrm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/tmia.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wacc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wadd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/waligni.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/walignr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wand.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wandn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wmac.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wmax.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wmin.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wmov.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wmul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wpack.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wror.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wsad.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wsll.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wsra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wsub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wxor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/iwmmxt/wzero.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/ldm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/ldr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/ldrb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/ldrh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/ldrsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/ldrsh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/misaligned1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/misaligned2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/misaligned3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/misc.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/mla.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/mov.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/movw-movt.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/mrs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/msr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/mul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/mvn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/orr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/rsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/rsc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/sbc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/smlal.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/smull.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/stm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/str.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/strb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/strh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/sub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/swi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/swp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/swpb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/teq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/adc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/add-sp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/add.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/addi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/addi8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/allthumb.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/and.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/asr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/b.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bcs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/beq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bic.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bl-hi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bl-lo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ble.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/blt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bmi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bpl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bvc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bvs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bx-hs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/bx-rs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/cmn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/cmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/eor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/lda-pc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/lda-sp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldmia.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldr-imm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldr-pc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldrb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldrh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ldsh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/lsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/lsr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/mov.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/mul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/mvn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/neg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/orr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/pop-pc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/pop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/push-lr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/push.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/ror.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/sbc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/stmia.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/str-imm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/str-sprel.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/str.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/strb-imm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/strb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/strh-imm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/strh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/sub-sp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/sub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/subi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/subi8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/swi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/thumb/tst.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/tst.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/umlal.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/umull.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/xscale/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/xscale/blx.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/xscale/mia.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/xscale/miaph.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/xscale/miaxy.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/xscale/mra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/xscale/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/arm/xscale/xscale.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/avr/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/avr/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/avr/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/avr/pass.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/avr/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/.gitignore branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/10272_small.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/10436.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/10622.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/10742.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/10799.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/11080.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/7641.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/PN_generator.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a0shift.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a10.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a11.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a12.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a20.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a21.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a22.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a23.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a24.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a25.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a26.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a30.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a4.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a5.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a6.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a7.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a8.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/a9.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/abs-2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/abs-3.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/abs-4.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/abs.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/abs_acc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/acc-rot.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/acp5_19.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/acp5_4.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/add_imm7.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/add_shift.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/add_sub_acc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/addsub_flags.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/algnbug1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/algnbug2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/argc.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/ashift.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/ashift_flags.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/b0.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/b1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/b2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/brcc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/brevadd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/byteop16m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/byteop16p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/byteop1p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/byteop2p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/byteop3p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/byteunpack.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_arith_r_sft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_conv_b.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_conv_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_conv_mix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_conv_neg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_conv_toggle.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_conv_xb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_conv_xh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_divq.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_divs.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_log_l_sft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_log_r_sft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_shadd_1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_alu2op_shadd_2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_br_preg_killed_ac.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_br_preg_killed_ex1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_br_preg_stall_ac.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_br_preg_stall_ex1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_bp1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_bp2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_bp3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_bp4.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_brf_bp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_brf_brt_bp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_brf_brt_nbp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_brf_fbkwd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_brf_nbp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_brt_bp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_brt_nbp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_kills_dhits.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_brcc_kills_dmiss.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cactrl_iflush_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_calla_ljump.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_calla_subr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc2dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc2stat_cc_an.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc2stat_cc_aq.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc2stat_cc_av0.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc2stat_cc_az.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc_flag_ccmv_depend.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_s1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_sn.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_s1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_sn.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_a0a1.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_dr_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_dr_dr_uu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_pr_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_mix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_flags.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_flags_2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_abs.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_absabs.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_awx.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_max.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_min.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_minmin.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_mix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rmm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rmp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rpm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rpp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_saa.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_search.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_sgn.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_mix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_u.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_u.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair_is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair_m.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_is.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_u.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_a0alr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_af.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_af_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_align16.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_align24.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_align8.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_amix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_bxor.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_fextx.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_lf.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_lhh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_lmix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_ones.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_pack.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_rot.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_vmax.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_af.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_except_illopcode.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_except_sys_sstep.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_except_user_mode.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_disable.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_disable_enable.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_excpt.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_nested.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_nmi.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_pending.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_pending_2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_timer.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_timer_reload.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_timer_tcount.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_interr_timer_tscale.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_p_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_d.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_p.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstii_ld_preg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstii_st_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstii_st_preg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_linkage.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_arith_shft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_bitclr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_bitset.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_bittgl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_bittst.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_log_l_shft_astat.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_log_r_shft_astat.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_logi2op_nbittst.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_nested.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_nested_top.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_overlap.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_prelc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_mmr_loop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_mmr_timer.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_mode_supervisor.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_mode_user.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_mode_user_superivsor.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_call_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_except_rtx.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_excpt.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_nop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_progctrl_rts.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_acc_acc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_dr_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_dr_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_imlb_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_imlb_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_pr_dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_pr_imlb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_regmv_pr_pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ujump.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cc-alu.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cc-astat-bits.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cc0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cc1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cc5.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cec-exact-exception.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cec-ifetch.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cec-multi-pending.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cec-no-snen-reti.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cec-non-operating-env.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cec-raise-reti.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cec-snen-reti.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cec-syscfg-ssstep.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cec-system-call.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cir.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cir1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cli-sti.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cmpacc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cmpdreg.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/compare.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/conv_enc_gen.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/cycles.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/d0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/d1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/d2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dbg_tr_basic.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dbg_tr_simplejp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dbg_tr_umode.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/disalnexcpt_implicit.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/div0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/divq.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dotproduct.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dotproduct2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/double_prec_mult.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dsp_a4.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dsp_a7.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dsp_a8.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dsp_d0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dsp_d1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dsp_neg.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/dsp_s1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/e0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/edn_snafu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/eu_dsp32mac_s.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/events.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/f221.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/fact.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/fir.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/fsm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/greg2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/hwloop-bits.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/hwloop-branch-in.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/hwloop-branch-out.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/hwloop-lt-bits.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/hwloop-nested.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/i0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/iir.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue103.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue109.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue112.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue113.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue117.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue118.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue119.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue121.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue123.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue124.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue125.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue126.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue127.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue129.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue139.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue140.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue142.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue144.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue146.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue175.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue205.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue257.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue272.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue83.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/issue89.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/l0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/l0shift.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/l2_loop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/link-2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/link.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lmu_cplb_multiple0.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lmu_cplb_multiple1.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lmu_excpt_align.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lmu_excpt_default.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lmu_excpt_illaddr.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lmu_excpt_prot0.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lmu_excpt_prot1.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/load.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/logic.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/loop_snafu.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/loop_strncpy.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lp0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lp1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/lsetup.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m0boundary.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m1.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m10.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m11.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m12.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m13.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m14.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m15.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m16.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m17.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m4.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m5.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m6.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m7.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m8.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/m9.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mac2halfreg.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/math.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/max_min_flags.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mc_s2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mdma-32bit-1d-neg-count.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mdma-32bit-1d.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mdma-8bit-1d-neg-count.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mdma-8bit-1d.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mdma-skel.h branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mem3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mmr-exception.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/move.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/msa_acp_5.10.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/msa_acp_5.12_1.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/msa_acp_5.12_2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/msa_acp_5_10.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/mult.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/neg-2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/neg-3.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/neg.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/nshift.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/pr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/push-pop-multiple.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/push-pop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/pushpopreg_1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/quadaddsub.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0001.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0002.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0003.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0004.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0005.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0006.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0007.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0008.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0009.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0010.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0011.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0012.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0013.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0014.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0015.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0016.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0017.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0018.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0019.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0020.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0021.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0022.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0023.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0024.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0025.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0026.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0027.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0028.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0029.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0030.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0031.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0032.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0033.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0034.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0035.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0036.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/random_0037.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/run-tests.sh branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s10.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s11.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s12.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s13.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s14.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s15.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s16.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s17.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s18.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s19.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s20.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s21.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s30.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s4.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s5.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s6.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s7.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s8.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/s9.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/saatest.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_all16bitopcodes.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_all32bitopcodes.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_all32bitopcodes.lds branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_all64bitg0opcodes.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_all64bitg1opcodes.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_all64bitg2opcodes.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_allopcodes.h branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_brtarget_stall.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_bug_ui.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_bug_ui2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_bug_ui3.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_cc2stat_haz.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_cc_kill.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_cof.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_event_quad.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_excpt_ssstep.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_illegalcombination.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_kill_wbbr.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_kills2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_disable.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_kill.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_kill_01.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_kill_dcr.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_lr.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_mv2lc.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_nest_ppm.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_ppm.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_ppm_1.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_loop_ppm_int.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_lsetup_kill.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_misaligned_fetch.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_more_ret_haz.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_mv2lp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_oneins_zoff.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_popkill.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_rets_hazard.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_rts_rti.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_ssync.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_stall_if2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_undefinedinstruction1.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_undefinedinstruction2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_undefinedinstruction3.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_undefinedinstruction4.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/se_usermode_protviol.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/seqstat.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/sign.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/simple0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/sri.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/stk.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/stk2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/stk3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/stk4.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/stk5.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/stk6.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/syscfg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/tar10622.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/test-dma.h branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/test.h branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/testset.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/testset2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/unlink.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/up0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/usp.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/vec-abs-2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/vec-abs-3.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/vec-abs.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/vec-neg-2.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/vec-neg-3.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/vec-neg.S branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/vecadd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/vit_max.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/vit_max2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/viterbi2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/wtf.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/x1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/zcall.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/zeroflagrnd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/addb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/addd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/addi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/addw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/andb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/andd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/andw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/ashub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/ashub_i.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/ashud.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/ashud_i.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/ashuw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/ashuw_i.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bal1_24.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bal2_24.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bcs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/beq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/beq0b.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/beq0w.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bht.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/blo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/blt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bne0b.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/bne0w.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/br.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/cbitb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/cbitw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/cmpb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/cmpb_i.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/cmpd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/cmpd_i.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/cmpi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/cmpw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/cmpw_i.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/excp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/hello.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/hw-trap.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jal.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jcs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jfc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jfs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jlo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jlt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/jump.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/loadb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/loadd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/loadm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/loadmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/loadw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/lpr-spr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/lprd-sprd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/lshb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/lshb_i.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/lshd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/lshd_i.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/lshw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/lshw_i.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/macqw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/macsw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/macuw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/misc.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/movb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/movd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/movw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/movxb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/movxw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/movzb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/movzw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/mulb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/mulsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/mulsw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/muluw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/mulw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/nop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/orb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/ord.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/orw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/pop1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/pop2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/pop3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/popret1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/popret2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/popret3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/push1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/push2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/push3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/sbitb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/sbitw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/scc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/scs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/seq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/sfc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/sfs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/sge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/sgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/shi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/shs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/slo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/sls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/slt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/sne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/storb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/stord.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/storw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/subb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/subd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/subi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/subw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/tbit.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/tbitb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/tbitw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/uread16.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/uread32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/xorb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/xord.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cr16/xorw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/abs.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addcpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addcv32c.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addcv32m.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addcv32r.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addi.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addiv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addoc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addom.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addoq.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addq.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addqpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addswpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addxc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addxm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/addxr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/andc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/andm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/andq.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/andr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/asm.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/asr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/ba.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/badarch1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/bare1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/bare2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/bare3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/bas.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/bccb.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/bdapc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/bdapm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/bdapq.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/bdapqpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/biap.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/boundc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/boundm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/boundmv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/boundr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/break.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/btst.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/ccr-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/ccs-v32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/clearfv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/clearfv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/clrjmp1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/cmpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/cmpm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/cmpq.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/cmpr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/cmpxc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/cmpxm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/dflags.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/dip.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/dstep.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/fidxd.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/fidxi.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/ftagd.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/ftagi.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/halt.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/io1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/io2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/io3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/io4.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/io5.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/io6.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/io7.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/io8.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/io9.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/jsr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/jsrmv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/jumpmp.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/jumppv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/lapc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/lsl.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/lsr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/lz.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/mcp.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movdelsr1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movecpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movecr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movecrt10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movecrt32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movect10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movei.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movempc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movemr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movemrv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movemrv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movepcb.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movepcd.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movepcw.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/moveq.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/moveqpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/mover.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/moverbpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/moverdpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/moverm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/moverpcb.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/moverpcd.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/moverpcw.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/moverwpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movesmp.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movmp.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movmp8.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movpmv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movpmv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movppc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movpr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movprv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movprv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movrss.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movscpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movscr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movsm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movsmpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movsr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movsrpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movssr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movucpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movucr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movum.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movumpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movur.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/movurpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/mstep.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/msteppc1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/msteppc2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/msteppc3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/mulv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/mulv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/mulx.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/neg.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/nonvcv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/nopv10t.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/nopv32t.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/nopv32t2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/nopv32t3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/nopv32t4.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/not.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/op3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/opterr1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/opterr2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/opterr3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/opterr4.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/opterr5.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/option1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/option2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/option3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/option4.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/orc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/orm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/orq.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/orr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/pcplus.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/pid1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw11.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw12.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw13.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw14.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw15.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw16.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw17.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw4.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw5.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw6.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw7.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw8.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/raw9.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/ret.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/rfe.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/rfg.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/rfn.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/sbfs.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/scc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/sfe.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/subc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/subm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/subq.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/subqpc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/subr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/subxc.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/subxm.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/subxr.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/swap.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tb.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/test.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tjmpsrv32-2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tjmpsrv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tjsrcv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tjsrcv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmemv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmemv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmulv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmulv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmvm1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmvm2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmvmrv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmvmrv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmvrmv10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/tmvrmv32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/user.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x0-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x0-v32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x1-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x1-v32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x10-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x2-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x2-v32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x3-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x3-v32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x4-v32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x5-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x5-v32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x6-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x6-v32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x7-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x7-v32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x8-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/x9-v10.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/asm/xor.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/access1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/append1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/badldso1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/badldso2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/badldso3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/c.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/clone1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/clone2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/clone3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/clone4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/clone5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/clone6.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/ex1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/exitg1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/exitg2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/fcntl1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/fcntl2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/fdopen1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/fdopen2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/freopen1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/freopen2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/ftruncate1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/ftruncate2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/getcwd1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/gettod.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/hello.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/helloaout.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/hellodyn.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/hellodyn2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/hellodyn3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/kill1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/kill2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/kill3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mapbrk.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mmap1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mmap2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mmap3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mmap4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mmap5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mmap6.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mmap7.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mmap8.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mprotect1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mprotect2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/mremap.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/openpf1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/openpf2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/openpf3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/openpf4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/openpf5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/pipe1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/pipe2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/pipe3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/pipe4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/pipe5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/pipe6.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/pipe7.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink10.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink11.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink6.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink7.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink8.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/readlink9.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/rename2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/rtsigprocmask1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/rtsigprocmask2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/rtsigsuspend1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/rtsigsuspend2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sched1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sched2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sched3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sched4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sched5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sched6.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sched7.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sched8.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sched9.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/seek1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/seek2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/seek3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/seek4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/setrlimit1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/settls1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig10.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig11.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig12.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig13.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig6.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig7.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig8.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sig9.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sigreturn1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sigreturn2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sigreturn3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sigreturn4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sjlj.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sock1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/stat1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/stat2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/stat3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/stat4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/stat5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/stat7.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/stat8.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/syscall1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/syscall2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/syscall3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/syscall4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/syscall5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/syscall6.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/syscall7.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/syscall8.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sysctl1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sysctl2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/sysctl3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/thread2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/thread3.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/thread4.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/thread5.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/time1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/time2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/truncate1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/truncate2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/ugetrlimit1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/uname1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/writev1.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/c/writev2.c branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/host1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/irq1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/irq2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/irq3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/irq4.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/irq5.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/irq6.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/mbox1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/mem1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/mem2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/poll1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/quit.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/std.dev branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/trivial1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/trivial2.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/trivial3.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.r branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/trivial5.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/cris/hw/rv-n-cris/wd1.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/add.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/add.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/add2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/addc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/addn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/addn2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/addsp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/and.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/andb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/andccr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/andh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/asr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/asr2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bandh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bandl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/beorh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/beorl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/beq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ble.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/blt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bnc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bno.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bnv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/borh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/borl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/btsth.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/btstl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/bv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/call.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/cmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/cmp2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/copld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/copop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/copst.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/copsv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/div.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/div0s.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/div0u.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/div1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/div2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/div3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/div4s.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/dmov.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/dmovb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/dmovh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/enter.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/eor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/eorb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/eorh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/extsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/extsh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/extub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/extuh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/hello.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/int.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/inte.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/jmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ldi20.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ldi32.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ldi8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ldm0.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ldm1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ldres.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ldub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/lduh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/leave.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/lsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/lsl2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/lsr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/lsr2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/misc.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/mov.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/mul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/mulh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/mulu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/muluh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/nop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/or.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/orb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/orccr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/orh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/ret.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/reti.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/st.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/stb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/sth.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/stilm.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/stm0.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/stm1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/stres.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/sub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/subc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/subn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/fr30/xchb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/add.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/add.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/addcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/addi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/addicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/addx.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/addxcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/addxi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/addxicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/and.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/andcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/andcr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/andi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/andicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/andncr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bar.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcclr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bceqlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcgelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcgtlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bchilr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bclelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bclr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bclslr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcltlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcnclr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcnelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcnlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcnolr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcnvlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcplr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcralr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bctrlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bcvlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/beq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/beqlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bgelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bgtlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bhilr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ble.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/blelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/blslr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/blt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bltlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bnc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bnclr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bnelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bnlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bno.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bnolr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bnv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bnvlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bplr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bralr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/branch.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/break.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/bvlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cadd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/caddcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/call.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/call.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/callil.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/calll.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cand.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/candcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ccalll.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckle.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ccklt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ccknc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckno.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ccknv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cckv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ccmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfabss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckle.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfcklg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfcklt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckno.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfcko.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfcku.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckue.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckug.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckuge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfckule.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfcmps.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfdivs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfitos.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfmadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfmas.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfmovs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfmss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfmsubs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfmuls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfnegs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfsqrts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfstoi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cfsubs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cjmpl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckle.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cklt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cknc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckno.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cknv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ckv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldbf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldbfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/clddf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/clddfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/clddu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldhf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldhfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldqu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldsbu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldsh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldshu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cldubu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/clduh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/clduhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/clrfa.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/clrfr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/clrga.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/clrgr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmaddhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmaddhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmand.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmbtoh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmbtohe.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmcpxis.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmcpxiu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmcpxrs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmcpxru.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmexpdhd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmexpdhw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmhtob.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmmachu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmmulhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmmulhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmnot.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmov.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmovfg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmovfgd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmovgf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmovgfd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmpb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmpba.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmpi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmqmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmqmachu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmqmulhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmqmulhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmsubhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmsubhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cmxor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cnot.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/commitfa.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/commitfr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/commitga.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/commitgr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cop1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cop2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/corcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cscan.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csdiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csll.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csllcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csmul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csmulcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csracc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csrl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csrlcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cst.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstbf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstbfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstbu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstdf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstdfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstdu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csth.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csthf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csthfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csthu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cstu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/csubcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cswap.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cudiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cxor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/cxorcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/dcef.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/dcei.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/dcf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/dci.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fabsd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fabss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/faddd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbeqlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbgelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbgtlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fble.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fblelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fblg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fblglr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fblt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbltlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbnelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbno.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbnolr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbolr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbralr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbue.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbuelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbug.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbuge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbugelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbuglr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbule.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbulelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbullr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fbulr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbeqlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbgelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbgtlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcblelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcblglr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbltlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbnelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbnolr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbolr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbralr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbuelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbugelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbuglr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbulelr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbullr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcbulr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckle.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcklg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcklt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckno.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcko.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcku.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckue.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckug.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckuge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fckule.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcmpd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fcmps.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdabss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdcmps.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fddivs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fditos.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdivd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdivs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdmadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdmas.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdmovs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdmss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdmulcs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdmuls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdnegs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdsads.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdsqrts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdstoi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdsubs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fdtoi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fitod.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fitos.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmad.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmaddd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmas.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmovd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmovs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmsd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmsubd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmsubs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmuld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fmuls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fnegd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fnegs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fnop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/addss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/csdiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/maddaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/masaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/maveh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/mclracc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/mhdseth.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/mhdsets.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/mhsethih.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/mhsethis.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/mhsetloh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/mhsetlos.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/movgs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/movsg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/msubaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/scutss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/sdiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/sdivi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/slass.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/smass.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/smsss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/smu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/subss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/udiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr400/udivi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/dcpl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/dcul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/mclracc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/mqaddhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/mqaddhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/mqsubhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr500/mqsubhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmaddhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmaddhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmcpxru.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmmachu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmqmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmqmachu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmsubhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/cmsubhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/dcpl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/dcul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mabshs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/maddaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/maddhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/maddhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/masaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mdasaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mmachu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mmrdhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mmrdhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mqaddhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mqaddhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mqmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mqmachu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mqsubhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mqsubhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mqxmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/msubaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/msubhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/msubhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/mtrap.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/udiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fr550/udivi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fsqrtd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fsqrts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fstoi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fsubd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fsubs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fteq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftieq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftige.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftigt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftile.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftilg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftilt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftine.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftino.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftio.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftira.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftiu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftiue.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftiug.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftiuge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftiul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftle.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftlg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftlt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftno.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/fto.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftue.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftug.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftuge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ftule.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/icei.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ici.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/icpl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/icul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/badalign.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/compound.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/data_store_error.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/fp_exception.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/illinsn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/mp_exception.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/regalign.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/reset.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts/timer.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/interrupts.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/jmpil.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/jmpl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/jmpl.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldbf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldbfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldbfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldcu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lddc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lddcu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lddf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lddfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lddfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lddi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lddu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldhf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldhfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldhfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldqc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldqcu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldqf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldqfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldqfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldqi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldqu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldsbi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldsbu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldsh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldshi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldshu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldubi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ldubu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lduh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lduhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lduhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/lrbranch.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mabshs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/maddhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/maddhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mand.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/maveh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mbtoh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mbtohe.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mclracc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcmpsh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcmpuh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcop1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcop2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcplhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcpli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcpxis.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcpxiu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcpxrs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcpxru.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcut.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcuti.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcutss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mcutssi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mdaddaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mdasaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mdcutssi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mdpackh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mdrotli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mdsubaccs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mdunpackh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/membar.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mexpdhd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mexpdhw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mhdseth.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mhdsets.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mhsethih.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mhsethis.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mhsetloh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mhsetlos.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mhtob.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mmachu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mmrdhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mmrdhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mmulhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mmulhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mmulxhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mmulxhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mnop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mnot.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mov.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/movfg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/movfgd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/movfgq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/movgf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/movgfd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/movgfq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/movgs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/movsg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mpackh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqcpxis.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqcpxiu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqcpxrs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqcpxru.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqlclrhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqlmths.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqmachu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqmacxhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqmulhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqmulhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqmulxhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqmulxhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqsaths.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqsllhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqsrahi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqxmachs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mqxmacxhs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mrdacc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mrdaccg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mrotli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mrotri.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/msaths.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/msathu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/msllhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/msrahi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/msrlhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/msubhss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/msubhus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mtrap.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/munpackh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mwcut.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mwcuti.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mwtacc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mwtaccg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/mxor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nandcr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nandncr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdcmps.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfddivs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfditos.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdivs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdmadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdmas.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdmss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdmulcs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdmuls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdsads.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdsqrts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdstoi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfdsubs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfitos.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfmadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfmas.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfmss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfmsubs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfmuls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfsqrts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfstoi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nfsubs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldbf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldbfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldbfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nlddf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nlddfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nlddfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nlddi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nlddu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldhf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldhfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldhfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldqf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldqfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldqfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldqu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldsbi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldsbu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldsh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldshi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldshu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldubi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nldubu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nlduh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nlduhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nlduhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/norcr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/norncr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/not.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/notcr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nsdiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nsdivi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nudiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/nudivi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/or.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/orcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/orcr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ori.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/oricc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/orncr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/parallel.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/ret.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/rett.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/scan.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/scani.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sdiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sdivi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sethi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sethilo.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/setlo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/setlos.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sll.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sllcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/slli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sllicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/smul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/smulcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/smuli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/smulicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sracc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/srai.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sraicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/srl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/srlcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/srli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/srlicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/st.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stbf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stbfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stbfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stbi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stbu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stcu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/std.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/std.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stdc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stdc.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stdcu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stdf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stdf.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stdfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stdfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stdi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stdu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sth.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sthf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sthfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sthfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sthi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sthu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sti.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stq.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stqc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stqc.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stqcu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stqf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stqf.pcgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stqfi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stqfu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stqi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stqu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/stu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/sub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/subcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/subi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/subicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/subx.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/subxcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/subxi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/subxicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/swap.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/swapi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/teq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/thi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tic.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tieq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tige.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tigt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tihi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tile.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tils.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tilt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tin.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tinc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tine.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tino.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tinv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tip.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tira.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tle.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tlt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tn.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tnc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tno.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tnv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/tv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/udiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/udivi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/umul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/umulcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/umuli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/umulicc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/xor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/xorcc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/xorcr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/xori.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/frv/xoricc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/ft32/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/ft32/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/ft32/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/ft32/basic.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/ft32/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/addb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/addl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/adds.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/addw.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/addx.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/andb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/andl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/andw.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/band.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/bfld.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/biand.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/bra.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/brabc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/bset.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/cmpb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/cmpl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/cmpw.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/daa.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/das.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/dec.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/div.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/extl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/extw.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/inc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/jmp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/ldc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/ldm.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/mac.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/mova.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/movb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/movl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/movmd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/movsd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/movw.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/mul.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/neg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/nop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/not.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/orb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/orl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/orw.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/rotl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/rotr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/rotxl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/rotxr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/shal.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/shar.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/shll.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/shlr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/stack.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/stc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/subb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/subl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/subs.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/subw.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/subx.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/tas.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/xorb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/xorl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/h8300/xorw.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/iq2000/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/iq2000/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/iq2000/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/iq2000/pass.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/iq2000/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/lm32/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/lm32/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/lm32/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/lm32/pass.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/lm32/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/add.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/add3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/addi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/addv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/addv3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/addx.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/and.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/and3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bc24.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bc8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/beq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/beqz.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bgez.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bgtz.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bl24.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bl8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/blez.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bltz.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bnc24.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bnc8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bnez.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bra24.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/bra8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/cmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/cmpi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/cmpu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/cmpui.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/div.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/divu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/hello.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/hw-trap.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/jl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/jmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ld-d.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ld-plus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ld24.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ldb-d.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ldb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ldh-d.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ldh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ldi16.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ldi8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ldub-d.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/ldub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/lduh-d.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/lduh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/lock.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/machi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/maclo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/macwhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/macwlo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/misc.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mulhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mullo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mulwhi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mulwlo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mvfachi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mvfaclo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mvfacmi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mvfc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mvtachi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mvtaclo.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/mvtc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/neg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/nop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/not.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/or.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/or3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/rac.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/rach.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/rem.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/remu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/rte.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/seth.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/sll.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/sll3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/slli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/sra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/sra3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/srai.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/srl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/srl3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/srli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/st-d.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/st-minus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/st-plus.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/st.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/stb-d.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/stb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/sth-d.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/sth.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/sub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/subv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/subx.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/trap.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/unlock.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/uread16.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/uread32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/uwrite16.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/uwrite32.ms branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/xor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m32r/xor3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m68hc11/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m68hc11/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m68hc11/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m68hc11/pass.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/m68hc11/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mcore/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mcore/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mcore/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mcore/pass.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mcore/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/microblaze/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/microblaze/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/microblaze/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/microblaze/pass.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/microblaze/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/basic.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/fpu64-ps-sb1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/fpu64-ps.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/hilo-hazard-1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/hilo-hazard-2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/hilo-hazard-3.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/mdmx-ob-sb1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/mdmx-ob.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/mips32-dsp.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/mips32-dsp2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/sanity.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/utils-dsp.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/utils-fpu.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mips/utils-mdmx.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mn10300/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mn10300/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mn10300/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mn10300/pass.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/mn10300/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/moxie/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/moxie/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/moxie/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/moxie/pass.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/moxie/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/msp430/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/msp430/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/msp430/add.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/msp430/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/msp430/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/add.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/allinsn.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/and.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/bandor.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/bandornot.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/bclr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/bld.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/bldnot.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/bset.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/bst.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/bxor.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/clip.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/div.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/dmxy.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fabs.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fadd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fail.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fcmpeq.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fcmpgt.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fcnvds.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fcnvsd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fdiv.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fipr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fldi0.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fldi1.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/flds.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/float.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fmac.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fmov.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fmul.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fneg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fpchg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/frchg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fsca.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fschg.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fsqrt.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fsrra.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/fsub.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/ftrc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/ldrc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/loop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/macl.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/macw.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/mov.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/movi.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/movli.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/movua.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/movxy.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/mulr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pabs.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/padd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/paddc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pand.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pass.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pclr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pdec.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pdmsb.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pinc.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pmuls.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/prnd.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pshai.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pshar.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pshli.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pshlr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/psub.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pswap.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/pushpop.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/resbank.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/sett.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/shll.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/shll16.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/shll2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/shll8.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/shlr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/shlr16.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/shlr2.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/shlr8.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/swap.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/add.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/addc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/addi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/addv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/and.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/andb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/andi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/bf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/bfs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/bra.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/braf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/brk.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/bsr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/bsrf.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/bt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/bts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/clrmac.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/clrs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/clrt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/cmpeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/cmpeqi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/cmpge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/cmpgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/cmphi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/cmphs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/cmppl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/cmppz.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/cmpstr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/div0s.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/div0u.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/div1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/dmulsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/dmulul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/dt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/extsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/extsw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/extub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/extuw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fabs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fadd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fcmpeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fcmpgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fcnvds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fcnvsd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fdiv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fipr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fldi0.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fldi1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/flds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/float.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fmac.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fmov.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fmul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fneg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/frchg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fschg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fsqrt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fsts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/fsub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ftrc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ftrv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/jmp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/jsr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/lds-fpul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/lds-mach.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/lds-macl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/lds-pr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/macl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/macw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/mov.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/mova.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb10.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb4.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb5.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb6.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb7.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movb9.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movcal.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl10.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl11.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl4.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl5.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl6.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl7.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movl9.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw10.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw11.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw4.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw5.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw6.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw7.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/movw9.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/mull.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/mulsw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/muluw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/neg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/negc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/nop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/not.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ocbi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ocbp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ocbwb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/or.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/orb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/ori.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/pref.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/rotcl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/rotcr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/rotl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/rotr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/rts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/sets.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/sett.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shad.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shal.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shar.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shll.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shll16.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shll2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shll8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shlr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shlr16.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shlr2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/shlr8.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/stc-gbr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/sts-fpul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/sts-mach.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/sts-macl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/sts-pr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/stsl-mach.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/stsl-macl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/stsl-pr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/sub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/subc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/subv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/swapb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/swapw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/tasb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/trapa.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/tst.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/tstb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/tsti.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/xor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/xorb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/xori.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact/xtrct.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/compact.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/interwork.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/add.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/addi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/addil.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/addl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/addzl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/alloco.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/and.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/andc.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/andi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/beq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/beqi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/bge.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/bgeu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/bgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/bgtu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/blink.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/bne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/bnei.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/brk.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/byterev.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/cmpeq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/cmpgt.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/cmpgtu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/cmveq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/cmvne.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fabsd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fabss.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/faddd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fadds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcmpeqd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcmpeqs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcmpged.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcmpges.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcmpgtd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcmpgts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcmpund.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcmpuns.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcnvds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fcnvsd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fdivd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fdivs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fgetscr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fiprs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fldd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fldp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/flds.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fldxd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fldxp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fldxs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/floatld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/floatls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/floatqd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/floatqs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fmacs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fmovd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fmovdq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fmovls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fmovqd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fmovs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fmovsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fmuld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fmuls.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fnegd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fnegs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fputscr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fsqrtd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fsqrts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fstd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fstp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fsts.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fstxd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fstxp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fstxs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fsubd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/fsubs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ftrcdl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ftrcdq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ftrcsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ftrcsq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ftrvs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/getcfg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/getcon.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/gettr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/icbi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldhil.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldhiq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldlol.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldloq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/lduw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldxb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldxl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldxq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldxub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldxuw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ldxw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mabsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mabsw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/maddl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/maddsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/maddsub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/maddsw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/maddw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcmpeqb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcmpeql.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcmpeqw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcmpgtl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcmpgtub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcmpgtw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcmv.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcnvslw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcnvswb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mcnvswub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mextr1.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mextr2.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mextr3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mextr4.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mextr5.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mextr6.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mextr7.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmacfxwl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmulfxl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmulfxw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmulhiwl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmull.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmullowl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmulsumwq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mmulw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/movi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mpermw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/msadubq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshaldsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshaldsw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshardl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshardsq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshardw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshfhib.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshfhil.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshfhiw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshflob.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshflol.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshflow.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshlldl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshlldw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshlrdl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mshlrdw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/msubl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/msubsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/msubsub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/msubsw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/msubw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mulsl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/mulul.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/nop.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/nsb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ocbi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ocbp.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ocbwb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/or.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ori.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/prefi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/pta.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ptabs.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ptb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/ptrel.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/putcfg.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/putcon.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/rte.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shard.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shardl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shari.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/sharil.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shlld.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shlldl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shlli.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shllil.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shlrd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shlrdl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shlri.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shlril.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/shori.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/sleep.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/sthil.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/sthiq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stlol.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stloq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stxb.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stxl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stxq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/stxw.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/sub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/subl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/swapq.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/synci.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/synco.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/trapa.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/xor.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media/xori.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/media.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/misc/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/sh64/misc/fr-dr.s branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/ branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/allinsns.exp branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/bsh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/div.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/divh.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/divh_3.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/divhu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/divu.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/sar.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/satadd.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/satsub.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/satsubi.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/satsubr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/shl.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/shr.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/testutils.cgs branches/Cog/processors/ARM/gdb-7.10/sim/testsuite/sim/v850/testutils.inc branches/Cog/processors/ARM/gdb-7.10/sim/v850/ branches/Cog/processors/ARM/gdb-7.10/sim/v850/ChangeLog branches/Cog/processors/ARM/gdb-7.10/sim/v850/Makefile.in branches/Cog/processors/ARM/gdb-7.10/sim/v850/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/sim/v850/config.in branches/Cog/processors/ARM/gdb-7.10/sim/v850/configure branches/Cog/processors/ARM/gdb-7.10/sim/v850/configure.ac branches/Cog/processors/ARM/gdb-7.10/sim/v850/interp.c branches/Cog/processors/ARM/gdb-7.10/sim/v850/sim-main.h branches/Cog/processors/ARM/gdb-7.10/sim/v850/simops.c branches/Cog/processors/ARM/gdb-7.10/sim/v850/simops.h branches/Cog/processors/ARM/gdb-7.10/sim/v850/v850-dc branches/Cog/processors/ARM/gdb-7.10/sim/v850/v850.igen branches/Cog/processors/ARM/gdb-7.10/sim/v850/v850_sim.h branches/Cog/processors/ARM/gdb-7.10/src-release.sh branches/Cog/processors/ARM/gdb-7.10/symlink-tree branches/Cog/processors/ARM/gdb-7.10/ylwrap branches/Cog/processors/ARM/gdb-7.10/zlib/ branches/Cog/processors/ARM/gdb-7.10/zlib/CMakeLists.txt branches/Cog/processors/ARM/gdb-7.10/zlib/ChangeLog branches/Cog/processors/ARM/gdb-7.10/zlib/ChangeLog.gcj branches/Cog/processors/ARM/gdb-7.10/zlib/ChangeLog.jit branches/Cog/processors/ARM/gdb-7.10/zlib/FAQ branches/Cog/processors/ARM/gdb-7.10/zlib/INDEX branches/Cog/processors/ARM/gdb-7.10/zlib/Makefile.am branches/Cog/processors/ARM/gdb-7.10/zlib/Makefile.in branches/Cog/processors/ARM/gdb-7.10/zlib/README branches/Cog/processors/ARM/gdb-7.10/zlib/acinclude.m4 branches/Cog/processors/ARM/gdb-7.10/zlib/aclocal.m4 branches/Cog/processors/ARM/gdb-7.10/zlib/adler32.c branches/Cog/processors/ARM/gdb-7.10/zlib/amiga/ branches/Cog/processors/ARM/gdb-7.10/zlib/amiga/Makefile.pup branches/Cog/processors/ARM/gdb-7.10/zlib/amiga/Makefile.sas branches/Cog/processors/ARM/gdb-7.10/zlib/as400/ branches/Cog/processors/ARM/gdb-7.10/zlib/as400/bndsrc branches/Cog/processors/ARM/gdb-7.10/zlib/as400/compile.clp branches/Cog/processors/ARM/gdb-7.10/zlib/as400/readme.txt branches/Cog/processors/ARM/gdb-7.10/zlib/as400/zlib.inc branches/Cog/processors/ARM/gdb-7.10/zlib/compress.c branches/Cog/processors/ARM/gdb-7.10/zlib/configure branches/Cog/processors/ARM/gdb-7.10/zlib/configure.ac branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/README.contrib branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/buffer_demo.adb branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/mtest.adb branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/read.adb branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/readme.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/test.adb branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/zlib-streams.adb branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/zlib-streams.ads branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/zlib-thin.adb branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/zlib-thin.ads branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/zlib.adb branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/zlib.ads branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/ada/zlib.gpr branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/amd64/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/amd64/amd64-match.S branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/asm686/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/asm686/README.686 branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/asm686/match.S branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/blast/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/blast/Makefile branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/blast/README branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/blast/blast.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/blast/blast.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/blast/test.pk branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/blast/test.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/delphi/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/delphi/ZLib.pas branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/delphi/ZLibConst.pas branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/delphi/readme.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/delphi/zlibd32.mak branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/AssemblyInfo.cs branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/ChecksumImpl.cs branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/CircularBuffer.cs branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/CodecBase.cs branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/Deflater.cs branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/DotZLib.cs branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/DotZLib.csproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/GZipStream.cs branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/Inflater.cs branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib/UnitTests.cs branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib.build branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib.chm branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/DotZLib.sln branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/LICENSE_1_0.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/dotzlib/readme.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/gcc_gvmat64/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/gcc_gvmat64/gvmat64.S branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/infback9/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/infback9/README branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/infback9/infback9.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/infback9/infback9.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/infback9/inffix9.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/infback9/inflate9.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/infback9/inftree9.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/infback9/inftree9.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/inflate86/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/inflate86/inffas86.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/inflate86/inffast.S branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream/test.cpp branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream/zfstream.cpp branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream/zfstream.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream2/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream2/zstream.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream2/zstream_test.cpp branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream3/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream3/README branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream3/TODO branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream3/test.cc branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream3/zfstream.cc branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/iostream3/zfstream.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx64/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx64/bld_ml64.bat branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx64/gvmat64.asm branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx64/gvmat64.obj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx64/inffas8664.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx64/inffasx64.asm branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx64/inffasx64.obj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx64/readme.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx86/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx86/bld_ml32.bat branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx86/gvmat32.obj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx86/inffas32.asm branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx86/inffas32.obj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx86/match686.asm branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/masmx86/readme.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/Makefile branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/Makefile.am branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/MiniZip64_Changes.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/MiniZip64_info.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/configure.ac branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/crypt.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/ioapi.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/ioapi.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/iowin32.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/iowin32.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/make_vms.com branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/miniunz.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/minizip.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/minizip.pc.in branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/mztools.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/mztools.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/unzip.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/unzip.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/zip.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/minizip/zip.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/pascal/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/pascal/example.pas branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/pascal/readme.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/pascal/zlibd32.mak branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/pascal/zlibpas.pas branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/puff/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/puff/Makefile branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/puff/README branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/puff/puff.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/puff/puff.h branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/puff/pufftest.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/puff/zeros.raw branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/testzlib/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/testzlib/testzlib.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/testzlib/testzlib.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/untgz/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/untgz/Makefile branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/untgz/Makefile.msc branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/untgz/untgz.c branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/readme.txt branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/miniunz.vcxproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/miniunz.vcxproj.filters branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/miniunz.vcxproj.user branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/minizip.vcxproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/minizip.vcxproj.filters branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/minizip.vcxproj.user branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/testzlib.vcxproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/testzlib.vcxproj.filters branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/testzlib.vcxproj.user branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/testzlibdll.vcxproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/testzlibdll.vcxproj.filters branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/testzlibdll.vcxproj.user branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/zlib.rc branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/zlibstat.vcxproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/zlibstat.vcxproj.filters branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/zlibstat.vcxproj.user branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/zlibvc.def branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/zlibvc.sln branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/zlibvc.vcxproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/zlibvc.vcxproj.filters branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc10/zlibvc.vcxproj.user branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/ branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/miniunz.vcproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/minizip.vcproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/testzlib.vcproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/testzlibdll.vcproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/zlib.rc branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/zlibstat.vcproj branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/zlibvc.def branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/zlibvc.sln branches/Cog/processors/ARM/gdb-7.10/zlib/contrib/vstudio/vc9/zlibvc.vcproj branches/Cog/processors/ARM/gdb-7.10/zlib/crc32.c branches/Cog/processors/ARM/gdb-7.10/zlib/crc32.h branches/Cog/processors/ARM/gdb-7.10/zlib/deflate.c branches/Cog/processors/ARM/gdb-7.10/zlib/deflate.h branches/Cog/processors/ARM/gdb-7.10/zlib/doc/ branches/Cog/processors/ARM/gdb-7.10/zlib/doc/algorithm.txt branches/Cog/processors/ARM/gdb-7.10/zlib/doc/rfc1950.txt branches/Cog/processors/ARM/gdb-7.10/zlib/doc/rfc1951.txt branches/Cog/processors/ARM/gdb-7.10/zlib/doc/rfc1952.txt branches/Cog/processors/ARM/gdb-7.10/zlib/doc/txtvsbin.txt branches/Cog/processors/ARM/gdb-7.10/zlib/example.c branches/Cog/processors/ARM/gdb-7.10/zlib/examples/ branches/Cog/processors/ARM/gdb-7.10/zlib/examples/README.examples branches/Cog/processors/ARM/gdb-7.10/zlib/examples/enough.c branches/Cog/processors/ARM/gdb-7.10/zlib/examples/fitblk.c branches/Cog/processors/ARM/gdb-7.10/zlib/examples/gun.c branches/Cog/processors/ARM/gdb-7.10/zlib/examples/gzappend.c branches/Cog/processors/ARM/gdb-7.10/zlib/examples/gzjoin.c branches/Cog/processors/ARM/gdb-7.10/zlib/examples/gzlog.c branches/Cog/processors/ARM/gdb-7.10/zlib/examples/gzlog.h branches/Cog/processors/ARM/gdb-7.10/zlib/examples/zlib_how.html branches/Cog/processors/ARM/gdb-7.10/zlib/examples/zpipe.c branches/Cog/processors/ARM/gdb-7.10/zlib/examples/zran.c branches/Cog/processors/ARM/gdb-7.10/zlib/gzclose.c branches/Cog/processors/ARM/gdb-7.10/zlib/gzguts.h branches/Cog/processors/ARM/gdb-7.10/zlib/gzlib.c branches/Cog/processors/ARM/gdb-7.10/zlib/gzread.c branches/Cog/processors/ARM/gdb-7.10/zlib/gzwrite.c branches/Cog/processors/ARM/gdb-7.10/zlib/infback.c branches/Cog/processors/ARM/gdb-7.10/zlib/inffast.c branches/Cog/processors/ARM/gdb-7.10/zlib/inffast.h branches/Cog/processors/ARM/gdb-7.10/zlib/inffixed.h branches/Cog/processors/ARM/gdb-7.10/zlib/inflate.c branches/Cog/processors/ARM/gdb-7.10/zlib/inflate.h branches/Cog/processors/ARM/gdb-7.10/zlib/inftrees.c branches/Cog/processors/ARM/gdb-7.10/zlib/inftrees.h branches/Cog/processors/ARM/gdb-7.10/zlib/make_vms.com branches/Cog/processors/ARM/gdb-7.10/zlib/minigzip.c branches/Cog/processors/ARM/gdb-7.10/zlib/msdos/ branches/Cog/processors/ARM/gdb-7.10/zlib/msdos/Makefile.bor branches/Cog/processors/ARM/gdb-7.10/zlib/msdos/Makefile.dj2 branches/Cog/processors/ARM/gdb-7.10/zlib/msdos/Makefile.emx branches/Cog/processors/ARM/gdb-7.10/zlib/msdos/Makefile.msc branches/Cog/processors/ARM/gdb-7.10/zlib/msdos/Makefile.tc branches/Cog/processors/ARM/gdb-7.10/zlib/nintendods/ branches/Cog/processors/ARM/gdb-7.10/zlib/nintendods/Makefile branches/Cog/processors/ARM/gdb-7.10/zlib/nintendods/README branches/Cog/processors/ARM/gdb-7.10/zlib/old/ branches/Cog/processors/ARM/gdb-7.10/zlib/old/Makefile.emx branches/Cog/processors/ARM/gdb-7.10/zlib/old/Makefile.riscos branches/Cog/processors/ARM/gdb-7.10/zlib/old/README branches/Cog/processors/ARM/gdb-7.10/zlib/old/descrip.mms branches/Cog/processors/ARM/gdb-7.10/zlib/old/os2/ branches/Cog/processors/ARM/gdb-7.10/zlib/old/os2/Makefile.os2 branches/Cog/processors/ARM/gdb-7.10/zlib/old/os2/zlib.def branches/Cog/processors/ARM/gdb-7.10/zlib/old/visual-basic.txt branches/Cog/processors/ARM/gdb-7.10/zlib/qnx/ branches/Cog/processors/ARM/gdb-7.10/zlib/qnx/package.qpg branches/Cog/processors/ARM/gdb-7.10/zlib/test/ branches/Cog/processors/ARM/gdb-7.10/zlib/test/example.c branches/Cog/processors/ARM/gdb-7.10/zlib/test/infcover.c branches/Cog/processors/ARM/gdb-7.10/zlib/test/minigzip.c branches/Cog/processors/ARM/gdb-7.10/zlib/treebuild.xml branches/Cog/processors/ARM/gdb-7.10/zlib/trees.c branches/Cog/processors/ARM/gdb-7.10/zlib/trees.h branches/Cog/processors/ARM/gdb-7.10/zlib/uncompr.c branches/Cog/processors/ARM/gdb-7.10/zlib/watcom/ branches/Cog/processors/ARM/gdb-7.10/zlib/watcom/watcom_f.mak branches/Cog/processors/ARM/gdb-7.10/zlib/watcom/watcom_l.mak branches/Cog/processors/ARM/gdb-7.10/zlib/win32/ branches/Cog/processors/ARM/gdb-7.10/zlib/win32/DLL_FAQ.txt branches/Cog/processors/ARM/gdb-7.10/zlib/win32/Makefile.bor branches/Cog/processors/ARM/gdb-7.10/zlib/win32/Makefile.gcc branches/Cog/processors/ARM/gdb-7.10/zlib/win32/Makefile.msc branches/Cog/processors/ARM/gdb-7.10/zlib/win32/README-WIN32.txt branches/Cog/processors/ARM/gdb-7.10/zlib/win32/VisualC.txt branches/Cog/processors/ARM/gdb-7.10/zlib/win32/zlib.def branches/Cog/processors/ARM/gdb-7.10/zlib/win32/zlib1.rc branches/Cog/processors/ARM/gdb-7.10/zlib/zconf.h branches/Cog/processors/ARM/gdb-7.10/zlib/zconf.h.cmakein branches/Cog/processors/ARM/gdb-7.10/zlib/zconf.h.in branches/Cog/processors/ARM/gdb-7.10/zlib/zlib.3 branches/Cog/processors/ARM/gdb-7.10/zlib/zlib.h branches/Cog/processors/ARM/gdb-7.10/zlib/zlib.map branches/Cog/processors/ARM/gdb-7.10/zlib/zlib.pc.cmakein branches/Cog/processors/ARM/gdb-7.10/zlib/zlib.pc.in branches/Cog/processors/ARM/gdb-7.10/zlib/zlib2ansi branches/Cog/processors/ARM/gdb-7.10/zlib/zutil.c branches/Cog/processors/ARM/gdb-7.10/zlib/zutil.h Property changes on: branches/Cog/build.macos32x86/gdbarm32 ___________________________________________________________________ Added: svn:ignore + bfd libiberty opcodes sim zlib Added: branches/Cog/build.macos32x86/gdbarm32/conf.COG =================================================================== --- branches/Cog/build.macos32x86/gdbarm32/conf.COG (rev 0) +++ branches/Cog/build.macos32x86/gdbarm32/conf.COG 2015-11-11 22:48:34 UTC (rev 3491) @@ -0,0 +1,17 @@ +#!/bin/sh +mkdir -p zlib bfd libiberty opcodes sim/common sim/arm +for d in zlib; do + (cd $d; ../../../processors/ARM/gdb-7.10/$d/configure) +done +for d in bfd; do + (cd $d; ../../../processors/ARM/gdb-7.10/$d/configure \ + --target=arm-linux --with-system-zlib=no) +done +for d in libiberty opcodes; do + (cd $d; ../../../processors/ARM/gdb-7.10/$d/configure \ + --target=arm-linux) +done +for d in sim/common sim/arm; do + (cd $d; ../../../../processors/ARM/gdb-7.10/$d/configure \ + --target=arm-linux) +done Property changes on: branches/Cog/build.macos32x86/gdbarm32/conf.COG ___________________________________________________________________ Added: svn:executable + * Added: branches/Cog/build.macos32x86/gdbarm32/makeem =================================================================== --- branches/Cog/build.macos32x86/gdbarm32/makeem (rev 0) +++ branches/Cog/build.macos32x86/gdbarm32/makeem 2015-11-11 22:48:34 UTC (rev 3491) @@ -0,0 +1,4 @@ +#!/bin/sh +for d in zlib bfd libiberty opcodes sim/arm; do + (cd $d; make COG=1) +done Property changes on: branches/Cog/build.macos32x86/gdbarm32/makeem ___________________________________________________________________ Added: svn:executable + * Modified: branches/Cog/processors/ARM/README =================================================================== --- branches/Cog/processors/ARM/README 2015-11-11 18:04:09 UTC (rev 3490) +++ branches/Cog/processors/ARM/README 2015-11-11 22:48:34 UTC (rev 3491) @@ -8,19 +8,32 @@ Ubuntu configuration for binutils and libiberty sudo apt-get install binutils-dev libiberty-dev -The gdb-7.6 here is a subtly modified version of, um, gdb-7.6. +The gdb-7.10 here is a subtly modified version of, um, gdb-7.10. Then -cd gdb-7.6/opcodes # i.e. processors/ARM/gdb-7.6/opcodes +cd gdb-7.10/zib # i.e. processors/ARM/gdb-7.10/zlib +./configure +make COG=1 + +cd gdb-7.10/bfd # i.e. processors/ARM/gdb-7.10/bfd +./configure --target=arm-linux --with-system-zlib=no +make COG=1 + +cd gdb-7.10/libiberty # i.e. processors/ARM/gdb-7.10/libiberty ./configure --target=arm-linux -make +make COG=1 -cd ../sim/common # i.e. processors/ARM/gdb-7.6/sim/common +cd gdb-7.10/opcodes # i.e. processors/ARM/gdb-7.10/opcodes ./configure --target=arm-linux -cd ../arm # i.e. processors/ARM/gdb-7.6/sim/arm +make COG=1 + +cd ../sim/common # i.e. processors/ARM/gdb-7.10/sim/common ./configure --target=arm-linux -make -That should produce processors/ARM/gdb-7.6/sim/arm/libsim.a +cd ../arm # i.e. processors/ARM/gdb-7.10/sim/arm +./configure --target=arm-linux +make COG=1 + +That should produce processors/ARM/gdb-7.10/sim/arm/libsim.a With that built you can configure and build VMs that will build the ARM plugin. Added: branches/Cog/processors/ARM/TODO =================================================================== --- branches/Cog/processors/ARM/TODO (rev 0) +++ branches/Cog/processors/ARM/TODO 2015-11-11 22:48:34 UTC (rev 3491) @@ -0,0 +1,194 @@ +Files modified for Cog: + +opcodes/libtool -- added file? + +README -- added notes on the cut-down distribution + +sim/arm/armemu.c + -- notes that file has been modified +*************** +*** 592,606 **** + NORMALCYCLE; + break; + } +- // END OF SWITCH stmt, where the above breaks go +- +- // TPR - save the pc to help in CogVM sim error handling, IFF the instr is not an abort SWI +- if ( instr != (0xEF000000 | SWI_CogPrefetch)) { +- state->temp = pc; +- } + +! if (state->EventSet) +! ARMul_EnvokeEvent (state); + #if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */ + fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr); + if (instr == 0) +--- 576,584 ---- + NORMALCYCLE; + break; + } + +! if (state->EventSet) +! ARMul_EnvokeEvent (state); + #if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */ + fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr); + if (instr == 0) + + +sim/arm/armos.c +*************** +*** 453,471 **** + + switch (number) + { +- case SWI_CogPrefetch: +- // TPR - This is the SWI number which is returned by our memory interface +- // if there is an instruction fetch for an illegal address. +- // this #define stolen from GdbARMPlugin.h and ought to be done better +- # define InstructionPrefetchError 5 +- state->Emulate = STOP; +- state->EndCondition = InstructionPrefetchError; +- +- // during execution, the pc points the next fetch address, which is 8 byte after the current instruction. +- gdb_log_printf(NULL, "Illegal Instruction fetch address (%#p).", state->Reg[15]-8); +- return TRUE; // escape immediately +- break; +- + case SWI_Read: + if (swi_mask & SWI_MASK_DEMON) + SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]); +--- 453,458 ---- + +sim/arm/armos.h +*************** +*** 25,34 **** + + /* SWI numbers. */ + +- /* Add prefetch error for Cog usage of this simulator, hacked up though it may be +- It isn't a real SWI but (ab)uses the mechanism to do it's eeeeeevil work */ +- #define SWI_CogPrefetch 0x42 /* because why wouldn't we? */ +- + #define SWI_WriteC 0x0 + #define SWI_Write0 0x2 + #define SWI_ReadC 0x4 +--- 25,30 ---- + + +sim/arm/armulmem.c added file? + +sim/arm/gentmap added file? + +sim/arm/libtool added file? + +sim/arm/Makefile.in +*************** +*** 21,29 **** + + COPRO=@COPRO@ + +- # tim(a)rowledge.org - exchange armvirt.o for armulmem.o for Cog support + SIM_OBJS = armemu26.o armemu32.o arminit.o armos.o armsupp.o \ +! armulmem.o bag.o thumbemu.o wrapper.o sim-load.o $(COPRO) + + ## COMMON_POST_CONFIG_FRAG + +--- 21,28 ---- + + COPRO=@COPRO@ + + SIM_OBJS = armemu26.o armemu32.o arminit.o armos.o armsupp.o \ +! armvirt.o bag.o thumbemu.o wrapper.o sim-load.o $(COPRO) + + ## COMMON_POST_CONFIG_FRAG + +sim/arm/stamp-h added file? +sim/arm/stamp-tvals added file? +sim/arm/targ-map.c added file? +sim/arm/targ-vals.h added file? + +sim/arm/thumbemu.c +*************** +*** 102,114 **** + tdstate valid = t_decoded; /* default assumes a valid instruction */ + ARMword next_instr; + +- // tpr - catch our special SWI and effectively skip over thumb nonsense +- if (tinstr == 0xEF200000) { +- // that's us - hate using magic numbers but that's life +- *ainstr = tinstr; +- return valid; +- } +- + if (state->bigendSig) + { + next_instr = tinstr & 0xFFFF; +--- 102,107 ---- + +sim/arm/version.c added file? + +sim/common/Make-common.in +*************** +*** 272,279 **** + callback_h = $(srcroot)/include/gdb/callback.h + remote_sim_h = $(srcroot)/include/gdb/remote-sim.h + +! all: $(SIM_EXTRA_ALL) libsim.a +! # reomved by tpr for squeak gdbarmplugin stuff run$(EXEEXT) .gdbinit + + libsim.a: $(LIB_OBJS) + rm -f libsim.a +--- 272,278 ---- + callback_h = $(srcroot)/include/gdb/callback.h + remote_sim_h = $(srcroot)/include/gdb/remote-sim.h + +! all: $(SIM_EXTRA_ALL) libsim.a run$(EXEEXT) .gdbinit + + libsim.a: $(LIB_OBJS) + rm -f libsim.a +*************** +*** 301,310 **** + $(SHELL) $(srcroot)/move-if-change tmp-tmap.c targ-map.c + touch stamp-tvals + +! #version.c: Makefile + rm -f version.c-tmp version.c + echo '#include "version.h"' >> version.c-tmp +! echo 'const char version[] = "'"7.6"'";' >> version.c-tmp + mv version.c-tmp version.c + + +--- 300,309 ---- + $(SHELL) $(srcroot)/move-if-change tmp-tmap.c targ-map.c + touch stamp-tvals + +! version.c: Makefile ../../gdb/version.in + rm -f version.c-tmp version.c + echo '#include "version.h"' >> version.c-tmp +! echo 'const char version[] = "'"`sed q ${srcdir}/../../gdb/version.in`"'";' >> version.c-tmp + mv version.c-tmp version.c + + +*************** +*** 436,445 **** + $(SIM_EXTRA_DEPS) \ + hw-config.h \ + targ-map.c \ +! targ-vals.h +! # \ +! # version.c +! # removed by tpr for Squeak gdbarmplugin stuff + + # Ensure that generated files are created early. Use order-only + # dependencies if available. They require GNU make 3.80 or newer, +--- 435,442 ---- + $(SIM_EXTRA_DEPS) \ + hw-config.h \ + targ-map.c \ +! targ-vals.h \ +! version.c + + # Ensure that generated files are created early. Use order-only + # dependencies if available. They require GNU make 3.80 or newer, + + Added: branches/Cog/processors/ARM/gdb-7.10/COPYING =================================================================== --- branches/Cog/processors/ARM/gdb-7.10/COPYING (rev 0) +++ branches/Cog/processors/ARM/gdb-7.10/COPYING 2015-11-11 22:48:34 UTC (rev 3491) @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Program, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. (This alternative is + allowed only for noncommercial distribution and only if you + received the program in object code or executable form with such + an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for +making modifications to it. For an executable work, complete source +code means all the source code for all modules it contains, plus any +associated interface definition files, plus the scripts used to +control compilation and installation of the executable. However, as a +special exception, the source code distributed need not include +anything that is normally distributed (in either source or binary +form) with the major components (compiler, kernel, and so on) of the +operating system on which the executable runs, unless that component +itself accompanies the executable. + +If distribution of executable or object code is made by offering +access to copy from a designated place, then offering equivalent +access to copy the source code from the same place counts as +distribution of the source code, even though third parties are not +compelled to copy the source along with the object code. + + 4. You may not copy, modify, sublicense, or distribute the Program +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 8. If the distribution and/or use of the Program is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Program under this License +may add an explicit geographical distribution limitation excluding +those countries, so that distribution is permitted only in or among +countries not thus excluded. In such case, this License incorporates +the limitation as if written in the body of this License. + + 9. The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + <one line to give the program's name and a brief idea of what it does.> + Copyright (C) <year> <name of author> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. Added: branches/Cog/processors/ARM/gdb-7.10/COPYING.LIB =================================================================== --- branches/Cog/processors/ARM/gdb-7.10/COPYING.LIB (rev 0) +++ branches/Cog/processors/ARM/gdb-7.10/COPYING.LIB 2015-11-11 22:48:34 UTC (rev 3491) @@ -0,0 +1,482 @@ + GNU LIBRARY GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1991 Free Software Foundation, Inc. + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + +[This is the first released version of the library GPL. It is + numbered 2 because it goes with version 2 of the ordinary GPL.] + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +Licenses are intended to guarantee your freedom to share and change +free software--to make sure the software is free for all its users. + + This license, the Library General Public License, applies to some +specially designated Free Software Foundation software, and to any +other libraries whose authors decide to use it. You can use it for +your libraries, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if +you distribute copies of the library, or if you modify it. + + For example, if you distribute copies of the library, whether gratis +or for a fee, you must give the recipients all the rights that we gave +you. You must make sure that they, too, receive or can get the source +code. If you link a program with the library, you must provide +complete object files to the recipients so that they can relink them +with the library, after making changes to the library and recompiling +it. And you must show them these terms so they know their rights. + + Our method of protecting your rights has two steps: (1) copyright +the library, and (2) offer you this license which gives you legal +permission to copy, distribute and/or modify the library. + + Also, for each distributor's protection, we want to make certain +that everyone understands that there is no warranty for this free +library. If the library is modified by someone else and passed on, we +want its recipients to know that what they have is not the original +version, so that any problems introduced by others will not reflect on +the original authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that companies distributing free +software will individually obtain patent licenses, thus in effect +transforming the program into proprietary software. To prevent this, +we have made it clear that any patent must be licensed for everyone's +free use or not licensed at all. + + Most GNU software, including some libraries, is covered by the ordinary +GNU General Public License, which was designed for utility programs. This +license, the GNU Library General Public License, applies to certain +designated libraries. This license is quite different from the ordinary +one; be sure to read it in full, and don't assume that anything in it is +the same as in the ordinary license. + + The reason we have a separate public license for some libraries is that +they blur the distinction we usually make between modifying or adding to a +program and simply using it. Linking a program with a library, without +changing the library, is in some sense simply using the library, and is +analogous to running a utility program or application program. However, in +a textual and legal sense, the linked executable is a combined work, a +derivative of the original library, and the ordinary General Public License +treats it as such. + + Because of this blurred distinction, using the ordinary General +Public License for libraries did not effectively promote software +sharing, because most developers did not use the libraries. We +concluded that weaker conditions might promote sharing better. + + However, unrestricted linking of non-free programs would deprive the +users of those programs of all benefit from the free status of the +libraries themselves. This Library General Public License is intended to +permit developers of non-free programs to use free libraries, while +preserving your freedom as a user of such programs to change the free +libraries that are incorporated in them. (We have not seen how to achieve +this as regards changes in header files, but we have achieved it as regards +changes in the actual functions of the Library.) The hope is that this +will lead to faster development of free libraries. + + The precise terms and conditions for copying, distribution and +modification follow. Pay close attention to the difference between a +"work based on the library" and a "work that uses the library". The +former contains code derived from the library, while the latter only +works together with the library. + + Note that it is possible for a library to be covered by the ordinary +General Public License rather than by this special one. + + GNU LIBRARY GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License Agreement applies to any software library which +contains a notice placed by the copyright holder or other authorized +party saying it may be distributed under the terms of this Library +General Public License (also called "this License"). Each licensee is +addressed as "you". + + A "library" means a collection of software functions and/or data +prepared so as to be conveniently linked with application programs +(which use some of those functions and data) to form executables. + + The "Library", below, refers to any such software library or work +which has been distributed under these terms. A "work based on the +Library" means either the Library or any derivative work under +copyright law: that is to say, a work containing the Library or a +portion of it, either verbatim or with modifications and/or translated +straightforwardly into another language. (Hereinafter, translation is +included without limitation in the term "modification".) + + "Source code" for a work means the preferred form of the work for +making modifications to it. For a library, complete source code means +all the source code for all modules it contains, plus any associated +interface definition files, plus the scripts used to control compilation +and installation of the library. + + Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running a program using the Library is not restricted, and output from +such a program is covered only if its contents constitute a work based +on the Library (independent of the use of the Library in a tool for +writing it). Whether that is true depends on what the Library does +and what the program that uses the Library does. + + 1. You may copy and distribute verbatim copies of the Library's +complete source code as you receive it, in any medium, provided that +you conspicuously and appropriately publish on each copy an +appropriate copyright notice and disclaimer of warranty; keep intact +all the notices that refer to this License and to the absence of any +warranty; and distribute a copy of this License along with the +Library. + + You may charge a fee for the physical act of transferring a copy, +and you may at your option offer warranty protection in exchange for a +fee. + + 2. You may modify your copy or copies of the Library or any portion +of it, thus forming a work based on the Library, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) The modified work must itself be a software library. + + b) You must cause the files modified to carry prominent notices + stating that you changed the files and the date of any change. + + c) You must cause the whole of the work to be licensed at no + charge to all third parties under the terms of this License. + + d) If a facility in the modified Library refers to a function or a + table of data to be supplied by an application program that uses + the facility, other than as an argument passed when the facility + is invoked, then you must make a good faith effort to ensure that, + in the event an application does not supply such function or + table, the facility still operates, and performs whatever part of + its purpose remains meaningful. + + (For example, a function in a library to compute square roots has + a purpose that is entirely well-defined independent of the + application. Therefore, Subsection 2d requires that any + application-supplied function or table used by this function must + be optional: if the application does not supply it, the square + root function must still compute square roots.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Library, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Library, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote +it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Library. + +In addition, mere aggregation of another work not based on the Library +with the Library (or with a work based on the Library) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may opt to apply the terms of the ordinary GNU General Public +License instead of this License to a given copy of the Library. To do +this, you must alter all the notices that refer to this License, so +that they refer to the ordinary GNU General Public License, version 2, +instead of to this License. (If a newer version than version 2 of the +ordinary GNU General Public License has appeared, then you can specify +that version instead if you wish.) Do not make any other change in +these notices. + + Once this change is made in a given copy, it is irreversible for +that copy, so the ordinary GNU General Public License applies to all +subsequent copies and derivative works made from that copy. + + This option is useful when you wish to copy part of the code of +the Library into a program that is not a library. + + 4. You may copy and distribute the Library (or a portion or +derivative of it, under Section 2) in object code or executable form +under the terms of Sections 1 and 2 above provided that you accompany +it with the complete corresponding machine-readable source code, which +must be distributed under the terms of Sections 1 and 2 above on a +medium customarily used for software interchange. + + If distribution of object code is made by offering access to copy +from a designated place, then offering equivalent access to copy the +source code from the same place satisfies the requirement to +distribute the source code, even though third parties are not +compelled to copy the source along with the object code. + + 5. A program that contains no derivative of any portion of the +Library, but is designed to work with the Library by being compiled or +linked with it, is called a "work that uses the Library". Such a +work, in isolation, is not a derivative work of the Library, and +therefore falls outside the scope of this License. + + However, linking a "work that uses the Library" with the Library +creates an executable that is a derivative of the Library (because it +contains portions of the Library), rather than a "work that uses the +library". The executable is therefore covered by this License. +Section 6 states terms for distribution of such executables. + + When a "work that uses the Library" uses material from a header file +that is part of the Library, the object code for the work may be a +derivative work of the Library even though the source code is not. +Whether this is true is especially significant if the work can be +linked without the Library, or if the work is itself a library. The +threshold for this to be true is not precisely defined by law. + + If such an object file uses only numerical parameters, data +structure layouts and accessors, and small macros and small inline +functions (ten lines or less in length), then the use of the object +file is unrestricted, regardless of whether it is legally a derivative +work. (Executables containing this object code plus portions of the +Library will still fall under Section 6.) + + Otherwise, if the work is a derivative of the Library, you may +distribute the object code for the work under the terms of Section 6. +Any executables containing that work also fall under Section 6, +whether or not they are linked directly with the Library itself. + + 6. As an exception to the Sections above, you may also compile or +link a "work that uses the Library" with the Library to produce a +work containing portions of the Library, and distribute that work +under terms of your choice, provided that the terms permit +modification of the work for the customer's own use and reverse +engineering for debugging such modifications. + + You must give prominent notice with each copy of the work that the +Library is used in it and that the Library and its use are covered by +this License. You must supply a copy of this License. If the work +during execution displays copyright notices, you must include the +copyright notice for the Library among them, as well as a reference +directing the user to the copy of this License. Also, you must do one +of these things: + + a) Accompany the work with the complete corresponding + machine-readable source code for the Library including whatever + changes were used in the work (which must be distributed under + Sections 1 and 2 above); and, if the work is an executable linked + with the Library, with the complete machine-readable "work that + uses the Library", as object code and/or source code, so that the + user can modify the Library and then relink to produce a modified + executable containing the modified Library. (It is understood + that the user who changes the contents of definitions files in the + Library will not necessarily be able to recompile the application + to use the modified definitions.) + + b) Accompany the work with a written offer, valid for at + least three years, to give the same user the materials + specified in Subsection 6a, above, for a charge no more + than the cost of performing this distribution. + + c) If distribution of the work is made by offering access to copy + from a designated place, offer equivalent access to copy the above + specified materials from the same place. + + d) Verify that the user has already received a copy of these + materials or that you have already sent this user a copy. + + For an executable, the required form of the "work that uses the +Library" must include any data and utility programs needed for +reproducing the executable from it. However, as a special exception, +the source code distributed need not include anything that is normally +distributed (in either source or binary form) with the major +components (compiler, kernel, and so on) of the operating system on +which the executable runs, unless that component itself accompanies +the executable. + + It may happen that this requirement contradicts the license +restrictions of other proprietary libraries that do not normally +accompany the operating system. Such a contradiction means you cannot +use both them and the Library together in an executable that you +distribute. + + 7. You may place library facilities that are a work based on the +Library side-by-side in a single library together with other library +facilities not covered by this License, and distribute such a combined +library, provided that the separate distribution of the work based on +the Library and of the other library facilities is otherwise +permitted, and provided that you do these two things: + + a) Accompany the combined library with a copy of the same work + based on the Library, uncombined with any other library + facilities. This must be distributed under the terms of the + Sections above. + + b) Give prominent notice with the combined library of the fact + that part of it is a work based on the Library, and explaining + where to find the accompanying uncombined form of the same work. + + 8. You may not copy, modify, sublicense, link with, or distribute +the Library except as expressly provided under this License. Any +attempt otherwise to copy, modify, sublicense, link with, or +distribute the Library is void, and will automatically terminate your +rights under this License. However, parties who have received copies, +or rights, from you under this License will not have their licenses +terminated so long as such parties remain in full compliance. + + 9. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Library or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Library (or any work based on the +Library), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Library or works based on it. + + 10. Each time you redistribute the Library (or any work based on the +Library), the recipient automatically receives a license from the +original licensor to copy, distribute, link with or modify the Library +subject to these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 11. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Library at all. For example, if a patent +license would not permit royalty-free redistribution of the Library by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Library. + +If any portion of this section is held invalid or unenforceable under any +particular circumstance, the balance of the section is intended to apply, +and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 12. If the distribution and/or use of the Library is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Library under this License may add +an explicit geographical distribution limitation excluding those countries, +so that distribution is permitted only in or among countries not thus +excluded. In such case, this License incorporates the limitation as if +written in the body of this License. + + 13. The Free Software Foundation may publish revised and/or new +versions of the Library General Public License from time to time. +Such new versions will be similar in spirit to the present version, +but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Library +specifies a version number of this License which applies to it and +"any later version", you have the option of following the terms and +conditions either of that version or of any later version published by +the Free Software Foundation. If the Library does not specify a +license version number, you may choose any version ever published by +the Free Software Foundation. + + 14. If you wish to incorporate parts of the Library into other free +programs whose distribution conditions are incompatible with these, +write to the author to ask for permission. For software which is +copyrighted by the Free Software Foundation, write to the Free +Software Foundation; we sometimes make exceptions for this. Our +decision will be guided by the two goals of preserving the free status +of all derivatives of our free software and of promoting the sharing +and reuse of software generally. + + NO WARRANTY + + 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO +WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW. +EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR +OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY +KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE +LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME +THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + + 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN @@ Diff output truncated at 50000 characters. @@

1 0

VM Maker: VMMaker.oscog-tpr.1513.mcz
by commits＠source.squeak.org 11 Nov '15

11 Nov '15

tim Rowledge uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1513.mcz ==================== Summary ==================== Name: VMMaker.oscog-tpr.1513 Author: tpr Time: 11 November 2015, 11:33:12.233 am UUID: 6ff3cfa5-df00-4848-96ba-589d9ddeb05b Ancestors: VMMaker.oscog-rmacnak.1512 Fix a couple of CPIC bugs and commetns. =============== Diff against VMMaker.oscog-rmacnak.1512 =============== Item was changed: ----- Method: CogARMCompiler>>callTargetFromReturnAddress: (in category 'inline cacheing') ----- callTargetFromReturnAddress: callSiteReturnAddress "Answer the address that the call immediately preceding callSiteReturnAddress will jump to." "this is also used by #jumpLongTargetBeforeFollowingAddress:." | callDistance call | call := self instructionBeforeAddress: callSiteReturnAddress. self assert: ((self instructionIsB: call) or: [self instructionIsBL: call]). callDistance := self extractOffsetFromBL: call. + "this is the pc's +8 offset, - the 4 byte correction for the previous instruction address" + ^callSiteReturnAddress + 4 + callDistance signedIntFromLong! - ^callSiteReturnAddress + 4 "this is the pc's +8 offset, - the 4 byte correction for the previous instruction address" + callDistance signedIntFromLong! Item was removed: - ----- Method: CogARMCompiler>>loadLiteralByteSize (in category 'accessing') ----- - loadLiteralByteSize - "Answer the byte size of a MoveCwR opcode's corresponding machine code. On ARM this is a single instruction pc-relative register load - unless we have made a mistake and not turned on the out of line literals manager" - ^4! Item was added: + ----- Method: CogInLineLiteralsARMCompiler>>loadLiteralByteSize (in category 'accessing') ----- + loadLiteralByteSize + "Answer the byte size of a MoveCwR opcode's corresponding machine code. On ARM this is a single instruction pc-relative register load - unless we have made a mistake and not turned on the out of line literals manager" + ^16! Item was added: + ----- Method: CogOutOfLineLiteralsARMCompiler>>loadLiteralByteSize (in category 'accessing') ----- + loadLiteralByteSize + "Answer the byte size of a MoveCwR opcode's corresponding machine code. On ARM this is a single instruction pc-relative register load - unless we have made a mistake and not turned on the out of line literals manager" + ^4! Item was changed: ----- Method: Cogit>>addressOfEndOfCase:inCPIC: (in category 'in-line cacheing') ----- addressOfEndOfCase: n inCPIC: cPIC "calculate the end of the n'th case statement - which is complicated because we have case 1 right at the top of our CPIC and then build up from the last one. Yes I know this sounds strange, but trust me - I'm an Engineer, we do things backwards all the emit" <var: #cPIC type: #'CogMethod *'> self assert: (n >= 1and: [n <= maxCPICCases]). + ^n = 1 + ifTrue: [cPIC asInteger + firstCPICCaseOffset] + ifFalse: [cPIC asInteger + firstCPICCaseOffset + (maxCPICCases + 1 - n * cPICCaseSize)]! - n = 1 - ifTrue: [^ cPIC asInteger + firstCPICCaseOffset] - ifFalse: [^ cPIC asInteger + firstCPICCaseOffset + (maxCPICCases + 1 - n * cPICCaseSize)]! Item was changed: ----- Method: Cogit>>cPIC:HasTarget: (in category 'in-line cacheing') ----- cPIC: cPIC HasTarget: targetMethod "Are any of the jumps from this CPIC to targetMethod?" <var: #cPIC type: #'CogMethod *'> <var: #targetMethod type: #'CogMethod *'> | pc target | target := targetMethod asUnsignedInteger + cmNoCheckEntryOffset. pc := cPIC asInteger + firstCPICCaseOffset. "Since this is a fast test doing simple compares we don't need to care that some cases have nonsense addresses in there. Just zip on through" + 1 to: maxCPICCases do: - 1 to: cPIC cPICNumCases do: [:i| target = (backEnd jumpLongTargetBeforeFollowingAddress: pc) ifTrue: [^true]. pc := pc + cPICCaseSize]. ^false!

1 0

[commit][3490] Add svn:ignore for user state to all xcode projects that don 't yet have them.
by commits＠squeakvm.org 11 Nov '15

11 Nov '15

Revision: 3490 Author: eliot Date: 2015-11-11 10:04:09 -0800 (Wed, 11 Nov 2015) Log Message: ----------- Add svn:ignore for user state to all xcode projects that don't yet have them. Add a 64-bit xcode template. Modified Paths: -------------- branches/Cog/build.macos32x86/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.pbxproj Added Paths: ----------- branches/Cog/build.macos64x64/xcode/CocoaTemplate/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/AppDelegate.h branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/AppDelegate.m branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/Base.lproj/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/Base.lproj/MainMenu.xib branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/Images.xcassets/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/Images.xcassets/AppIcon.appiconset/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/Images.xcassets/AppIcon.appiconset/Contents.json branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/Info.plist branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/main.m branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/eliot.mode1v3 branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/eliot.pbxuser branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.pbxproj branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.xcworkspace/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.xcworkspace/contents.xcworkspacedata branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.xcworkspace/xcuserdata/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.xcworkspace/xcuserdata/eliot.xcuserdatad/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.xcworkspace/xcuserdata/eliot.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/xcuserdata/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplateTests/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplateTests/CocoaTemplateTests.m branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplateTests/Info.plist branches/Cog/build.macos64x64/xcode/CocoaTemplate/DOIT branches/Cog/build.macos64x64/xcode/CocoaTemplate/README branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/categories.pbxbtree branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/cdecls.pbxbtree branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/decls.pbxbtree branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/files.pbxbtree branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/imports.pbxbtree branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/pbxindex.header branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/protocols.pbxbtree branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/refs.pbxbtree branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/strings.pbxstrings/ branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/strings.pbxstrings/control branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/strings.pbxstrings/strings branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/subclasses.pbxbtree branches/Cog/build.macos64x64/xcode/CocoaTemplate/build/CocoaTemplate.build/CocoaTemplate.pbxindex/symbols0.pbxsymbols Property Changed: ---------------- branches/Cog/build.macos32x86/squeak.cog.spur/BochsIA32Plugin/BochsIA32Plugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.cog.spur/BochsX64Plugin/BochsX64Plugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.cog.spur/CroquetPlugin/CroquetPlugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.cog.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/ branches/Cog/build.macos32x86/squeak.cog.v3/BochsIA32Plugin/BochsIA32Plugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.cog.v3/CroquetPlugin/CroquetPlugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.cog.v3/FloatArrayPlugin/FloatArrayPlugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.sista.spur/BochsIA32Plugin/BochsIA32Plugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.sista.spur/CroquetPlugin/CroquetPlugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.sista.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.stack.spur/CroquetPlugin/CroquetPlugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.stack.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.stack.v3/CroquetPlugin/CroquetPlugin.xcodeproj/ branches/Cog/build.macos32x86/squeak.stack.v3/FloatArrayPlugin/FloatArrayPlugin.xcodeproj/ branches/Cog/build.macos32x86/xcode/CarbonTemplate/Template.xcodeproj/ branches/Cog/build.macos32x86/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/ branches/Cog/build.macos64x64/newspeak.cog.spur/CoreVM.xcodeproj/ branches/Cog/build.macos64x64/newspeak.cog.spur/SqueakSSL/SqueakSSL.xcodeproj/ branches/Cog/build.macos64x64/newspeak.cog.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj/ branches/Cog/build.macos64x64/newspeak.stack.spur/CoreVM.xcodeproj/ branches/Cog/build.macos64x64/newspeak.stack.spur/SqueakSSL/SqueakSSL.xcodeproj/ branches/Cog/build.macos64x64/newspeak.stack.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/BochsIA32Plugin/BochsIA32Plugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/CoreMTVM.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/CoreVM.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/CroquetPlugin/CroquetPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/FloatMathPlugin/FloatMathPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/SqueakFFIPrims/SqueakFFI.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/SqueakMTFFIPrims/SqueakFFI.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/SqueakSSL/SqueakSSL.xcodeproj/ branches/Cog/build.macos64x64/squeak.cog.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.sista.spur/CoreVM.xcodeproj/ branches/Cog/build.macos64x64/squeak.sista.spur/CroquetPlugin/CroquetPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.sista.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.sista.spur/FloatMathPlugin/FloatMathPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.sista.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.sista.spur/SqueakFFIPrims/SqueakFFI.xcodeproj/ branches/Cog/build.macos64x64/squeak.sista.spur/SqueakSSL/SqueakSSL.xcodeproj/ branches/Cog/build.macos64x64/squeak.sista.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.stack.spur/CroquetPlugin/CroquetPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.stack.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.stack.spur/FloatMathPlugin/FloatMathPlugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.stack.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/ branches/Cog/build.macos64x64/squeak.stack.spur/SqueakFFIPrims/SqueakFFI.xcodeproj/ branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj/ branches/Cog/build.macos64x64/squeak.stack.spur/SqueakSSL/SqueakSSL.xcodeproj/ branches/Cog/build.macos64x64/squeak.stack.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj/ branches/Cog/build.macos64x64/xcode/Template/Template.xcodeproj/ Property changes on: branches/Cog/build.macos32x86/squeak.cog.spur/BochsIA32Plugin/BochsIA32Plugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.cog.spur/BochsX64Plugin/BochsX64Plugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.cog.spur/CroquetPlugin/CroquetPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.cog.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.cog.v3/BochsIA32Plugin/BochsIA32Plugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.cog.v3/CroquetPlugin/CroquetPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.cog.v3/FloatArrayPlugin/FloatArrayPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.sista.spur/BochsIA32Plugin/BochsIA32Plugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.sista.spur/CroquetPlugin/CroquetPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.sista.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.stack.spur/CroquetPlugin/CroquetPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.stack.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.stack.v3/CroquetPlugin/CroquetPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/squeak.stack.v3/FloatArrayPlugin/FloatArrayPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/xcode/CarbonTemplate/Template.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos32x86/xcode/CocoaTemplate/CocoaTemplate.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Modified: branches/Cog/build.macos32x86/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.pbxproj =================================================================== --- branches/Cog/build.macos32x86/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.pbxproj 2015-11-11 02:07:54 UTC (rev 3489) +++ branches/Cog/build.macos32x86/xcode/CocoaTemplate/CocoaTemplate.xcodeproj/project.pbxproj 2015-11-11 18:04:09 UTC (rev 3490) @@ -254,7 +254,7 @@ CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; CLANG_CXX_LIBRARY = "libc++"; CLANG_ENABLE_MODULES = YES; - CLANG_ENABLE_OBJC_ARC = YES; + CLANG_ENABLE_OBJC_ARC = NO; CLANG_WARN_BOOL_CONVERSION = YES; CLANG_WARN_CONSTANT_CONVERSION = YES; CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; @@ -334,7 +334,7 @@ CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; CLANG_CXX_LIBRARY = "libc++"; CLANG_ENABLE_MODULES = YES; - CLANG_ENABLE_OBJC_ARC = YES; + CLANG_ENABLE_OBJC_ARC = NO; CLANG_WARN_BOOL_CONVERSION = YES; CLANG_WARN_CONSTANT_CONVERSION = YES; CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; @@ -378,7 +378,7 @@ CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; CLANG_CXX_LIBRARY = "libc++"; CLANG_ENABLE_MODULES = YES; - CLANG_ENABLE_OBJC_ARC = YES; + CLANG_ENABLE_OBJC_ARC = NO; CLANG_WARN_BOOL_CONVERSION = YES; CLANG_WARN_CONSTANT_CONVERSION = YES; CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; Property changes on: branches/Cog/build.macos64x64/newspeak.cog.spur/CoreVM.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/newspeak.cog.spur/SqueakSSL/SqueakSSL.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/newspeak.cog.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/newspeak.stack.spur/CoreVM.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/newspeak.stack.spur/SqueakSSL/SqueakSSL.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/newspeak.stack.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/BochsIA32Plugin/BochsIA32Plugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/CoreMTVM.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/CoreVM.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/CroquetPlugin/CroquetPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/FloatMathPlugin/FloatMathPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/SqueakFFIPrims/SqueakFFI.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/SqueakMTFFIPrims/SqueakFFI.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/SqueakSSL/SqueakSSL.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.cog.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.sista.spur/CoreVM.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.sista.spur/CroquetPlugin/CroquetPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.sista.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.sista.spur/FloatMathPlugin/FloatMathPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.sista.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.sista.spur/SqueakFFIPrims/SqueakFFI.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.sista.spur/SqueakSSL/SqueakSSL.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.sista.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.stack.spur/CroquetPlugin/CroquetPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.stack.spur/FloatArrayPlugin/FloatArrayPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.stack.spur/FloatMathPlugin/FloatMathPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.stack.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.stack.spur/SqueakFFIPrims/SqueakFFI.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.stack.spur/SqueakSSL/SqueakSSL.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Property changes on: branches/Cog/build.macos64x64/squeak.stack.spur/UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj ___________________________________________________________________ Added: svn:ignore + *.pbxuser *.mode1v3 Added: branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/AppDelegate.h =================================================================== --- branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/AppDelegate.h (rev 0) +++ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/AppDelegate.h 2015-11-11 18:04:09 UTC (rev 3490) @@ -0,0 +1,15 @@ +// +// AppDelegate.h +// CocoaTemplate +// +// Created by Eliot Miranda on 09/11/2015. +// Copyright (c) 2015 Cog VM. All rights reserved. +// + +#import <Cocoa/Cocoa.h> + +@interface AppDelegate : NSObject <NSApplicationDelegate> + + +@end + Added: branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/AppDelegate.m =================================================================== --- branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/AppDelegate.m (rev 0) +++ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/AppDelegate.m 2015-11-11 18:04:09 UTC (rev 3490) @@ -0,0 +1,26 @@ +// +// AppDelegate.m +// CocoaTemplate +// +// Created by Eliot Miranda on 09/11/2015. +// Copyright (c) 2015 Cog VM. All rights reserved. +// + +#import "AppDelegate.h" + +@interface AppDelegate () + +@property (weak) IBOutlet NSWindow *window; +@end + +@implementation AppDelegate + +- (void)applicationDidFinishLaunching:(NSNotification *)aNotification { + // Insert code here to initialize your application +} + +- (void)applicationWillTerminate:(NSNotification *)aNotification { + // Insert code here to tear down your application +} + +@end Added: branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/Base.lproj/MainMenu.xib =================================================================== --- branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/Base.lproj/MainMenu.xib (rev 0) +++ branches/Cog/build.macos64x64/xcode/CocoaTemplate/CocoaTemplate/Base.lproj/MainMenu.xib 2015-11-11 18:04:09 UTC (rev 3490) @@ -0,0 +1,680 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<document type="com.apple.InterfaceBuilder3.Cocoa.XIB" version="3.0" toolsVersion="6233" systemVersion="14A329f" targetRuntime="MacOSX.Cocoa" propertyAccessControl="none" useAutolayout="YES" customObjectInstantitationMethod="direct"> + <dependencies> + <plugIn identifier="com.apple.InterfaceBuilder.CocoaPlugin" version="6233"/> + </dependencies> + <objects> + <customObject id="-2" userLabel="File's Owner" customClass="NSApplication"> + <connections> + <outlet property="delegate" destination="Voe-Tx-rLC" id="GzC-gU-4Uq"/> + </connections> + </customObject> + <customObject id="-1" userLabel="First Responder" customClass="FirstResponder"/> + <customObject id="-3" userLabel="Application" customClass="NSObject"/> + <customObject id="Voe-Tx-rLC" customClass="AppDelegate" customModuleProvider=""> + <connections> + <outlet property="window" destination="QvC-M9-y7g" id="gIp-Ho-8D9"/> + </connections> + </customObject> + <customObject id="YLy-65-1bz" customClass="NSFontManager"/> + <menu title="Main Menu" systemMenu="main" id="AYu-sK-qS6"> + <items> + <menuItem title="CocoaTemplate" id="1Xt-HY-uBw"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="CocoaTemplate" systemMenu="apple" id="uQy-DD-JDr"> + <items> + <menuItem title="About CocoaTemplate" id="5kV-Vb-QxS"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="orderFrontStandardAboutPanel:" target="-1" id="Exp-CZ-Vem"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="VOq-y0-SEH"/> + <menuItem title="Preferences…" keyEquivalent="," id="BOF-NM-1cW"/> + <menuItem isSeparatorItem="YES" id="wFC-TO-SCJ"/> + <menuItem title="Services" id="NMo-om-nkz"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Services" systemMenu="services" id="hz9-B4-Xy5"/> + </menuItem> + <menuItem isSeparatorItem="YES" id="4je-JR-u6R"/> + <menuItem title="Hide CocoaTemplate" keyEquivalent="h" id="Olw-nP-bQN"> + <connections> + <action selector="hide:" target="-1" id="PnN-Uc-m68"/> + </connections> + </menuItem> + <menuItem title="Hide Others" keyEquivalent="h" id="Vdr-fp-XzO"> + <modifierMask key="keyEquivalentModifierMask" option="YES" command="YES"/> + <connections> + <action selector="hideOtherApplications:" target="-1" id="VT4-aY-XCT"/> + </connections> + </menuItem> + <menuItem title="Show All" id="Kd2-mp-pUS"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="unhideAllApplications:" target="-1" id="Dhg-Le-xox"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="kCx-OE-vgT"/> + <menuItem title="Quit CocoaTemplate" keyEquivalent="q" id="4sb-4s-VLi"> + <connections> + <action selector="terminate:" target="-1" id="Te7-pn-YzF"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem title="File" id="dMs-cI-mzQ"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="File" id="bib-Uj-vzu"> + <items> + <menuItem title="New" keyEquivalent="n" id="Was-JA-tGl"> + <connections> + <action selector="newDocument:" target="-1" id="4Si-XN-c54"/> + </connections> + </menuItem> + <menuItem title="Open…" keyEquivalent="o" id="IAo-SY-fd9"> + <connections> + <action selector="openDocument:" target="-1" id="bVn-NM-KNZ"/> + </connections> + </menuItem> + <menuItem title="Open Recent" id="tXI-mr-wws"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Open Recent" systemMenu="recentDocuments" id="oas-Oc-fiZ"> + <items> + <menuItem title="Clear Menu" id="vNY-rz-j42"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="clearRecentDocuments:" target="-1" id="Daa-9d-B3U"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem isSeparatorItem="YES" id="m54-Is-iLE"/> + <menuItem title="Close" keyEquivalent="w" id="DVo-aG-piG"> + <connections> + <action selector="performClose:" target="-1" id="HmO-Ls-i7Q"/> + </connections> + </menuItem> + <menuItem title="Save…" keyEquivalent="s" id="pxx-59-PXV"> + <connections> + <action selector="saveDocument:" target="-1" id="teZ-XB-qJY"/> + </connections> + </menuItem> + <menuItem title="Save As…" keyEquivalent="S" id="Bw7-FT-i3A"> + <connections> + <action selector="saveDocumentAs:" target="-1" id="mDf-zr-I0C"/> + </connections> + </menuItem> + <menuItem title="Revert to Saved" id="KaW-ft-85H"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="revertDocumentToSaved:" target="-1" id="iJ3-Pv-kwq"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="aJh-i4-bef"/> + <menuItem title="Page Setup…" keyEquivalent="P" id="qIS-W8-SiK"> + <modifierMask key="keyEquivalentModifierMask" shift="YES" command="YES"/> + <connections> + <action selector="runPageLayout:" target="-1" id="Din-rz-gC5"/> + </connections> + </menuItem> + <menuItem title="Print…" keyEquivalent="p" id="aTl-1u-JFS"> + <connections> + <action selector="print:" target="-1" id="qaZ-4w-aoO"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem title="Edit" id="5QF-Oa-p0T"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Edit" id="W48-6f-4Dl"> + <items> + <menuItem title="Undo" keyEquivalent="z" id="dRJ-4n-Yzg"> + <connections> + <action selector="undo:" target="-1" id="M6e-cu-g7V"/> + </connections> + </menuItem> + <menuItem title="Redo" keyEquivalent="Z" id="6dh-zS-Vam"> + <connections> + <action selector="redo:" target="-1" id="oIA-Rs-6OD"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="WRV-NI-Exz"/> + <menuItem title="Cut" keyEquivalent="x" id="uRl-iY-unG"> + <connections> + <action selector="cut:" target="-1" id="YJe-68-I9s"/> + </connections> + </menuItem> + <menuItem title="Copy" keyEquivalent="c" id="x3v-GG-iWU"> + <connections> + <action selector="copy:" target="-1" id="G1f-GL-Joy"/> + </connections> + </menuItem> + <menuItem title="Paste" keyEquivalent="v" id="gVA-U4-sdL"> + <connections> + <action selector="paste:" target="-1" id="UvS-8e-Qdg"/> + </connections> + </menuItem> + <menuItem title="Paste and Match Style" keyEquivalent="V" id="WeT-3V-zwk"> + <modifierMask key="keyEquivalentModifierMask" option="YES" command="YES"/> + <connections> + <action selector="pasteAsPlainText:" target="-1" id="cEh-KX-wJQ"/> + </connections> + </menuItem> + <menuItem title="Delete" id="pa3-QI-u2k"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="delete:" target="-1" id="0Mk-Ml-PaM"/> + </connections> + </menuItem> + <menuItem title="Select All" keyEquivalent="a" id="Ruw-6m-B2m"> + <connections> + <action selector="selectAll:" target="-1" id="VNm-Mi-diN"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="uyl-h8-XO2"/> + <menuItem title="Find" id="4EN-yA-p0u"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Find" id="1b7-l0-nxx"> + <items> + <menuItem title="Find…" tag="1" keyEquivalent="f" id="Xz5-n4-O0W"> + <connections> + <action selector="performFindPanelAction:" target="-1" id="cD7-Qs-BN4"/> + </connections> + </menuItem> + <menuItem title="Find and Replace…" tag="12" keyEquivalent="f" id="YEy-JH-Tfz"> + <modifierMask key="keyEquivalentModifierMask" option="YES" command="YES"/> + <connections> + <action selector="performFindPanelAction:" target="-1" id="WD3-Gg-5AJ"/> + </connections> + </menuItem> + <menuItem title="Find Next" tag="2" keyEquivalent="g" id="q09-fT-Sye"> + <connections> + <action selector="performFindPanelAction:" target="-1" id="NDo-RZ-v9R"/> + </connections> + </menuItem> + <menuItem title="Find Previous" tag="3" keyEquivalent="G" id="OwM-mh-QMV"> + <connections> + <action selector="performFindPanelAction:" target="-1" id="HOh-sY-3ay"/> + </connections> + </menuItem> + <menuItem title="Use Selection for Find" tag="7" keyEquivalent="e" id="buJ-ug-pKt"> + <connections> + <action selector="performFindPanelAction:" target="-1" id="U76-nv-p5D"/> + </connections> + </menuItem> + <menuItem title="Jump to Selection" keyEquivalent="j" id="S0p-oC-mLd"> + <connections> + <action selector="centerSelectionInVisibleArea:" target="-1" id="IOG-6D-g5B"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem title="Spelling and Grammar" id="Dv1-io-Yv7"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Spelling" id="3IN-sU-3Bg"> + <items> + <menuItem title="Show Spelling and Grammar" keyEquivalent=":" id="HFo-cy-zxI"> + <connections> + <action selector="showGuessPanel:" target="-1" id="vFj-Ks-hy3"/> + </connections> + </menuItem> + <menuItem title="Check Document Now" keyEquivalent=";" id="hz2-CU-CR7"> + <connections> + <action selector="checkSpelling:" target="-1" id="fz7-VC-reM"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="bNw-od-mp5"/> + <menuItem title="Check Spelling While Typing" id="rbD-Rh-wIN"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="toggleContinuousSpellChecking:" target="-1" id="7w6-Qz-0kB"/> + </connections> + </menuItem> + <menuItem title="Check Grammar With Spelling" id="mK6-2p-4JG"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="toggleGrammarChecking:" target="-1" id="muD-Qn-j4w"/> + </connections> + </menuItem> + <menuItem title="Correct Spelling Automatically" id="78Y-hA-62v"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="toggleAutomaticSpellingCorrection:" target="-1" id="2lM-Qi-WAP"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem title="Substitutions" id="9ic-FL-obx"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Substitutions" id="FeM-D8-WVr"> + <items> + <menuItem title="Show Substitutions" id="z6F-FW-3nz"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="orderFrontSubstitutionsPanel:" target="-1" id="oku-mr-iSq"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="gPx-C9-uUO"/> + <menuItem title="Smart Copy/Paste" id="9yt-4B-nSM"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="toggleSmartInsertDelete:" target="-1" id="3IJ-Se-DZD"/> + </connections> + </menuItem> + <menuItem title="Smart Quotes" id="hQb-2v-fYv"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="toggleAutomaticQuoteSubstitution:" target="-1" id="ptq-xd-QOA"/> + </connections> + </menuItem> + <menuItem title="Smart Dashes" id="rgM-f4-ycn"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="toggleAutomaticDashSubstitution:" target="-1" id="oCt-pO-9gS"/> + </connections> + </menuItem> + <menuItem title="Smart Links" id="cwL-P1-jid"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="toggleAutomaticLinkDetection:" target="-1" id="Gip-E3-Fov"/> + </connections> + </menuItem> + <menuItem title="Data Detectors" id="tRr-pd-1PS"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="toggleAutomaticDataDetection:" target="-1" id="R1I-Nq-Kbl"/> + </connections> + </menuItem> + <menuItem title="Text Replacement" id="HFQ-gK-NFA"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="toggleAutomaticTextReplacement:" target="-1" id="DvP-Fe-Py6"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem title="Transformations" id="2oI-Rn-ZJC"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Transformations" id="c8a-y6-VQd"> + <items> + <menuItem title="Make Upper Case" id="vmV-6d-7jI"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="uppercaseWord:" target="-1" id="sPh-Tk-edu"/> + </connections> + </menuItem> + <menuItem title="Make Lower Case" id="d9M-CD-aMd"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="lowercaseWord:" target="-1" id="iUZ-b5-hil"/> + </connections> + </menuItem> + <menuItem title="Capitalize" id="UEZ-Bs-lqG"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="capitalizeWord:" target="-1" id="26H-TL-nsh"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem title="Speech" id="xrE-MZ-jX0"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Speech" id="3rS-ZA-NoH"> + <items> + <menuItem title="Start Speaking" id="Ynk-f8-cLZ"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="startSpeaking:" target="-1" id="654-Ng-kyl"/> + </connections> + </menuItem> + <menuItem title="Stop Speaking" id="Oyz-dy-DGm"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="stopSpeaking:" target="-1" id="dX8-6p-jy9"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem title="Format" id="jxT-CU-nIS"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Format" id="GEO-Iw-cKr"> + <items> + <menuItem title="Font" id="Gi5-1S-RQB"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Font" systemMenu="font" id="aXa-aM-Jaq"> + <items> + <menuItem title="Show Fonts" keyEquivalent="t" id="Q5e-8K-NDq"> + <connections> + <action selector="orderFrontFontPanel:" target="YLy-65-1bz" id="WHr-nq-2xA"/> + </connections> + </menuItem> + <menuItem title="Bold" tag="2" keyEquivalent="b" id="GB9-OM-e27"> + <connections> + <action selector="addFontTrait:" target="YLy-65-1bz" id="hqk-hr-sYV"/> + </connections> + </menuItem> + <menuItem title="Italic" tag="1" keyEquivalent="i" id="Vjx-xi-njq"> + <connections> + <action selector="addFontTrait:" target="YLy-65-1bz" id="IHV-OB-c03"/> + </connections> + </menuItem> + <menuItem title="Underline" keyEquivalent="u" id="WRG-CD-K1S"> + <connections> + <action selector="underline:" target="-1" id="FYS-2b-JAY"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="5gT-KC-WSO"/> + <menuItem title="Bigger" tag="3" keyEquivalent="+" id="Ptp-SP-VEL"> + <connections> + <action selector="modifyFont:" target="YLy-65-1bz" id="Uc7-di-UnL"/> + </connections> + </menuItem> + <menuItem title="Smaller" tag="4" keyEquivalent="-" id="i1d-Er-qST"> + <connections> + <action selector="modifyFont:" target="YLy-65-1bz" id="HcX-Lf-eNd"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="kx3-Dk-x3B"/> + <menuItem title="Kern" id="jBQ-r6-VK2"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Kern" id="tlD-Oa-oAM"> + <items> + <menuItem title="Use Default" id="GUa-eO-cwY"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="useStandardKerning:" target="-1" id="6dk-9l-Ckg"/> + </connections> + </menuItem> + <menuItem title="Use None" id="cDB-IK-hbR"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="turnOffKerning:" target="-1" id="U8a-gz-Maa"/> + </connections> + </menuItem> + <menuItem title="Tighten" id="46P-cB-AYj"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="tightenKerning:" target="-1" id="hr7-Nz-8ro"/> + </connections> + </menuItem> + <menuItem title="Loosen" id="ogc-rX-tC1"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="loosenKerning:" target="-1" id="8i4-f9-FKE"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem title="Ligatures" id="o6e-r0-MWq"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Ligatures" id="w0m-vy-SC9"> + <items> + <menuItem title="Use Default" id="agt-UL-0e3"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="useStandardLigatures:" target="-1" id="7uR-wd-Dx6"/> + </connections> + </menuItem> + <menuItem title="Use None" id="J7y-lM-qPV"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="turnOffLigatures:" target="-1" id="iX2-gA-Ilz"/> + </connections> + </menuItem> + <menuItem title="Use All" id="xQD-1f-W4t"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="useAllLigatures:" target="-1" id="KcB-kA-TuK"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem title="Baseline" id="OaQ-X3-Vso"> + <modifierMask key="keyEquivalentModifierMask"/> + <menu key="submenu" title="Baseline" id="ijk-EB-dga"> + <items> + <menuItem title="Use Default" id="3Om-Ey-2VK"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="unscript:" target="-1" id="0vZ-95-Ywn"/> + </connections> + </menuItem> + <menuItem title="Superscript" id="Rqc-34-cIF"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="superscript:" target="-1" id="3qV-fo-wpU"/> + </connections> + </menuItem> + <menuItem title="Subscript" id="I0S-gh-46l"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="subscript:" target="-1" id="Q6W-4W-IGz"/> + </connections> + </menuItem> + <menuItem title="Raise" id="2h7-ER-AoG"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="raiseBaseline:" target="-1" id="4sk-31-7Q9"/> + </connections> + </menuItem> + <menuItem title="Lower" id="1tx-W0-xDw"> + <modifierMask key="keyEquivalentModifierMask"/> + <connections> + <action selector="lowerBaseline:" target="-1" id="OF1-bc-KW4"/> + </connections> + </menuItem> + </items> + </menu> + </menuItem> + <menuItem isSeparatorItem="YES" id="Ndw-q3-faq"/> + <menuItem title="Show Colors" keyEquivalent="C" id="bgn-CT-cEk"> + <connections> + <action selector="orderFrontColorPanel:" target="-1" id="mSX-Xz-DV3"/> + </connections> + </menuItem> + <menuItem isSeparatorItem="YES" id="iMs-zA-UFJ"/> + <menuItem title="Copy Style" keyEquivalent="c" id="5Vv-lz-BsD"> + <modifierMask key="keyEquivalentModifierMask" option="YES" command="YES"/> + <connections> + <action selector="copyFont:" target="-1" id="GJO-xA-L4q"/> @@ Diff output truncated at 50000 characters. @@

1 0

[commit][3488] JMM - fix xcodeproj and script so you can use makeiosvm for assert VM
by commits＠squeakvm.org 11 Nov '15

11 Nov '15

Revision: 3488 Author: johnmci Date: 2015-11-10 18:03:46 -0800 (Tue, 10 Nov 2015) Log Message: ----------- JMM - fix xcodeproj and script so you can use makeiosvm for assert VM Modified Paths: -------------- branches/Cog/build.macos32x86/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/project.pbxproj branches/Cog/build.macos32x86/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/project.pbxproj branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/xcuserdata/johnmci.xcuserdatad/xcschemes/SqueakCogSpur32x86.xcscheme branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/build.macos32x86/squeak.cog.spur/SqueakFFIPrims/SqueakFFI.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/build.macos32x86/squeak.cog.spur/SqueakSSL/SqueakSSL.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj/project.pbxproj branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/platforms/iOS/vm/iPhone/sqPlatformSpecific.h Modified: branches/Cog/build.macos32x86/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/project.pbxproj =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/project.pbxproj 2015-11-10 19:15:04 UTC (rev 3487) +++ branches/Cog/build.macos32x86/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/project.pbxproj 2015-11-11 02:03:46 UTC (rev 3488) @@ -8,7 +8,7 @@ /* Begin PBXBuildFile section */ 949199FD098186FB000FC37A /* Carbon.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 66DF6C8201D7DF7E00A80119 /* Carbon.framework */; }; - 94C941F71BBB2384005D3CFF /* dct.c in Sources */ = {isa = PBXBuildFile; fileRef = A2181BC910814EC700B8FC7A /* dct.c */; settings = {ASSET_TAGS = (); }; }; + 94C941F71BBB2384005D3CFF /* dct.c in Sources */ = {isa = PBXBuildFile; fileRef = A2181BC910814EC700B8FC7A /* dct.c */; }; A2181C0F10814EC700B8FC7A /* header.c in Sources */ = {isa = PBXBuildFile; fileRef = A2181BCA10814EC700B8FC7A /* header.c */; }; A2181C1010814EC700B8FC7A /* layer1.c in Sources */ = {isa = PBXBuildFile; fileRef = A2181BCC10814EC700B8FC7A /* layer1.c */; }; A2181C1110814EC700B8FC7A /* layer2.c in Sources */ = {isa = PBXBuildFile; fileRef = A2181BCD10814EC700B8FC7A /* layer2.c */; }; @@ -338,6 +338,7 @@ buildSettings = { ARCHS = "$(ARCHS_STANDARD_32_BIT)"; ENABLE_TESTABILITY = YES; + GCC_C_LANGUAGE_STANDARD = "compiler-default"; GCC_PREPROCESSOR_DEFINITIONS = TARGET_API_MAC_OSX; MACOSX_DEPLOYMENT_TARGET = 10.7; ONLY_ACTIVE_ARCH = YES; @@ -351,6 +352,7 @@ isa = XCBuildConfiguration; buildSettings = { ARCHS = "$(ARCHS_STANDARD_32_BIT)"; + GCC_C_LANGUAGE_STANDARD = "compiler-default"; GCC_PREPROCESSOR_DEFINITIONS = TARGET_API_MAC_OSX; MACOSX_DEPLOYMENT_TARGET = 10.7; SDKROOT = macosx; @@ -362,6 +364,7 @@ isa = XCBuildConfiguration; buildSettings = { ARCHS = "$(ARCHS_STANDARD_32_BIT)"; + GCC_C_LANGUAGE_STANDARD = "compiler-default"; GCC_PREPROCESSOR_DEFINITIONS = TARGET_API_MAC_OSX; MACOSX_DEPLOYMENT_TARGET = 10.7; SDKROOT = macosx; @@ -432,7 +435,7 @@ 946BCE030959347500803517 /* Default */, ); defaultConfigurationIsVisible = 0; - defaultConfigurationName = Default; + defaultConfigurationName = Deployment; }; 949199E409818612000FC37A /* Build configuration list for PBXNativeTarget "Mpeg3Plugin" */ = { isa = XCConfigurationList; @@ -442,7 +445,7 @@ 949199E709818612000FC37A /* Default */, ); defaultConfigurationIsVisible = 0; - defaultConfigurationName = Default; + defaultConfigurationName = Deployment; }; /* End XCConfigurationList section */ }; Modified: branches/Cog/build.macos32x86/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ) Modified: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/project.pbxproj =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/project.pbxproj 2015-11-10 19:15:04 UTC (rev 3487) +++ branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/project.pbxproj 2015-11-11 02:03:46 UTC (rev 3488) @@ -41,13 +41,6 @@ 9463C1D61AEE168F009C5CE5 /* pcre.c in Sources */ = {isa = PBXBuildFile; fileRef = 94E65A2E0DDD053900358328 /* pcre.c */; }; 9463C1D71AEE1693009C5CE5 /* study.c in Sources */ = {isa = PBXBuildFile; fileRef = 94E65A340DDD053900358328 /* study.c */; }; 948773FC10C64DD800E4AEC5 /* MainMenu.xib in Resources */ = {isa = PBXBuildFile; fileRef = 947E64DC10AA18FE00D3B69E /* MainMenu.xib */; }; - 948773FF10C64DD800E4AEC5 /* SqueakChanges.icns in Resources */ = {isa = PBXBuildFile; fileRef = 9414421F10BC89440088F8AC /* SqueakChanges.icns */; }; - 9487740010C64DD800E4AEC5 /* SqueakGeneric.icns in Resources */ = {isa = PBXBuildFile; fileRef = 9414422010BC89440088F8AC /* SqueakGeneric.icns */; }; - 9487740110C64DD800E4AEC5 /* SqueakImage.icns in Resources */ = {isa = PBXBuildFile; fileRef = 9414422110BC89440088F8AC /* SqueakImage.icns */; }; - 9487740210C64DD800E4AEC5 /* SqueakPlugin.icns in Resources */ = {isa = PBXBuildFile; fileRef = 9414422210BC89440088F8AC /* SqueakPlugin.icns */; }; - 9487740310C64DD800E4AEC5 /* SqueakProject.icns in Resources */ = {isa = PBXBuildFile; fileRef = 9414422310BC89440088F8AC /* SqueakProject.icns */; }; - 9487740410C64DD800E4AEC5 /* SqueakScript.icns in Resources */ = {isa = PBXBuildFile; fileRef = 9414422410BC89440088F8AC /* SqueakScript.icns */; }; - 9487740510C64DD800E4AEC5 /* SqueakSources.icns in Resources */ = {isa = PBXBuildFile; fileRef = 9414422510BC89440088F8AC /* SqueakSources.icns */; }; 9487740610C64DD800E4AEC5 /* Credits.rtf in Resources */ = {isa = PBXBuildFile; fileRef = 94D16CAF10BCF96B00A69A89 /* Credits.rtf */; }; 9487740810C64DD800E4AEC5 /* main.m in Sources */ = {isa = PBXBuildFile; fileRef = 29B97316FDCFA39411CA2CEA /* main.m */; }; 9487740910C64DD800E4AEC5 /* sqNamedPrims.c in Sources */ = {isa = PBXBuildFile; fileRef = 9424FF5E0DDCB1C7009912BF /* sqNamedPrims.c */; }; @@ -399,9 +392,9 @@ 94B9533310E6BD7100DC476A /* MacMenuOS9ToOSX.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = MacMenuOS9ToOSX.h; sourceTree = "<group>"; }; 94B9533410E6BD7100DC476A /* MacMenuOS9ToOSX.m */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.objc; path = MacMenuOS9ToOSX.m; sourceTree = "<group>"; }; 94BB096B1BB47DDB0016BFDF /* Security.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = Security.framework; path = System/Library/Frameworks/Security.framework; sourceTree = SDKROOT; }; - 94BB09711BB47F9B0016BFDF /* libz.tbd */ = {isa = PBXFileReference; lastKnownFileType = file; name = libz.tbd; path = usr/lib/libz.tbd; sourceTree = SDKROOT; }; - 94BB09731BB47FB20016BFDF /* libstdc++.tbd */ = {isa = PBXFileReference; lastKnownFileType = file; name = "libstdc++.tbd"; path = "usr/lib/libstdc++.tbd"; sourceTree = SDKROOT; }; - 94BB09751BB47FCD0016BFDF /* libc++.tbd */ = {isa = PBXFileReference; lastKnownFileType = file; name = "libc++.tbd"; path = "usr/lib/libc++.tbd"; sourceTree = SDKROOT; }; + 94BB09711BB47F9B0016BFDF /* libz.tbd */ = {isa = PBXFileReference; lastKnownFileType = "sourcecode.text-based-dylib-definition"; name = libz.tbd; path = usr/lib/libz.tbd; sourceTree = SDKROOT; }; + 94BB09731BB47FB20016BFDF /* libstdc++.tbd */ = {isa = PBXFileReference; lastKnownFileType = "sourcecode.text-based-dylib-definition"; name = "libstdc++.tbd"; path = "usr/lib/libstdc++.tbd"; sourceTree = SDKROOT; }; + 94BB09751BB47FCD0016BFDF /* libc++.tbd */ = {isa = PBXFileReference; lastKnownFileType = "sourcecode.text-based-dylib-definition"; name = "libc++.tbd"; path = "usr/lib/libc++.tbd"; sourceTree = SDKROOT; }; 94BCABBF10AB72A600F87527 /* sqSqueakOSXFileDirectoryInterface.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = sqSqueakOSXFileDirectoryInterface.h; path = vm/OSX/sqSqueakOSXFileDirectoryInterface.h; sourceTree = "<group>"; }; 94BCABC010AB72A600F87527 /* sqSqueakOSXFileDirectoryInterface.m */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.objc; name = sqSqueakOSXFileDirectoryInterface.m; path = vm/OSX/sqSqueakOSXFileDirectoryInterface.m; sourceTree = "<group>"; }; 94BCAD1B10AB942300F87527 /* sqSqueakOSXApplication+attributes.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = "sqSqueakOSXApplication+attributes.h"; path = "vm/OSX/sqSqueakOSXApplication+attributes.h"; sourceTree = "<group>"; }; @@ -1576,13 +1569,6 @@ 948773FC10C64DD800E4AEC5 /* MainMenu.xib in Resources */, 9422C3B51AFFFAC500448DC0 /* Localizable.strings in Resources */, 94FA4CE51BB4DE1400C1BE8F /* Images-2.xcassets in Resources */, - 948773FF10C64DD800E4AEC5 /* SqueakChanges.icns in Resources */, - 9487740010C64DD800E4AEC5 /* SqueakGeneric.icns in Resources */, - 9487740110C64DD800E4AEC5 /* SqueakImage.icns in Resources */, - 9487740210C64DD800E4AEC5 /* SqueakPlugin.icns in Resources */, - 9487740310C64DD800E4AEC5 /* SqueakProject.icns in Resources */, - 9487740410C64DD800E4AEC5 /* SqueakScript.icns in Resources */, - 9487740510C64DD800E4AEC5 /* SqueakSources.icns in Resources */, 9487740610C64DD800E4AEC5 /* Credits.rtf in Resources */, ); runOnlyForDeploymentPostprocessing = 0; @@ -1840,6 +1826,10 @@ "DEBUGVM=0", "USE_GLOBAL_STRUCT=0", SQUEAK_BUILTIN_PLUGIN, + "DEBUG=1", + "NO_ISNAN=1", + USE_INLINE_MEMORY_ACCESSORS, + HAVE_NANOSLEEP, ); GCC_WARN_ABOUT_RETURN_TYPE = YES; GCC_WARN_UNUSED_VARIABLE = YES; @@ -1869,11 +1859,8 @@ GCC_PRECOMPILE_PREFIX_HEADER = YES; GCC_PREFIX_HEADER = ../../platforms/iOS/vm/SqueakPureObjc_Prefix.pch; GCC_PREPROCESSOR_DEFINITIONS = ( + "$(inherited)", BUILD_FOR_OSX, - USE_INLINE_MEMORY_ACCESSORS, - HAVE_NANOSLEEP, - SQUEAK_BUILTIN_PLUGIN, - "DEBUGVM=0", ); GCC_WARN_64_TO_32_BIT_CONVERSION = NO; INFOPLIST_FILE = SqueakCogSpur32x86.plist; @@ -1907,6 +1894,9 @@ "DEBUGVM=1", "USE_GLOBAL_STRUCT=0", SQUEAK_BUILTIN_PLUGIN, + "NO_ISNAN=1", + USE_INLINE_MEMORY_ACCESSORS, + HAVE_NANOSLEEP, ); GCC_WARN_ABOUT_RETURN_TYPE = YES; GCC_WARN_UNUSED_VARIABLE = YES; @@ -1938,6 +1928,9 @@ "NDEBUG=1", "USE_GLOBAL_STRUCT=0", SQUEAK_BUILTIN_PLUGIN, + "NO_ISNAN=1", + USE_INLINE_MEMORY_ACCESSORS, + HAVE_NANOSLEEP, ); GCC_WARN_ABOUT_RETURN_TYPE = YES; GCC_WARN_UNUSED_VARIABLE = YES; @@ -1966,12 +1959,8 @@ GCC_PRECOMPILE_PREFIX_HEADER = YES; GCC_PREFIX_HEADER = ../../platforms/iOS/vm/SqueakPureObjc_Prefix.pch; GCC_PREPROCESSOR_DEFINITIONS = ( + "$(inherited)", BUILD_FOR_OSX, - USE_INLINE_MEMORY_ACCESSORS, - HAVE_NANOSLEEP, - SQUEAK_BUILTIN_PLUGIN, - "DEBUGVM=1", - "USE_GLOBAL_STRUCT=0", ); GCC_WARN_64_TO_32_BIT_CONVERSION = NO; INFOPLIST_FILE = SqueakCogSpur32x86.plist; @@ -2000,10 +1989,8 @@ GCC_PRECOMPILE_PREFIX_HEADER = YES; GCC_PREFIX_HEADER = ../../platforms/iOS/vm/SqueakPureObjc_Prefix.pch; GCC_PREPROCESSOR_DEFINITIONS = ( + "$(inherited)", BUILD_FOR_OSX, - HAVE_NANOSLEEP, - SQUEAK_BUILTIN_PLUGIN, - USE_INLINE_MEMORY_ACCESSORS, ); GCC_WARN_64_TO_32_BIT_CONVERSION = NO; INFOPLIST_FILE = SqueakCogSpur32x86.plist; Modified: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/xcuserdata/johnmci.xcuserdatad/xcschemes/SqueakCogSpur32x86.xcscheme =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/xcuserdata/johnmci.xcuserdatad/xcschemes/SqueakCogSpur32x86.xcscheme 2015-11-10 19:15:04 UTC (rev 3487) +++ branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/xcuserdata/johnmci.xcuserdatad/xcschemes/SqueakCogSpur32x86.xcscheme 2015-11-11 02:03:46 UTC (rev 3488) @@ -74,7 +74,7 @@ <ProfileAction displayScaleIsEnabled = "NO" displayScale = "1.00" - buildConfiguration = "Debug" + buildConfiguration = "Release" shouldUseLaunchSchemeArgsEnv = "YES" savedToolIdentifier = "" useCustomWorkingDirectory = "NO" Modified: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ) Modified: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakFFIPrims/SqueakFFI.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ) Modified: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakSSL/SqueakSSL.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ) Modified: branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm 2015-11-10 19:15:04 UTC (rev 3487) +++ branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm 2015-11-11 02:03:46 UTC (rev 3488) @@ -94,9 +94,8 @@ echo echo Mpeg3Plugin xcodebuild -project Mpeg3Plugin/Mpeg3Plugin.xcodeproj -configuration $NSD_BUILD_CONFIGURATION xcodebuild -project Mpeg3Plugin/Mpeg3Plugin.xcodeproj -configuration $NSD_BUILD_CONFIGURATION -cp -R Mpeg3Plugin/build/Release/Mpeg3Plugin.bundle mpeg3.app/Contents/Resources +cp -R Mpeg3Plugin/build/$NSD_BUILD_CONFIGURATION/Mpeg3Plugin.bundle "$DEST/Contents/Resources" -# Build the FFI plugin (New as of 27 March 2008) echo echo SqueakFFIPlugin xcodebuild -project $SFP/SqueakFFI.xcodeproj -configuration $NSD_BUILD_CONFIGURATION xcodebuild -project $SFP/SqueakFFI.xcodeproj -configuration $NSD_BUILD_CONFIGURATION @@ -154,3 +153,4 @@ # Clean out any .svn directories (result of copying) in the VM find "$DEST" -name .svn -exec rm -rf {} \; + Modified: branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj/project.pbxproj =================================================================== --- branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj/project.pbxproj 2015-11-10 19:15:04 UTC (rev 3487) +++ branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj/project.pbxproj 2015-11-11 02:03:46 UTC (rev 3488) @@ -180,6 +180,7 @@ 949382771B001B9F00C802B2 /* Crashlytics.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 949382761B001B9F00C802B2 /* Crashlytics.framework */; }; 949382791B001C7A00C802B2 /* sqSqueakOSXInfoPlistInterface.m in Sources */ = {isa = PBXBuildFile; fileRef = 94BCAE6810ACA10100F87527 /* sqSqueakOSXInfoPlistInterface.m */; }; 9493827A1B001C7E00C802B2 /* sqSqueakInfoPlistInterface.m in Sources */ = {isa = PBXBuildFile; fileRef = 9412CAE50E6C05EC00DB8625 /* sqSqueakInfoPlistInterface.m */; }; + 94A6BD651BF2A9FE00389822 /* AppKit.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 947E61C410AA03DC00D3B69E /* AppKit.framework */; }; 94B9533510E6BD7100DC476A /* MacMenuOS9ToOSX.m in Sources */ = {isa = PBXBuildFile; fileRef = 94B9533410E6BD7100DC476A /* MacMenuOS9ToOSX.m */; }; 94C315341AD4949B0096E59D /* AsynchFilePlugin.c in Sources */ = {isa = PBXBuildFile; fileRef = 94C315311AD4949B0096E59D /* AsynchFilePlugin.c */; }; 94C317511AD495CD0096E59D /* JoystickTabletPlugin.c in Sources */ = {isa = PBXBuildFile; fileRef = 94C317491AD495CD0096E59D /* JoystickTabletPlugin.c */; }; @@ -590,6 +591,7 @@ 9487749F10C64DD800E4AEC5 /* AudioToolbox.framework in Frameworks */, 948774A010C64DD800E4AEC5 /* CoreAudio.framework in Frameworks */, 948774A110C64DD800E4AEC5 /* SystemConfiguration.framework in Frameworks */, + 94A6BD651BF2A9FE00389822 /* AppKit.framework in Frameworks */, 948774A210C64DD800E4AEC5 /* ApplicationServices.framework in Frameworks */, 948774A310C64DD800E4AEC5 /* QuartzCore.framework in Frameworks */, ); Modified: branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ) Modified: branches/Cog/platforms/iOS/vm/iPhone/sqPlatformSpecific.h =================================================================== --- branches/Cog/platforms/iOS/vm/iPhone/sqPlatformSpecific.h 2015-11-10 19:15:04 UTC (rev 3487) +++ branches/Cog/platforms/iOS/vm/iPhone/sqPlatformSpecific.h 2015-11-11 02:03:46 UTC (rev 3488) @@ -165,6 +165,11 @@ # endif /* COGMTVM */ #endif /* STACKVM */ +/* warnPrintf is provided (and needed) on the win32 platform. + * But it may be mentioned elsewhere, so provide a suitable def. + */ +#define warnPrintf printf + // From Joshua Gargus, for XCode 3.1 #ifdef __GNUC__ # undef EXPORT

2 1

ChromeOS/ARM/Cog problem
by tim Rowledge 11 Nov '15

11 Nov '15

At our CampSmalltalk over the weekend Ken Dickey & I were trying to make CogSpur run on his Acer ARM/Chromebook/ChromeOS machine. At first I thought we simply had the same problem that required me to rewrite the closed PIC system but right now it seems there is something about ChromeOS that is preventing u from running generated code. A simple test program that allocates some memory, set up permissions so we can execute from there, puts a few instructions in and jumps in, runs perfectly. However, in the full VM during the early stages of startup we generate a bunch of code for trampolines and when we make the first (I think( attempt to call one of those routines (ceCaptureCStackPointers IIRC) we get instead an illegal dereference to address 0. I didn’t have a great deal of time to debug this since we had a lot going on, so everything is a bit tentative for now. Is anyone out there sufficiently familiar with chromeos to know of the details of setting memory area permissions and so forth? Since chromeos doesn’t yet seem to support Pi hardware I can’t do much here unless I buy a chromebook - or of course, someone sends me one! tim -- tim Rowledge; tim(a)rowledge.org; http://www.rowledge.org/tim Useful random insult:- His seat back is not in the full upright and locked position.

3 5

[commit][3489] JMM - cleanup do not push xcode user specific data
by commits＠squeakvm.org 11 Nov '15

11 Nov '15

Revision: 3489 Author: johnmci Date: 2015-11-10 18:07:54 -0800 (Tue, 10 Nov 2015) Log Message: ----------- JMM - cleanup do not push xcode user specific data Removed Paths: ------------- branches/Cog/build.macos32x86/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/xcuserdata/johnmci.xcuserdatad/xcschemes/SqueakCogSpur32x86.xcscheme branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/build.macos32x86/squeak.cog.spur/SqueakFFIPrims/SqueakFFI.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/build.macos32x86/squeak.cog.spur/SqueakSSL/SqueakSSL.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate Deleted: branches/Cog/build.macos32x86/squeak.cog.spur/Mpeg3Plugin/Mpeg3Plugin.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ) Deleted: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/xcuserdata/johnmci.xcuserdatad/xcschemes/SqueakCogSpur32x86.xcscheme =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/xcuserdata/johnmci.xcuserdatad/xcschemes/SqueakCogSpur32x86.xcscheme 2015-11-11 02:03:46 UTC (rev 3488) +++ branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcodeproj/xcuserdata/johnmci.xcuserdatad/xcschemes/SqueakCogSpur32x86.xcscheme 2015-11-11 02:07:54 UTC (rev 3489) @@ -1,100 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<Scheme - LastUpgradeVersion = "0700" - version = "1.8"> - <BuildAction - parallelizeBuildables = "YES" - buildImplicitDependencies = "YES"> - <BuildActionEntries> - <BuildActionEntry - buildForTesting = "YES" - buildForRunning = "YES" - buildForProfiling = "YES" - buildForArchiving = "YES" - buildForAnalyzing = "YES"> - <BuildableReference - BuildableIdentifier = "primary" - BlueprintIdentifier = "948773F910C64DD800E4AEC5" - BuildableName = "Squeak.app" - BlueprintName = "SqueakPureObjc64x64" - ReferencedContainer = "container:SqueakPureObjc.xcodeproj"> - </BuildableReference> - </BuildActionEntry> - </BuildActionEntries> - </BuildAction> - <TestAction - buildConfiguration = "Debug" - selectedDebuggerIdentifier = "Xcode.DebuggerFoundation.Debugger.LLDB" - selectedLauncherIdentifier = "Xcode.DebuggerFoundation.Launcher.GDB" - shouldUseLaunchSchemeArgsEnv = "YES"> - <Testables> - </Testables> - <MacroExpansion> - <BuildableReference - BuildableIdentifier = "primary" - BlueprintIdentifier = "948773F910C64DD800E4AEC5" - BuildableName = "Squeak.app" - BlueprintName = "SqueakCogSpur32x86" - ReferencedContainer = "container:SqueakCogSpur32x86.xcodeproj"> - </BuildableReference> - </MacroExpansion> - <AdditionalOptions> - </AdditionalOptions> - </TestAction> - <LaunchAction - buildConfiguration = "Debug" - selectedDebuggerIdentifier = "Xcode.DebuggerFoundation.Debugger.LLDB" - selectedLauncherIdentifier = "Xcode.DebuggerFoundation.Launcher.LLDB" - displayScaleIsEnabled = "NO" - displayScale = "1.00" - launchStyle = "0" - useCustomWorkingDirectory = "NO" - ignoresPersistentStateOnLaunch = "NO" - debugDocumentVersioning = "YES" - debugServiceExtension = "internal" - allowLocationSimulation = "YES"> - <BuildableProductRunnable - runnableDebuggingMode = "0"> - <BuildableReference - BuildableIdentifier = "primary" - BlueprintIdentifier = "948773F910C64DD800E4AEC5" - BuildableName = "Squeak.app" - BlueprintName = "SqueakCogSpur32x86" - ReferencedContainer = "container:SqueakCogSpur32x86.xcodeproj"> - </BuildableReference> - </BuildableProductRunnable> - <AdditionalOptions> - <AdditionalOption - key = "NSZombieEnabled" - value = "YES" - isEnabled = "YES"> - </AdditionalOption> - </AdditionalOptions> - </LaunchAction> - <ProfileAction - displayScaleIsEnabled = "NO" - displayScale = "1.00" - buildConfiguration = "Release" - shouldUseLaunchSchemeArgsEnv = "YES" - savedToolIdentifier = "" - useCustomWorkingDirectory = "NO" - debugDocumentVersioning = "YES"> - <BuildableProductRunnable - runnableDebuggingMode = "0"> - <BuildableReference - BuildableIdentifier = "primary" - BlueprintIdentifier = "948773F910C64DD800E4AEC5" - BuildableName = "Squeak.app" - BlueprintName = "SqueakCogSpur32x86" - ReferencedContainer = "container:SqueakCogSpur32x86.xcodeproj"> - </BuildableReference> - </BuildableProductRunnable> - </ProfileAction> - <AnalyzeAction - buildConfiguration = "Debug"> - </AnalyzeAction> - <ArchiveAction - buildConfiguration = "Distribution" - revealArchiveInOrganizer = "YES"> - </ArchiveAction> -</Scheme> Deleted: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakCogSpur32x86.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ) Deleted: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakFFIPrims/SqueakFFI.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ) Deleted: branches/Cog/build.macos32x86/squeak.cog.spur/SqueakSSL/SqueakSSL.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ) Deleted: branches/Cog/build.macos64x64/squeak.stack.spur/SqueakPureObjcCog.xcodeproj/project.xcworkspace/xcuserdata/johnmci.xcuserdatad/UserInterfaceState.xcuserstate =================================================================== (Binary files differ)

1 0

← Newer
1
...
6
7
8
9
10
11
12
Older →

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

Vm-dev November 2015