Vm-dev November 2015

vm-dev@lists.squeakfoundation.org

32 participants
118 discussions

Re: [squeak-dev] Seeding instances of Random
by Ben Coman 03 Nov '15

03 Nov '15

On Tue, Nov 3, 2015 at 8:32 AM, Levente Uzonyi <leves(a)elte.hu> wrote: > Hi All, > > With the recent UUID changes, we're facing the problem of properly seeding a > Random instance. The current method provides only 2^32 different initial > states, with which the chance for two images to have the same values on > startup is way too high (~9300 startups for 1% chance of collision). > To avoid the collisions we need a reliable source of random bytes. > Currently we have the following sources: > 1. /dev/urandom: fast, reliable, but not available on all platforms (e.g. > windows). > 2. UUIDPlugin: fast, but this is what we wanted to get rid of in the first > place, so it may not be available. > 3. Audio recorded through SoundSystem: slow, unreliable, and it may not be > available. > 4. Time primUTCMicrosecondClock. On its own it has way too little entropy. > We can still use it to initalize the PRNG by using additional sources of > entropy (image name, path, vm version, whatever). We can use SHA1 to get > "more random" bits from out entropy sources. But this is more like a last > resort than a solution to rely on. > > So I suggest we should create a new primitive, which can fill a given > indexable object (bytes and optionally words) with random values - the same > way Random >> #nextBytes:into:startingAt: works. It could use CryptGenRandom > on Windows, and /dev/urandom on other unix-like platforms. > > As fallback mechanisms, I'd implement 1. 2. and optionally 4., and use them > in the given order. The drawback of these mechanisms is that they create > unwanted package dependencies, because Random is in Kernel, while most > potential sources of entropy, along with SHA1, are in other packages. > > Opinions, ideas? > > Levente > This snagged my interest so I had a poke around, from which maybe getrandom() seems a better choice [1] [2] - if available. Linux earlier than Oct-2014 may not have it, and on OpenBSD and (maybe) FreeBSD it is getentropy() [3]. [1] http://djalil.chafai.net/blog/2014/10/13/linux-kernel-3-17/ [2] http://man7.org/linux/man-pages/man2/getrandom.2.html [3] http://www.2uo.de/myths-about-urandom/ Also I found discussion [4] interesting about mixing additional entropy with OS supplied randomness, and discussion [5] is a very interesting method that might provide that -- but is it worth the additional effort ? [4] http://security.stackexchange.com/questions/43344/open-source-alternative-f… [5] http://www.chronox.de/jent/doc/CPU-Jitter-NPTRNG.html cheers -ben

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Re: [Vm-dev] VM Maker: VMMaker.oscog-EstebanLorenzano.1503.mcz
by Eliot Miranda 03 Nov '15

03 Nov '15

Hi Esteban, I *think* I understand the point of "don't you dare to read from object memory!!" + (addr == 0 "or:[interpreterProxy isInMemory: addr]") - (addr == 0 or:[interpreterProxy isInMemory: addr]) there are circumstances in which we *do* want to pass in an address in object memory. But this seems a bit drastic. Could you give a specific example? Also, shouldn't we be doing something like checking that the address is associated with an object that is pinned? So this change makes me nervous and I want you to calm my nerves ;-) On Fri, Oct 30, 2015 at 9:39 AM, <commits(a)source.squeak.org> wrote: > > Esteban Lorenzano uploaded a new version of VMMaker to project VM Maker: > http://source.squeak.org/VMMaker/VMMaker.oscog-EstebanLorenzano.1503.mcz > > ==================== Summary ==================== > > Name: VMMaker.oscog-EstebanLorenzano.1503 > Author: EstebanLorenzano > Time: 30 October 2015, 2:37:07.998518 pm > UUID: 2cc25296-b733-4968-bd6b-8f3db5277693 > Ancestors: VMMaker.oscog-eem.1502 > > general: > - applying correct cast so compiler does not fails. > > ThreadedFFIPlugin: > - ExternalAddress now are taken correctly (nor as ByteArray or Alien, > because they are different beasts). > - allow pushing of pointers to any type (into a ByteArray, an > ExternalAddress or an Alien), to allow passing parameters style int*, > float*, etc. > - allow reading in memory to allow read chunks of ByteArray > > =============== Diff against VMMaker.oscog-eem.1502 =============== > > Item was changed: > ----- Method: Cogit>>addressIsInInstructions: (in category 'testing') > ----- > addressIsInInstructions: address > <var: #address type: #'AbstractInstruction *'> > + ^self cCode: '!!((((unsigned)address) & BytesPerWord-1)) \ > - ^self cCode: '!!((unsigned)((address) & BytesPerWord-1)) \ > && (address) >= &abstractOpcodes[0] \ > && (address) < > &abstractOpcodes[opcodeIndex]' > inSmalltalk: [(abstractOpcodes object identityIndexOf: > address) between: 1 and: opcodeIndex]! > > Item was changed: > ----- Method: ThreadedFFIPlugin>>ffiAddressOf:startingAt:size: (in > category 'primitive support') ----- > ffiAddressOf: rcvr startingAt: byteOffset size: byteSize > "return an int of the address of the byteSize slot (byte, short, int, > whatever) at byteOffset in rcvr. Nominally intended for use with > ExternalAddress objects, this code will work (for obscure historical > reasons) with plain Byte or Word Arrays as well. " > | rcvrClass rcvrSize addr | > (interpreterProxy isBytes: rcvr) ifFalse:[^interpreterProxy > primitiveFail]. > (byteOffset > 0) ifFalse:[^interpreterProxy primitiveFail]. > rcvrClass := interpreterProxy fetchClassOf: rcvr. > rcvrSize := interpreterProxy byteSizeOf: rcvr. > rcvrClass = interpreterProxy classExternalAddress ifTrue:[ > (rcvrSize = 4) ifFalse:[^interpreterProxy primitiveFail]. > addr := interpreterProxy fetchPointer: 0 ofObject: rcvr. > "don't you dare to read from object memory!!" > + (addr == 0 "or:[interpreterProxy isInMemory: addr]") > - (addr == 0 or:[interpreterProxy isInMemory: addr]) > ifTrue:[^interpreterProxy primitiveFail]. > ] ifFalse:[ > (byteOffset+byteSize-1 <= rcvrSize) > ifFalse:[^interpreterProxy primitiveFail]. > addr := self cCoerce: (interpreterProxy > firstIndexableField: rcvr) to: 'int'. > ]. > addr := addr + byteOffset - 1. > ^addr! > > Item was changed: > ----- Method: ThreadedFFIPlugin>>ffiAtomicArgByReference:Class:in: (in > category 'callout support') ----- > ffiAtomicArgByReference: oop Class: oopClass in: calloutState > <var: #calloutState type: #'CalloutState *'> > "Support for generic callout. Prepare a pointer reference to an > atomic type for callout. > + Note: > + for type 'void*' we allow ByteArray/String/Symbol, > wordVariableSubclass, Alien or ExternalAddress. > + for other types we allow ByteArray, wordVariableSubclass, > Alien or ExternalAddress." > - Note: for type 'void*' we allow ByteArray/String/Symbol, > wordVariableSubclass or Alien." > | atomicType isString isAlien | > <inline: true> > atomicType := self atomicTypeOf: calloutState ffiArgHeader. > (atomicType = FFITypeBool) ifTrue: "No bools on input" > [^FFIErrorCoercionFailed]. > isAlien := (isString := interpreterProxy > includesBehavior: oopClass > ThatOf: interpreterProxy > classString) > ifTrue: [false] > ifFalse: > [interpreterProxy > includesBehavior: oopClass > ThatOf: interpreterProxy > classAlien]. > ((atomicType >> 1) = (FFITypeSignedChar >> 1)) ifTrue:"string > value (char*)" > "note: the only types allowed for passing into char* types > are > ByteArray, String, Symbol, Alien and *no* other byte > indexed objects > (e.g., CompiledMethod, LargeInteger). We only check for > strings > here and fall through to the byte* check otherwise." > [isString ifTrue:"String/Symbol" > "Strings must be allocated by the ffi support code" > [^self ffiPushString: (interpreterProxy > firstIndexableField: oop) > OfLength: (interpreterProxy byteSizeOf: > oop) > in: calloutState]. > "Fall through to byte* test" > atomicType := FFITypeUnsignedByte]. > > self cppIf: COGMTVM ifTrue: > ["Since all the following pass the address of the first indexable > field we need to fail > the call if it is threaded and the object is young, since it may > move during the call." > ((calloutState callFlags anyMask: FFICallFlagThreaded) > and: [(isAlien not or: [self isDirectAlien: oop]) > and: [interpreterProxy isYoung: oop]]) ifTrue: > [^PrimErrObjectMayMove negated]]. > > (atomicType = FFITypeVoid or:[(atomicType >> 1) = > (FFITypeSignedByte >> 1)]) ifTrue: > "byte* -- see comment on string above" > + [(isString or: [oopClass = interpreterProxy > classByteArray]) ifTrue: "String/Symbol/ByteArray" > - [(isString > - or: [oopClass = interpreterProxy classByteArray]) > ifTrue:"String/Symbol/ByteArray" > [^self ffiPushPointer: (interpreterProxy > firstIndexableField: oop) in: calloutState]. > + (oopClass = interpreterProxy classExternalAddress) ifTrue: > + [^self ffiPushPointer: (self longAt: oop + > interpreterProxy baseHeaderSize) in: calloutState]. > + isAlien ifTrue: > - (isAlien or: [oopClass = interpreterProxy > classExternalAddress]) ifTrue: > [^self ffiPushPointer: (self pointerForOop: (self > startOfData: oop)) in: calloutState]. > atomicType = FFITypeVoid ifFalse: > [^FFIErrorCoercionFailed]]. > "note: type void falls through" > > + "I can push pointers to any type (take for instance calls who > receive int* output arguments, etc.) > + but I need to store them into a ByteArray, ExternalAddress or > Alien" > + (atomicType <= FFITypeDoubleFloat) ifTrue: > + [((interpreterProxy isWords: oop) or: [oopClass = > interpreterProxy classByteArray]) ifTrue: > + [^self ffiPushPointer: (interpreterProxy > firstIndexableField: oop) in: calloutState]. > + (oopClass = interpreterProxy classExternalAddress) ifTrue: > + [^self ffiPushPointer: (self longAt: oop + > interpreterProxy baseHeaderSize) in: calloutState]. > + isAlien ifTrue: > + [^self ffiPushPointer: (self pointerForOop: (self > startOfData: oop)) in: calloutState]]. > - (atomicType <= FFITypeSignedInt "void/short/int" > - or:[atomicType = FFITypeSingleFloat]) ifTrue: > - ["require a word subclass to work" > - (interpreterProxy isWords: oop) ifTrue: > - [^self ffiPushPointer: (interpreterProxy > firstIndexableField: oop) in: calloutState]]. > > ^FFIErrorCoercionFailed! > > -- _,,,^..^,,,_ best, Eliot

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VM Maker: VMMaker.oscog-eem.1504.mcz
by commits＠source.squeak.org 03 Nov '15

03 Nov '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1504.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1504 Author: eem Time: 2 November 2015, 10:16:22.592 pm UUID: 3c702143-ff40-4e38-a55e-065a3aec15ec Ancestors: VMMaker.oscog-EstebanLorenzano.1503 Merge with VMMaker.oscog-EstebanLorenzano.1503: - simplify the addressIsInInstructions: macro. - express some concerns about ffiAddressOf:startingAt:size: x64 Cogit: Add support for MoveAb:R: & MoveR:Ab: on x64 & x86. Tim, would you mind adding support for ARM? The misuse of MoveMb:r:R:/MoveR:Mb:r: as a stand-in for MoveAb:R:/MoveR:Ab: only works on 32-bit platforms. Fix rip-relative addressing for MoveCwR/PushCw. Add some tests. Nuke the leaking breaks in genInnerPrimitiveNew[WithArg]: Execution now gets to the first jitted method that wants to create a closure. =============== Diff against VMMaker.oscog-EstebanLorenzano.1503 =============== Item was changed: ----- Method: CogIA32Compiler>>computeMaximumSize (in category 'generate machine code') ----- computeMaximumSize "Compute the maximum size for each opcode. This allows jump offsets to be determined, provided that all backward branches are long branches." "N.B. The ^N forms are to get around the bytecode compiler's long branch limits which are exceeded when each case jumps around the otherwise." opcode caseOf: { "Noops & Pseudo Ops" [Label] -> [^0]. [AlignmentNops] -> [^(operands at: 0) - 1]. [Fill16] -> [^2]. [Fill32] -> [^4]. [FillFromWord] -> [^4]. [Nop] -> [^1]. "Specific Control/Data Movement" [CDQ] -> [^1]. [IDIVR] -> [^2]. [IMULRR] -> [^3]. [CPUID] -> [^2]. [CMPXCHGAwR] -> [^7]. [CMPXCHGMwrR] -> [^(self concreteRegister: (operands at: 1)) = ESP ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]] ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]]. [LFENCE] -> [^3]. [MFENCE] -> [^3]. [SFENCE] -> [^3]. [LOCK] -> [^1]. [XCHGAwR] -> [^6]. [XCHGMwrR] -> [^(self concreteRegister: (operands at: 1)) = ESP ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]] ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [6]]]. [XCHGRR] -> [^((self concreteRegister: (operands at: 0)) = EAX or: [(self concreteRegister: (operands at: 1)) = EAX]) ifTrue: [1] ifFalse: [2]]. "Control" [CallFull] -> [^5]. [Call] -> [^5]. [JumpR] -> [^2]. [JumpFull] -> [self resolveJumpTarget. ^5]. [JumpLong] -> [self resolveJumpTarget. ^5]. [Jump] -> [self resolveJumpTarget. ^5]. [JumpZero] -> [self resolveJumpTarget. ^6]. [JumpNonZero] -> [self resolveJumpTarget. ^6]. [JumpNegative] -> [self resolveJumpTarget. ^6]. [JumpNonNegative] -> [self resolveJumpTarget. ^6]. [JumpOverflow] -> [self resolveJumpTarget. ^6]. [JumpNoOverflow] -> [self resolveJumpTarget. ^6]. [JumpCarry] -> [self resolveJumpTarget. ^6]. [JumpNoCarry] -> [self resolveJumpTarget. ^6]. [JumpLess] -> [self resolveJumpTarget. ^6]. [JumpGreaterOrEqual] -> [self resolveJumpTarget. ^6]. [JumpGreater] -> [self resolveJumpTarget. ^6]. [JumpLessOrEqual] -> [self resolveJumpTarget. ^6]. [JumpBelow] -> [self resolveJumpTarget. ^6]. [JumpAboveOrEqual] -> [self resolveJumpTarget. ^6]. [JumpAbove] -> [self resolveJumpTarget. ^6]. [JumpBelowOrEqual] -> [self resolveJumpTarget. ^6]. [JumpLongZero] -> [self resolveJumpTarget. ^6]. [JumpLongNonZero] -> [self resolveJumpTarget. ^6]. [JumpFPEqual] -> [self resolveJumpTarget. ^6]. [JumpFPNotEqual] -> [self resolveJumpTarget. ^6]. [JumpFPLess] -> [self resolveJumpTarget. ^6]. [JumpFPGreaterOrEqual] -> [self resolveJumpTarget. ^6]. [JumpFPGreater] -> [self resolveJumpTarget. ^6]. [JumpFPLessOrEqual] -> [self resolveJumpTarget. ^6]. [JumpFPOrdered] -> [self resolveJumpTarget. ^6]. [JumpFPUnordered] -> [self resolveJumpTarget. ^6]. [RetN] -> [^(operands at: 0) = 0 ifTrue: [1] ifFalse: [3]]. [Stop] -> [^1]. "Arithmetic" [AddCqR] -> [^(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]]. [AndCqR] -> [^(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]]. [CmpCqR] -> [^(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]]. [OrCqR] -> [^(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]]. [SubCqR] -> [^(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]]. [TstCqR] -> [^((self isQuick: (operands at: 0)) and: [(self concreteRegister: (operands at: 1)) < 4]) ifTrue: [3] ifFalse: [(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]]. [AddCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]. [AndCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]. [CmpCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]. [OrCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]. [SubCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]. [XorCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]. [AddRR] -> [^2]. [AndRR] -> [^2]. [CmpRR] -> [^2]. [OrRR] -> [^2]. [XorRR] -> [^2]. [SubRR] -> [^2]. [NegateR] -> [^2]. [LoadEffectiveAddressMwrR] -> [^((self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [6]) + ((self concreteRegister: (operands at: 1)) = ESP ifTrue: [1] ifFalse: [0])]. [LogicalShiftLeftCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]]. [LogicalShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]]. [ArithmeticShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]]. [LogicalShiftLeftRR] -> [^self computeShiftRRSize]. [LogicalShiftRightRR] -> [^self computeShiftRRSize]. [ArithmeticShiftRightRR] -> [^self computeShiftRRSize]. [AddRdRd] -> [^4]. [CmpRdRd] -> [^4]. [SubRdRd] -> [^4]. [MulRdRd] -> [^4]. [DivRdRd] -> [^4]. [SqrtRd] -> [^4]. "Data Movement" [MoveCqR] -> [^(operands at: 0) = 0 ifTrue: [2] ifFalse: [5]]. [MoveCwR] -> [^5]. [MoveRR] -> [^2]. [MoveRdRd] -> [^4]. [MoveAwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]. [MoveRAw] -> [^(self concreteRegister: (operands at: 0)) = EAX ifTrue: [5] ifFalse: [6]]. + [MoveAbR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]]. + [MoveRAb] -> [^(self concreteRegister: (operands at: 0)) = EAX ifTrue: [5] ifFalse: [6]]. [MoveRMwr] -> [^((self isQuick: (operands at: 1)) ifTrue: [((operands at: 1) = 0 and: [(self concreteRegister: (operands at: 2)) ~= EBP]) ifTrue: [2] ifFalse: [3]] ifFalse: [6]) + ((self concreteRegister: (operands at: 2)) = ESP ifTrue: [1] ifFalse: [0])]. [MoveRdM64r] -> [^((self isQuick: (operands at: 1)) ifTrue: [5] ifFalse: [8]) + ((self concreteRegister: (operands at: 2)) = ESP ifTrue: [1] ifFalse: [0])]. [MoveMbrR] -> [^(self concreteRegister: (operands at: 1)) = ESP ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]] ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]]. [MoveRMbr] -> [^(self concreteRegister: (operands at: 2)) = ESP ifTrue: [7] ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [3] ifFalse: [6]]]. [MoveM16rR] -> [^(self concreteRegister: (operands at: 1)) = ESP ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]] ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]]. [MoveM64rRd] -> [^((self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]) + ((self concreteRegister: (operands at: 1)) = ESP ifTrue: [1] ifFalse: [0])]. [MoveMwrR] -> [^((self isQuick: (operands at: 0)) ifTrue: [((operands at: 0) = 0 and: [(self concreteRegister: (operands at: 1)) ~= EBP]) ifTrue: [2] ifFalse: [3]] ifFalse: [6]) + ((self concreteRegister: (operands at: 1)) = ESP ifTrue: [1] ifFalse: [0])]. [MoveXbrRR] -> [self assert: (self concreteRegister: (operands at: 0)) ~= ESP. ^(self concreteRegister: (operands at: 1)) = EBP ifTrue: [5] ifFalse: [4]]. [MoveRXbrR] -> [self assert: (self concreteRegister: (operands at: 1)) ~= ESP. ^((self concreteRegister: (operands at: 2)) = EBP ifTrue: [4] ifFalse: [3]) + ((self concreteRegister: (operands at: 0)) >= 4 ifTrue: [2] ifFalse: [0])]. [MoveXwrRR] -> [self assert: (self concreteRegister: (operands at: 0)) ~= ESP. ^(self concreteRegister: (operands at: 1)) = EBP ifTrue: [4] ifFalse: [3]]. [MoveRXwrR] -> [self assert: (self concreteRegister: (operands at: 1)) ~= ESP. ^(self concreteRegister: (operands at: 2)) = EBP ifTrue: [4] ifFalse: [3]]. [PopR] -> [^1]. [PushR] -> [^1]. [PushCq] -> [^(self isQuick: (operands at: 0)) ifTrue: [2] ifFalse: [5]]. [PushCw] -> [^5]. [PrefetchAw] -> [^self hasSSEInstructions ifTrue: [7] ifFalse: [0]]. "Conversion" [ConvertRRd] -> [^4] }. ^0 "to keep C compiler quiet"! Item was added: + ----- Method: CogIA32Compiler>>concretizeMoveAbR (in category 'generate machine code') ----- + concretizeMoveAbR + "Will get inlined into concretizeAt: switch." + <inline: true> + | addressOperand reg | + addressOperand := operands at: 0. + (self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue: + [addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address]. + reg := self concreteRegister: (operands at: 1). + reg = EAX ifTrue: + [machineCode + at: 0 put: 16rA0; + at: 1 put: (addressOperand bitAnd: 16rFF); + at: 2 put: (addressOperand >> 8 bitAnd: 16rFF); + at: 3 put: (addressOperand >> 16 bitAnd: 16rFF); + at: 4 put: (addressOperand >> 24 bitAnd: 16rFF). + ^machineCodeSize := 5]. + machineCode + at: 0 put: 16r8A; + at: 1 put: (self mod: ModRegInd RM: 5 RO: reg); + at: 2 put: (addressOperand bitAnd: 16rFF); + at: 3 put: (addressOperand >> 8 bitAnd: 16rFF); + at: 4 put: (addressOperand >> 16 bitAnd: 16rFF); + at: 5 put: (addressOperand >> 24 bitAnd: 16rFF). + ^machineCodeSize := 6! Item was added: + ----- Method: CogIA32Compiler>>concretizeMoveRAb (in category 'generate machine code') ----- + concretizeMoveRAb + "Will get inlined into concretizeAt: switch." + <inline: true> + | addressOperand reg | + reg := self concreteRegister: (operands at: 0). + addressOperand := operands at: 1. + (self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue: + [addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address]. + reg = EAX ifTrue: + [machineCode + at: 0 put: 16rA2; + at: 1 put: (addressOperand bitAnd: 16rFF); + at: 2 put: (addressOperand >> 8 bitAnd: 16rFF); + at: 3 put: (addressOperand >> 16 bitAnd: 16rFF); + at: 4 put: (addressOperand >> 24 bitAnd: 16rFF). + ^machineCodeSize := 5]. + machineCode + at: 0 put: 16r88; + at: 1 put: (self mod: ModRegInd RM: 5 RO: reg); + at: 2 put: (addressOperand bitAnd: 16rFF); + at: 3 put: (addressOperand >> 8 bitAnd: 16rFF); + at: 4 put: (addressOperand >> 16 bitAnd: 16rFF); + at: 5 put: (addressOperand >> 24 bitAnd: 16rFF). + ^machineCodeSize := 6! Item was changed: ----- Method: CogIA32Compiler>>dispatchConcretize (in category 'generate machine code') ----- dispatchConcretize "Attempt to generate concrete machine code for the instruction at address. This is the inner dispatch of concretizeAt: actualAddress which exists only to get around the branch size limits in the SqueakV3 (blue book derived) bytecode set." <returnTypeC: #void> opcode caseOf: { "Noops & Pseudo Ops" [Label] -> [^self concretizeLabel]. [AlignmentNops] -> [^self concretizeAlignmentNops]. [Fill16] -> [^self concretizeFill16]. [Fill32] -> [^self concretizeFill32]. [FillFromWord] -> [^self concretizeFillFromWord]. [Nop] -> [^self concretizeNop]. "Specific Control/Data Movement" [CDQ] -> [^self concretizeCDQ]. [IDIVR] -> [^self concretizeIDIVR]. [IMULRR] -> [^self concretizeMulRR]. [CPUID] -> [^self concretizeCPUID]. [CMPXCHGAwR] -> [^self concretizeCMPXCHGAwR]. [CMPXCHGMwrR] -> [^self concretizeCMPXCHGMwrR]. [LFENCE] -> [^self concretizeFENCE: 5]. [MFENCE] -> [^self concretizeFENCE: 6]. [SFENCE] -> [^self concretizeFENCE: 7]. [LOCK] -> [^self concretizeLOCK]. [XCHGAwR] -> [^self concretizeXCHGAwR]. [XCHGMwrR] -> [^self concretizeXCHGMwrR]. [XCHGRR] -> [^self concretizeXCHGRR]. "Control" [Call] -> [^self concretizeCall]. [CallFull] -> [^self concretizeCall]. [JumpR] -> [^self concretizeJumpR]. [JumpFull] -> [^self concretizeJumpLong]. [JumpLong] -> [^self concretizeJumpLong]. [JumpLongZero] -> [^self concretizeConditionalJump: 16r4]. [JumpLongNonZero] -> [^self concretizeConditionalJump: 16r5]. [Jump] -> [^self concretizeJump]. "Table B-1 Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture" [JumpZero] -> [^self concretizeConditionalJump: 16r4]. [JumpNonZero] -> [^self concretizeConditionalJump: 16r5]. [JumpNegative] -> [^self concretizeConditionalJump: 16r8]. [JumpNonNegative] -> [^self concretizeConditionalJump: 16r9]. [JumpOverflow] -> [^self concretizeConditionalJump: 16r0]. [JumpNoOverflow] -> [^self concretizeConditionalJump: 16r1]. [JumpCarry] -> [^self concretizeConditionalJump: 16r2]. [JumpNoCarry] -> [^self concretizeConditionalJump: 16r3]. [JumpLess] -> [^self concretizeConditionalJump: 16rC]. [JumpGreaterOrEqual] -> [^self concretizeConditionalJump: 16rD]. [JumpGreater] -> [^self concretizeConditionalJump: 16rF]. [JumpLessOrEqual] -> [^self concretizeConditionalJump: 16rE]. [JumpBelow] -> [^self concretizeConditionalJump: 16r2]. [JumpAboveOrEqual] -> [^self concretizeConditionalJump: 16r3]. [JumpAbove] -> [^self concretizeConditionalJump: 16r7]. [JumpBelowOrEqual] -> [^self concretizeConditionalJump: 16r6]. [JumpFPEqual] -> [^self concretizeConditionalJump: 16r4]. [JumpFPNotEqual] -> [^self concretizeConditionalJump: 16r5]. [JumpFPLess] -> [^self concretizeConditionalJump: 16r2]. [JumpFPGreaterOrEqual] -> [^self concretizeConditionalJump: 16r3]. [JumpFPGreater] -> [^self concretizeConditionalJump: 16r7]. [JumpFPLessOrEqual] -> [^self concretizeConditionalJump: 16r6]. [JumpFPOrdered] -> [^self concretizeConditionalJump: 16rB]. [JumpFPUnordered] -> [^self concretizeConditionalJump: 16rA]. [RetN] -> [^self concretizeRetN]. [Stop] -> [^self concretizeStop]. "Arithmetic" [AddCqR] -> [^self concretizeAddCqR]. [AddCwR] -> [^self concretizeAddCwR]. [AddRR] -> [^self concretizeAddRR]. [AddRdRd] -> [^self concretizeSEE2OpRdRd: 16r58]. [AndCqR] -> [^self concretizeAndCqR]. [AndCwR] -> [^self concretizeAndCwR]. [AndRR] -> [^self concretizeAndRR]. [TstCqR] -> [^self concretizeTstCqR]. [CmpCqR] -> [^self concretizeCmpCqR]. [CmpCwR] -> [^self concretizeCmpCwR]. [CmpRR] -> [^self concretizeCmpRR]. [CmpRdRd] -> [^self concretizeCmpRdRd]. [DivRdRd] -> [^self concretizeSEE2OpRdRd: 16r5E]. [MulRdRd] -> [^self concretizeSEE2OpRdRd: 16r59]. [OrCqR] -> [^self concretizeOrCqR]. [OrCwR] -> [^self concretizeOrCwR]. [OrRR] -> [^self concretizeOrRR]. [SubCqR] -> [^self concretizeSubCqR]. [SubCwR] -> [^self concretizeSubCwR]. [SubRR] -> [^self concretizeSubRR]. [SubRdRd] -> [^self concretizeSEE2OpRdRd: 16r5C]. [SqrtRd] -> [^self concretizeSqrtRd]. [XorCwR] -> [^self concretizeXorCwR]. [XorRR] -> [^self concretizeXorRR]. [NegateR] -> [^self concretizeNegateR]. [LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR]. [ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR]. [LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR]. [LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR]. [ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR]. [LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR]. "Data Movement" [MoveCqR] -> [^self concretizeMoveCqR]. [MoveCwR] -> [^self concretizeMoveCwR]. [MoveRR] -> [^self concretizeMoveRR]. [MoveAwR] -> [^self concretizeMoveAwR]. [MoveRAw] -> [^self concretizeMoveRAw]. + [MoveAbR] -> [^self concretizeMoveAbR]. + [MoveRAb] -> [^self concretizeMoveRAb]. [MoveMbrR] -> [^self concretizeMoveMbrR]. [MoveRMbr] -> [^self concretizeMoveRMbr]. [MoveM16rR] -> [^self concretizeMoveM16rR]. [MoveM64rRd] -> [^self concretizeMoveM64rRd]. [MoveMwrR] -> [^self concretizeMoveMwrR]. [MoveXbrRR] -> [^self concretizeMoveXbrRR]. [MoveRXbrR] -> [^self concretizeMoveRXbrR]. [MoveXwrRR] -> [^self concretizeMoveXwrRR]. [MoveRXwrR] -> [^self concretizeMoveRXwrR]. [MoveRMwr] -> [^self concretizeMoveRMwr]. [MoveRdM64r] -> [^self concretizeMoveRdM64r]. [PopR] -> [^self concretizePopR]. [PushR] -> [^self concretizePushR]. [PushCq] -> [^self concretizePushCq]. [PushCw] -> [^self concretizePushCw]. [PrefetchAw] -> [^self concretizePrefetchAw]. "Conversion" [ConvertRRd] -> [^self concretizeConvertRRd] }! Item was added: + ----- Method: CogIA32CompilerTests>>testMoveAbR (in category 'tests') ----- + testMoveAbR + "self new testMoveAbR" + CogIA32CompilerForTests byteRegistersWithNamesDo: + [:reg :regname| + #(16r555555 16rAAAAAA) do: + [:addr| | inst len | + inst := self gen: MoveAbR operand: addr operand: reg. + len := inst concretizeAt: 0. + self processor + disassembleInstructionAt: 0 + In: inst machineCode object + into: [:str :sz| | plainJane herIntended | + "Convert e.g. '00000000: movl %eax, 0x2(%eax) : 89 40 02' to 'movl %eax, 0x2(%eax)'" + plainJane := self strip: str. + herIntended := 'movb 0x', (addr hex allButFirst: 3), ', ', regname. + self assert: (plainJane match: herIntended). + self assert: len = sz]]]! Item was added: + ----- Method: CogIA32CompilerTests>>testMoveRAb (in category 'tests') ----- + testMoveRAb + "self new testMoveRAb" + CogIA32CompilerForTests byteRegistersWithNamesDo: + [:reg :regname| + #(16r555555 16rAAAAAA) do: + [:addr| | inst len | + inst := self gen: MoveRAb operand: reg operand: addr. + len := inst concretizeAt: 0. + self processor + disassembleInstructionAt: 0 + In: inst machineCode object + into: [:str :sz| | plainJane herIntended | + plainJane := self strip: str. + herIntended := 'movb ', regname, ', 0x', (addr hex allButFirst: 3). + self assert: (plainJane match: herIntended). + self assert: len = sz]]]! Item was changed: ----- Method: CogInLineLiteralsX64Compiler>>concretizeMoveCwR (in category 'generate machine code') ----- concretizeMoveCwR "Will get inlined into concretizeAt: switch." <inline: true> | value reg offset | value := operands at: 0. reg := self concreteRegister: (operands at: 1). (self isAnInstruction: (cogit cCoerceSimple: value to: #'AbstractInstruction *')) ifTrue: [value := (cogit cCoerceSimple: value to: #'AbstractInstruction *') address]. (cogit addressIsInCurrentCompilation: value) ifTrue: [offset := value - (address + 7). machineCode at: 0 put: (self rexR: reg x: 0 b: 0); + at: 1 put: 16r8D; "LoadEffectiveAddress" + at: 2 put: (self mod: ModRegInd RM: 5 RO: reg); - at: 1 put: 16r8B; - at: 2 put: (self mod: ModReg RM: 5 RO: reg); at: 3 put: (offset bitAnd: 16rFF); at: 4 put: (offset >> 8 bitAnd: 16rFF); at: 5 put: (offset >> 16 bitAnd: 16rFF); at: 6 put: (offset >> 24 bitAnd: 16rFF). ^machineCodeSize := 7]. machineCode at: 0 put: (self rexR: reg x: 0 b: reg); at: 1 put: 16rB8 + (reg bitAnd: 7); at: 2 put: (value bitAnd: 16rFF); at: 3 put: (value >> 8 bitAnd: 16rFF); at: 4 put: (value >> 16 bitAnd: 16rFF); at: 5 put: (value >> 24 bitAnd: 16rFF); at: 6 put: (value >> 32 bitAnd: 16rFF); at: 7 put: (value >> 40 bitAnd: 16rFF); at: 8 put: (value >> 48 bitAnd: 16rFF); at: 9 put: (value >> 56 bitAnd: 16rFF); at: 10 put: 16r90. "Add a nop to disambiguate between MoveCwR/PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)" self assert: (self mod: ModReg RM: 0 RO: 0) > 16r90. ^machineCodeSize := 11! Item was changed: ----- Method: CogInLineLiteralsX64Compiler>>concretizePushCw (in category 'generate machine code') ----- concretizePushCw "Will get inlined into concretizeAt: switch." <inline: true> | value offset | value := operands at: 0. (self isAnInstruction: (cogit cCoerceSimple: value to: #'AbstractInstruction *')) ifTrue: [value := (cogit cCoerceSimple: value to: #'AbstractInstruction *') address]. (cogit addressIsInCurrentCompilation: value) ifTrue: + [offset := value - (address + 7). - [offset := value - (address + 6). machineCode + at: 0 put: (self rexR: ConcreteRISCTempReg x: 0 b: 0); + at: 1 put: 16r8D; "LoadEffectiveAddress" + at: 2 put: (self mod: ModRegInd RM: 5 RO: ConcreteRISCTempReg); + at: 3 put: (offset bitAnd: 16rFF); + at: 4 put: (offset >> 8 bitAnd: 16rFF); + at: 5 put: (offset >> 16 bitAnd: 16rFF); + at: 6 put: (offset >> 24 bitAnd: 16rFF); + at: 7 put: 16r41; + at: 8 put: 16r48 + ConcreteRISCTempReg. + ^machineCodeSize := 9]. - at: 0 put: 16rFF; - at: 1 put: 16r35; - at: 2 put: (offset bitAnd: 16rFF); - at: 3 put: (offset >> 8 bitAnd: 16rFF); - at: 4 put: (offset >> 16 bitAnd: 16rFF); - at: 5 put: (offset >> 24 bitAnd: 16rFF). - ^machineCodeSize := 6]. machineCode at: 0 put: (self rexR: ConcreteRISCTempReg x: 0 b: ConcreteRISCTempReg); at: 1 put: 16rB8 + (ConcreteRISCTempReg bitAnd: 7); at: 2 put: (value bitAnd: 16rFF); at: 3 put: (value >> 8 bitAnd: 16rFF); at: 4 put: (value >> 16 bitAnd: 16rFF); at: 5 put: (value >> 24 bitAnd: 16rFF); at: 6 put: (value >> 32 bitAnd: 16rFF); at: 7 put: (value >> 40 bitAnd: 16rFF); at: 8 put: (value >> 48 bitAnd: 16rFF); at: 9 put: (value >> 56 bitAnd: 16rFF); at: 10 put: 16r41; + at: 11 put: 16r48 + ConcreteRISCTempReg. "The 48 will disambiguate between MoveCwR, PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)" - at: 11 put: 16r50 + (ConcreteRISCTempReg - 8). "The 50 will disambiguate between MoveCwR, PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)" self assert: ConcreteRISCTempReg >= 8. self assert: (self mod: ModReg RM: 0 RO: 0) > 16r57. ^machineCodeSize := 12! Item was changed: ----- Method: CogObjectRepresentationFor64BitSpur>>genInnerPrimitiveNew: (in category 'primitive generators') ----- genInnerPrimitiveNew: retNoffset "Implement primitiveNew for convenient cases: - the receiver has a hash - the receiver is fixed size (excluding ephemerons to save instructions & miniscule time) - single word header/num slots < numSlotsMask - the result fits in eden (actually below scavengeThreshold)" | headerReg fillReg instSpecReg byteSizeReg jumpUnhashed jumpVariableOrEphemeron jumpNoSpace jumpTooBig jumpHasSlots fillLoop skip | <var: 'skip' type: #'AbstractInstruction *'> <var: 'fillLoop' type: #'AbstractInstruction *'> <var: 'jumpTooBig' type: #'AbstractInstruction *'> <var: 'jumpHasSlots' type: #'AbstractInstruction *'> <var: 'jumpNoSpace' type: #'AbstractInstruction *'> <var: 'jumpUnhashed' type: #'AbstractInstruction *'> <var: 'jumpVariableOrEphemeron' type: #'AbstractInstruction *'> "header will contain classIndex/class's hash & format & numSlots/fixed size and finally fill value (nilObject)." - self break. headerReg := fillReg := SendNumArgsReg. "inst spec will hold class's instance specification, then byte size and finally end of new object." instSpecReg := byteSizeReg := ClassReg. "get freeStart as early as possible so as not to wait later..." cogit MoveAw: objectMemory freeStartAddress R: Arg1Reg. "get class's hash & fail if 0" self genGetHashFieldNonImmOf: ReceiverResultReg into: headerReg. jumpUnhashed := cogit JumpZero: 0. "get class's format inst var for both inst spec (format field) and num fixed fields" self genLoadSlot: InstanceSpecificationIndex sourceReg: ReceiverResultReg destReg: TempReg. self genConvertSmallIntegerToIntegerInReg: TempReg. cogit MoveR: TempReg R: instSpecReg. cogit LogicalShiftRightCq: objectMemory fixedFieldsFieldWidth R: TempReg. cogit AndCq: objectMemory formatMask R: TempReg. cogit AndCq: objectMemory fixedFieldsOfClassFormatMask R: instSpecReg. "fail if not fixed or if ephemeron (rare beasts so save the cycles)" cogit CmpCq: objectMemory nonIndexablePointerFormat R: TempReg. jumpVariableOrEphemeron := cogit JumpAbove: 0. cogit CmpCq: objectMemory numSlotsMask R: instSpecReg. jumpTooBig := cogit JumpAboveOrEqual: 0. "Add format to classIndex/format in header; the add in numSlots" cogit LogicalShiftLeftCq: objectMemory formatShift R: TempReg. cogit AddR: TempReg R: headerReg. cogit MoveR: instSpecReg R: TempReg. cogit LogicalShiftLeftCq: objectMemory numSlotsFullShift R: TempReg. cogit AddR: TempReg R: headerReg. "compute byte size; remember 0-sized objects still need 1 slot." cogit CmpCq: 0 R: byteSizeReg. "a.k.a. instSpecReg" jumpHasSlots := cogit JumpNonZero: 0. cogit MoveCq: objectMemory baseHeaderSize * 2 R: byteSizeReg. skip := cogit Jump: 0. "round up to allocationUnit" jumpHasSlots jmpTarget: (cogit AddCq: objectMemory baseHeaderSize / objectMemory wordSize R: byteSizeReg). cogit LogicalShiftLeftCq: objectMemory shiftForWord R: byteSizeReg. skip jmpTarget: "check if allocation fits (freeSize + byteSize < scavengeThreshold); scavengeThreshold is constant." (cogit AddR: Arg1Reg R: byteSizeReg). cogit CmpCq: objectMemory getScavengeThreshold R: byteSizeReg. jumpNoSpace := cogit JumpAboveOrEqual: 0. "write back new freeStart; get result. byteSizeReg holds new freeStart, the limit of the object" cogit MoveR: byteSizeReg Aw: objectMemory freeStartAddress. cogit MoveR: Arg1Reg R: ReceiverResultReg. "write header" cogit MoveR: headerReg Mw: 0 r: Arg1Reg. "now fill" cogit LoadEffectiveAddressMw: objectMemory baseHeaderSize r: ReceiverResultReg R: Arg1Reg. cogit MoveCq: objectMemory nilObject R: fillReg. fillLoop := cogit MoveR: fillReg Mw: 0 r: Arg1Reg. cogit AddCq: 8 R: Arg1Reg. cogit CmpR: Arg1Reg R: byteSizeReg. cogit JumpAbove: fillLoop. cogit RetN: retNoffset. jumpUnhashed jmpTarget: (jumpVariableOrEphemeron jmpTarget: (jumpTooBig jmpTarget: (jumpNoSpace jmpTarget: cogit Label))). ^0! Item was changed: ----- Method: CogObjectRepresentationFor64BitSpur>>genInnerPrimitiveNewWithArg: (in category 'primitive generators') ----- genInnerPrimitiveNewWithArg: retNoffset "Implement primitiveNewWithArg for convenient cases: - the receiver has a hash - the receiver is variable and not compiled method - single word header/num slots < numSlotsMask - the result fits in eden See superclass method for dynamic frequencies of formats. For the moment we implement only arrayFormat, firstByteFormat & firstLongFormat" | headerReg fillReg instSpecReg byteSizeReg maxSlots jumpArrayTooBig jumpByteTooBig jumpLongTooBig jumpArrayFormat jumpByteFormat jumpBytePrepDone jumpLongPrepDone jumpUnhashed jumpNElementsNonInt jumpFailCuzFixed jumpNoSpace jumpHasSlots fillLoop skip | <var: 'skip' type: #'AbstractInstruction *'> <var: 'fillLoop' type: #'AbstractInstruction *'> <var: 'jumpHasSlots' type: #'AbstractInstruction *'> <var: 'jumpNoSpace' type: #'AbstractInstruction *'> <var: 'jumpUnhashed' type: #'AbstractInstruction *'> <var: 'jumpByteFormat' type: #'AbstractInstruction *'> <var: 'jumpByteTooBig' type: #'AbstractInstruction *'> <var: 'jumpLongTooBig' type: #'AbstractInstruction *'> <var: 'jumpArrayFormat' type: #'AbstractInstruction *'> <var: 'jumpArrayTooBig' type: #'AbstractInstruction *'> <var: 'jumpFailCuzFixed' type: #'AbstractInstruction *'> <var: 'jumpBytePrepDone' type: #'AbstractInstruction *'> <var: 'jumpLongPrepDone' type: #'AbstractInstruction *'> <var: 'jumpNElementsNonInt' type: #'AbstractInstruction *'> "header will contain classIndex/class's hash & format & numSlots/fixed size" - self break. headerReg := SendNumArgsReg. "Assume there's an available scratch register on 64-bit machines" fillReg := Scratch0Reg. self assert: (cogit backEnd concreteRegister: fillReg) > 0. "inst spec will hold class's instance specification and then byte size" instSpecReg := byteSizeReg := ClassReg. "The max slots we'll allocate here are those for a single header" maxSlots := objectMemory numSlotsMask - 1. "get freeStart as early as possible so as not to wait later..." cogit MoveAw: objectMemory freeStartAddress R: Arg1Reg. "get class's hash & fail if 0" self genGetHashFieldNonImmOf: ReceiverResultReg into: headerReg. jumpUnhashed := cogit JumpZero: 0. "get index and fail if not a +ve integer" jumpNElementsNonInt := self genJumpNotSmallInteger: Arg0Reg. jumpNElementsNonInt asInteger = UnimplementedOperation ifTrue: [cogit MoveR: Arg0Reg R: TempReg. jumpNElementsNonInt := self genJumpNotSmallIntegerInScratchReg: TempReg]. "get class's format inst var for inst spec (format field)" self genLoadSlot: InstanceSpecificationIndex sourceReg: ReceiverResultReg destReg: instSpecReg. cogit LogicalShiftRightCq: objectMemory fixedFieldsFieldWidth + self numSmallIntegerTagBits R: instSpecReg. cogit AndCq: objectMemory formatMask R: instSpecReg. "Add format to classIndex/format header now" cogit MoveR: instSpecReg R: TempReg. cogit LogicalShiftLeftCq: objectMemory formatShift R: TempReg. cogit AddR: TempReg R: headerReg. "get integer value of num fields in TempReg now" cogit MoveR: Arg0Reg R: TempReg. self genConvertSmallIntegerToIntegerInReg: TempReg. "dispatch on format, failing if not variable or if compiled method" cogit CmpCq: objectMemory arrayFormat R: instSpecReg. jumpArrayFormat := cogit JumpZero: 0. cogit CmpCq: objectMemory firstByteFormat R: instSpecReg. jumpByteFormat := cogit JumpZero: 0. cogit CmpCq: objectMemory firstLongFormat R: instSpecReg. jumpFailCuzFixed := cogit JumpNonZero: 0. cogit CmpCq: (objectMemory integerObjectOf: maxSlots) R: Arg0Reg. jumpLongTooBig := cogit JumpAbove: 0. "save num elements/slot size to instSpecReg" cogit MoveR: TempReg R: instSpecReg. cogit MoveCq: 0 R: fillReg. jumpLongPrepDone := cogit Jump: 0. "go allocate" jumpByteFormat jmpTarget: (cogit CmpCq: (objectMemory integerObjectOf: maxSlots * objectMemory wordSize) R: Arg0Reg). jumpByteTooBig := cogit JumpAbove: 0. "save num elements to instSpecReg" cogit MoveR: TempReg R: instSpecReg. "compute odd bits and add into headerReg; oddBits := 4 - nElements bitAnd: 3" cogit MoveCq: objectMemory wordSize R: TempReg. cogit SubR: instSpecReg R: TempReg. cogit AndCq: objectMemory wordSize - 1 R: TempReg. cogit LogicalShiftLeftCq: objectMemory formatShift R: TempReg. cogit AddR: TempReg R: headerReg. "round up num elements to numSlots in instSpecReg" cogit AddCq: objectMemory wordSize - 1 R: instSpecReg. cogit LogicalShiftRightCq: objectMemory shiftForWord R: instSpecReg. "store numSlots to headerReg" cogit MoveR: instSpecReg R: TempReg. cogit LogicalShiftLeftCq: objectMemory numSlotsFullShift R: TempReg. cogit AddR: TempReg R: headerReg. cogit MoveCq: 0 R: fillReg. jumpBytePrepDone := cogit Jump: 0. "go allocate" jumpArrayFormat jmpTarget: (cogit CmpCq: (objectMemory integerObjectOf: maxSlots) R: Arg0Reg). jumpArrayTooBig := cogit JumpAbove: 0. "save num elements/slot size to instSpecReg" cogit MoveR: TempReg R: instSpecReg. cogit MoveCq: objectMemory nilObject R: fillReg. "fall through to allocate" jumpBytePrepDone jmpTarget: (jumpLongPrepDone jmpTarget: cogit Label). "store numSlots to headerReg" cogit MoveR: instSpecReg R: TempReg. cogit LogicalShiftLeftCq: objectMemory numSlotsFullShift R: TempReg. cogit AddR: TempReg R: headerReg. "compute byte size; remember 0-sized objects still need 1 slot." cogit CmpCq: 0 R: byteSizeReg. "a.k.a. instSpecReg" jumpHasSlots := cogit JumpNonZero: 0. cogit MoveCq: objectMemory baseHeaderSize * 2 R: byteSizeReg. skip := cogit Jump: 0. "round up to allocationUnit" jumpHasSlots jmpTarget: (cogit MoveR: byteSizeReg R: TempReg). cogit AddR: TempReg R: byteSizeReg. cogit AddCq: objectMemory baseHeaderSize / objectMemory wordSize R: byteSizeReg. cogit LogicalShiftLeftCq: objectMemory shiftForWord R: byteSizeReg. skip jmpTarget: "check if allocation fits" (cogit AddR: Arg1Reg R: byteSizeReg). cogit CmpCq: objectMemory getScavengeThreshold R: byteSizeReg. jumpNoSpace := cogit JumpAboveOrEqual: 0. "get result, increment freeStart and write it back. Arg1Reg holds new freeStart, the limit of the object" cogit MoveR: Arg1Reg R: ReceiverResultReg. cogit MoveR: byteSizeReg Aw: objectMemory freeStartAddress. "write other half of header (numSlots/0 identityHash)" cogit MoveR: headerReg Mw: 0 r: ReceiverResultReg. "now fill" cogit LoadEffectiveAddressMw: objectMemory baseHeaderSize r: ReceiverResultReg R: Arg1Reg. fillLoop := cogit MoveR: fillReg Mw: 0 r: Arg1Reg. cogit AddCq: 8 R: Arg1Reg. cogit CmpR: Arg1Reg R: byteSizeReg. cogit JumpAbove: fillLoop. cogit RetN: retNoffset. jumpNoSpace jmpTarget: (jumpUnhashed jmpTarget: (jumpFailCuzFixed jmpTarget: (jumpArrayTooBig jmpTarget: (jumpByteTooBig jmpTarget: (jumpLongTooBig jmpTarget: (jumpNElementsNonInt jmpTarget: cogit Label)))))). ^0! Item was changed: ----- Method: CogX64Compiler>>computeMaximumSize (in category 'generate machine code') ----- computeMaximumSize "Compute the maximum size for each opcode. This allows jump offsets to be determined, provided that all backward branches are long branches." "N.B. The ^N forms are to get around the bytecode compiler's long branch limits which are exceeded when each case jumps around the otherwise." opcode caseOf: { "Noops & Pseudo Ops" [Label] -> [^0]. [AlignmentNops] -> [^(operands at: 0) - 1]. [Fill16] -> [^2]. [Fill32] -> [^4]. [FillFromWord] -> [^4]. [Nop] -> [^1]. "Specific Control/Data Movement" [CDQ] -> [^2]. [IDIVR] -> [^3]. [IMULRR] -> [^4]. [CPUID] -> [^2]. [CMPXCHGAwR] -> [^8]. [CMPXCHGMwrR] -> [^9]. [LFENCE] -> [^3]. [MFENCE] -> [^3]. [SFENCE] -> [^3]. [LOCK] -> [^1]. "[XCHGAwR] -> [^6]. [XCHGMwrR] -> [^7]." [XCHGRR] -> [^((self concreteRegister: (operands at: 0)) = RAX or: [(self concreteRegister: (operands at: 1)) = RAX]) ifTrue: [2] ifFalse: [3]]. "Control" [CallFull] -> [^12]. [Call] -> [^5]. [JumpR] -> [^2]. [JumpFull] -> [self resolveJumpTarget. ^12]. [JumpLong] -> [self resolveJumpTarget. ^5]. [Jump] -> [self resolveJumpTarget. ^5]. [JumpZero] -> [self resolveJumpTarget. ^6]. [JumpNonZero] -> [self resolveJumpTarget. ^6]. [JumpNegative] -> [self resolveJumpTarget. ^6]. [JumpNonNegative] -> [self resolveJumpTarget. ^6]. [JumpOverflow] -> [self resolveJumpTarget. ^6]. [JumpNoOverflow] -> [self resolveJumpTarget. ^6]. [JumpCarry] -> [self resolveJumpTarget. ^6]. [JumpNoCarry] -> [self resolveJumpTarget. ^6]. [JumpLess] -> [self resolveJumpTarget. ^6]. [JumpGreaterOrEqual] -> [self resolveJumpTarget. ^6]. [JumpGreater] -> [self resolveJumpTarget. ^6]. [JumpLessOrEqual] -> [self resolveJumpTarget. ^6]. [JumpBelow] -> [self resolveJumpTarget. ^6]. [JumpAboveOrEqual] -> [self resolveJumpTarget. ^6]. [JumpAbove] -> [self resolveJumpTarget. ^6]. [JumpBelowOrEqual] -> [self resolveJumpTarget. ^6]. [JumpLongZero] -> [self resolveJumpTarget. ^6]. [JumpLongNonZero] -> [self resolveJumpTarget. ^6]. [JumpFPEqual] -> [self resolveJumpTarget. ^6]. [JumpFPNotEqual] -> [self resolveJumpTarget. ^6]. [JumpFPLess] -> [self resolveJumpTarget. ^6]. [JumpFPGreaterOrEqual] -> [self resolveJumpTarget. ^6]. [JumpFPGreater] -> [self resolveJumpTarget. ^6]. [JumpFPLessOrEqual] -> [self resolveJumpTarget. ^6]. [JumpFPOrdered] -> [self resolveJumpTarget. ^6]. [JumpFPUnordered] -> [self resolveJumpTarget. ^6]. [RetN] -> [^(operands at: 0) = 0 ifTrue: [1] ifFalse: [3]]. [Stop] -> [^1]. "Arithmetic" [AddCqR] -> [^self computeSizeOfArithCqR]. [AndCqR] -> [^self computeSizeOfArithCqR]. [CmpCqR] -> [^self computeSizeOfArithCqR]. [OrCqR] -> [^self computeSizeOfArithCqR]. [SubCqR] -> [^self computeSizeOfArithCqR]. [TstCqR] -> [^self computeSizeOfArithCqR]. [AddCwR] -> [^self computeSizeOfArithCwR]. [AndCwR] -> [^self computeSizeOfArithCwR]. [CmpCwR] -> [^self computeSizeOfArithCwR]. [OrCwR] -> [^self computeSizeOfArithCwR]. [SubCwR] -> [^self computeSizeOfArithCwR]. [XorCwR] -> [^self computeSizeOfArithCwR]. [AddRR] -> [^3]. [AndRR] -> [^3]. [CmpRR] -> [^3]. [OrRR] -> [^3]. [XorRR] -> [^3]. [SubRR] -> [^3]. [NegateR] -> [^3]. [LoadEffectiveAddressMwrR] -> [^((self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]) + (((self concreteRegister: (operands at: 1)) bitAnd: 7) = RSP ifTrue: [1] ifFalse: [0])]. [LogicalShiftLeftCqR] -> [^(operands at: 0) = 1 ifTrue: [3] ifFalse: [4]]. [LogicalShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [3] ifFalse: [4]]. [ArithmeticShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [3] ifFalse: [4]]. [LogicalShiftLeftRR] -> [^self computeShiftRRSize]. [LogicalShiftRightRR] -> [^self computeShiftRRSize]. [ArithmeticShiftRightRR] -> [^self computeShiftRRSize]. [AddRdRd] -> [^4]. [CmpRdRd] -> [^4]. [SubRdRd] -> [^4]. [MulRdRd] -> [^4]. [DivRdRd] -> [^4]. [SqrtRd] -> [^4]. "Data Movement" [MoveCqR] -> [^(operands at: 0) = 0 ifTrue: [3] ifFalse: [(self is32BitSignedImmediate: (operands at: 0)) ifTrue: [7] ifFalse: [self moveCwRByteSize]]]. [MoveCwR] -> [^(self inCurrentCompilation: (operands at: 0)) ifTrue: [7] ifFalse: [self moveCwRByteSize]]. [MoveC32R] -> [^7]. "N.B. Always inlined." [MoveRR] -> [^3]. [MoveRdRd] -> [^4]. [MoveAwR] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) ifTrue: [7] ifFalse: [(self concreteRegister: (operands at: 1)) = RAX ifTrue: [10] ifFalse: [14]]]. [MoveRAw] -> [^(self isAddressRelativeToVarBase: (operands at: 1)) ifTrue: [7] ifFalse: [(self concreteRegister: (operands at: 0)) = RAX ifTrue: [10] ifFalse: [14]]]. + [MoveAbR] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) + ifTrue: [7] + ifFalse: [(self concreteRegister: (operands at: 1)) = RAX ifTrue: [10] ifFalse: [14]]]. + [MoveRAb] -> [^(self isAddressRelativeToVarBase: (operands at: 1)) + ifTrue: [7] + ifFalse: [(self concreteRegister: (operands at: 0)) = RAX ifTrue: [10] ifFalse: [14]]]. + [MoveRMwr] -> [self assert: (self is32BitSignedImmediate: (operands at: 1)). + ^((self isQuick: (operands at: 1)) - [MoveRMwr] -> [^((self isQuick: (operands at: 1)) ifTrue: [((operands at: 1) = 0 and: [((self concreteRegister: (operands at: 2)) bitAnd: 7) ~= RBP]) ifTrue: [3] ifFalse: [4]] ifFalse: [7]) + (((self concreteRegister: (operands at: 2)) bitAnd: 7) = RSP ifTrue: [1] ifFalse: [0])]. "[MoveRdM64r] -> [^((self isQuick: (operands at: 1)) ifTrue: [5] ifFalse: [8]) + ((self concreteRegister: (operands at: 2)) = ESP ifTrue: [1] ifFalse: [0])]." + [MoveMbrR] -> [self assert: (self is32BitSignedImmediate: (operands at: 0)). + ^((self isQuick: (operands at: 0)) - [MoveMbrR] -> [^((self isQuick: (operands at: 0)) ifTrue: [((operands at: 0) = 0 and: [((self concreteRegister: (operands at: 1)) bitAnd: 7) ~= RBP]) ifTrue: [4] ifFalse: [5]] ifFalse: [8]) + (((self concreteRegister: (operands at: 1)) bitAnd: 7) = RSP ifTrue: [1] ifFalse: [0])]. + [MoveRMbr] -> [self assert: (self is32BitSignedImmediate: (operands at: 1)). + ^((self isQuick: (operands at: 1)) - [MoveRMbr] -> [^((self isQuick: (operands at: 1)) ifTrue: [((operands at: 1) = 0 and: [((self concreteRegister: (operands at: 0)) bitAnd: 7) ~= RBP]) ifTrue: [3] ifFalse: [4]] ifFalse: [7]) + (((self concreteRegister: (operands at: 2)) bitAnd: 7) = RSP ifTrue: [1] ifFalse: [0])]. [MoveM16rR] -> [^((self isQuick: (operands at: 0)) ifTrue: [((operands at: 0) = 0 and: [((self concreteRegister: (operands at: 1)) bitAnd: 7) ~= RBP]) ifTrue: [4] ifFalse: [5]] ifFalse: [8]) + (((self concreteRegister: (operands at: 1)) bitAnd: 7) = RSP ifTrue: [1] ifFalse: [0])]. "[MoveM64rRd] -> [^((self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]) + ((self concreteRegister: (operands at: 1)) = ESP ifTrue: [1] ifFalse: [0])]." + [MoveMwrR] -> [self assert: (self is32BitSignedImmediate: (operands at: 0)). + ^((self isQuick: (operands at: 0)) - [MoveMwrR] -> [^((self isQuick: (operands at: 0)) ifTrue: [((operands at: 0) = 0 and: [((self concreteRegister: (operands at: 1)) bitAnd: 7) ~= RBP]) ifTrue: [3] ifFalse: [4]] ifFalse: [7]) + (((self concreteRegister: (operands at: 1)) bitAnd: 7) = RSP ifTrue: [1] ifFalse: [0])]. [MoveXbrRR] -> [self assert: (self concreteRegister: (operands at: 0)) ~= RSP. ^((self concreteRegister: (operands at: 1)) bitAnd: 7) = RBP ifTrue: [6] ifFalse: [5]]. [MoveRXbrR] -> [self assert: (self concreteRegister: (operands at: 1)) ~= RSP. ^(((self concreteRegister: (operands at: 0)) < 8 and: [(self concreteRegister: (operands at: 1)) < 8 and: [(self concreteRegister: (operands at: 2)) < 8]]) ifTrue: [3] ifFalse: [4]) + (((self concreteRegister: (operands at: 2)) bitAnd: 7) = RBP ifTrue: [1] ifFalse: [0])]. [MoveXwrRR] -> [self assert: (self concreteRegister: (operands at: 0)) ~= RSP. ^((self concreteRegister: (operands at: 1)) = RBP or: [(self concreteRegister: (operands at: 1)) = R13]) ifTrue: [5] ifFalse: [4]]. [MoveRXwrR] -> [self assert: (self concreteRegister: (operands at: 1)) ~= RSP. ^((self concreteRegister: (operands at: 2)) = RBP or: [(self concreteRegister: (operands at: 2)) = R13]) ifTrue: [5] ifFalse: [4]]. [PopR] -> [^(self concreteRegister: (operands at: 0)) < 8 ifTrue: [1] ifFalse: [2]]. [PushR] -> [^(self concreteRegister: (operands at: 0)) < 8 ifTrue: [1] ifFalse: [2]]. [PushCq] -> [^(self isQuick: (operands at: 0)) ifTrue: [2] ifFalse: [5]]. [PushCw] -> [^(self inCurrentCompilation: (operands at: 0)) + ifTrue: [9] - ifTrue: [6] ifFalse: [self pushCwByteSize]]. [PrefetchAw] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) ifTrue: [7] ifFalse: [0]]. "Conversion" "[ConvertRRd] -> [^4]" }. ^0 "to keep C compiler quiet"! Item was added: + ----- Method: CogX64Compiler>>concretizeMoveAbR (in category 'generate machine code') ----- + concretizeMoveAbR + "Will get inlined into concretizeAt: switch." + <inline: true> + | addressOperand reg offset save0 save1 | + addressOperand := operands at: 0. + (self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue: + [addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address]. + (self isAddressRelativeToVarBase: addressOperand) ifTrue: + [save0 := operands at: 0. + save1 := operands at: 1. + operands + at: 0 put: addressOperand - cogit varBaseAddress; + at: 1 put: RBX; + at: 2 put: save1. + self concretizeMoveMbrR. + operands + at: 0 put: save0; + at: 1 put: save1; + at: 2 put: 0. + ^machineCodeSize]. + reg := self concreteRegister: (operands at: 1). + reg = RAX + ifTrue: [offset := 0] + ifFalse: + [machineCode + at: 0 put: (self rexR: 0 x: 0 b: reg); + at: 1 put: 16r90 + (reg \\ 8). + offset := 2]. + machineCode + at: 0 + offset put: 16r48; + at: 1 + offset put: 16rA0; + at: 2 + offset put: (addressOperand bitAnd: 16rFF); + at: 3 + offset put: (addressOperand >> 8 bitAnd: 16rFF); + at: 4 + offset put: (addressOperand >> 16 bitAnd: 16rFF); + at: 5 + offset put: (addressOperand >> 24 bitAnd: 16rFF); + at: 6 + offset put: (addressOperand >> 32 bitAnd: 16rFF); + at: 7 + offset put: (addressOperand >> 40 bitAnd: 16rFF); + at: 8 + offset put: (addressOperand >> 48 bitAnd: 16rFF); + at: 9 + offset put: (addressOperand >> 56 bitAnd: 16rFF). + reg = RAX ifTrue: + [^machineCodeSize := 10]. + machineCode + at: 12 put: (machineCode at: 0); + at: 13 put: (machineCode at: 1). + ^machineCodeSize := 14! Item was added: + ----- Method: CogX64Compiler>>concretizeMoveRAb (in category 'generate machine code') ----- + concretizeMoveRAb + "Will get inlined into concretizeAt: switch." + <inline: true> + | addressOperand reg offset save1 | + reg := self concreteRegister: (operands at: 0). + addressOperand := operands at: 1. + (self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue: + [addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address]. + (self isAddressRelativeToVarBase: addressOperand) ifTrue: + [save1 := operands at: 1. + operands + at: 1 put: addressOperand - cogit varBaseAddress; + at: 2 put: RBX. + self concretizeMoveRMbr. + operands + at: 1 put: save1; + at: 2 put: 0. + ^machineCodeSize]. + reg = RAX + ifTrue: [offset := 0] + ifFalse: + [machineCode + at: 0 put: (self rexR: 0 x: 0 b: reg); + at: 1 put: 16r90 + (reg \\ 8). + offset := 2]. + machineCode + at: 0 + offset put: 16r48; + at: 1 + offset put: 16rA2; + at: 2 + offset put: (addressOperand bitAnd: 16rFF); + at: 3 + offset put: (addressOperand >> 8 bitAnd: 16rFF); + at: 4 + offset put: (addressOperand >> 16 bitAnd: 16rFF); + at: 5 + offset put: (addressOperand >> 24 bitAnd: 16rFF); + at: 6 + offset put: (addressOperand >> 32 bitAnd: 16rFF); + at: 7 + offset put: (addressOperand >> 40 bitAnd: 16rFF); + at: 8 + offset put: (addressOperand >> 48 bitAnd: 16rFF); + at: 9 + offset put: (addressOperand >> 56 bitAnd: 16rFF). + reg = RAX ifTrue: + [^machineCodeSize := 10]. + machineCode + at: 12 put: (machineCode at: 0); + at: 13 put: (machineCode at: 1). + ^machineCodeSize := 14! Item was changed: ----- Method: CogX64Compiler>>dispatchConcretize (in category 'generate machine code') ----- dispatchConcretize "Attempt to generate concrete machine code for the instruction at address. This is the inner dispatch of concretizeAt: actualAddress which exists only to get around the branch size limits in the SqueakV3 (blue book derived) bytecode set." <returnTypeC: #void> opcode caseOf: { "Noops & Pseudo Ops" [Label] -> [^self concretizeLabel]. [AlignmentNops] -> [^self concretizeAlignmentNops]. [Fill16] -> [^self concretizeFill16]. [Fill32] -> [^self concretizeFill32]. [FillFromWord] -> [^self concretizeFillFromWord]. [Nop] -> [^self concretizeNop]. "Specific Control/Data Movement" [CDQ] -> [^self concretizeCDQ]. [IDIVR] -> [^self concretizeIDIVR]. [IMULRR] -> [^self concretizeMulRR]. [CPUID] -> [^self concretizeCPUID]. [CMPXCHGAwR] -> [^self concretizeCMPXCHGAwR]. [CMPXCHGMwrR] -> [^self concretizeCMPXCHGMwrR]. [LFENCE] -> [^self concretizeFENCE: 5]. [MFENCE] -> [^self concretizeFENCE: 6]. [SFENCE] -> [^self concretizeFENCE: 7]. [LOCK] -> [^self concretizeLOCK]. [XCHGAwR] -> [^self concretizeXCHGAwR]. [XCHGMwrR] -> [^self concretizeXCHGMwrR]. [XCHGRR] -> [^self concretizeXCHGRR]. "Control" [Call] -> [^self concretizeCall]. [CallFull] -> [^self concretizeCallFull]. [JumpR] -> [^self concretizeJumpR]. [JumpFull] -> [^self concretizeJumpFull]. [JumpLong] -> [^self concretizeJumpLong]. [JumpLongZero] -> [^self concretizeConditionalJump: 16r4]. [JumpLongNonZero] -> [^self concretizeConditionalJump: 16r5]. [Jump] -> [^self concretizeJump]. "Table B-1 Intel¬Æ 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture" [JumpZero] -> [^self concretizeConditionalJump: 16r4]. [JumpNonZero] -> [^self concretizeConditionalJump: 16r5]. [JumpNegative] -> [^self concretizeConditionalJump: 16r8]. [JumpNonNegative] -> [^self concretizeConditionalJump: 16r9]. [JumpOverflow] -> [^self concretizeConditionalJump: 16r0]. [JumpNoOverflow] -> [^self concretizeConditionalJump: 16r1]. [JumpCarry] -> [^self concretizeConditionalJump: 16r2]. [JumpNoCarry] -> [^self concretizeConditionalJump: 16r3]. [JumpLess] -> [^self concretizeConditionalJump: 16rC]. [JumpGreaterOrEqual] -> [^self concretizeConditionalJump: 16rD]. [JumpGreater] -> [^self concretizeConditionalJump: 16rF]. [JumpLessOrEqual] -> [^self concretizeConditionalJump: 16rE]. [JumpBelow] -> [^self concretizeConditionalJump: 16r2]. [JumpAboveOrEqual] -> [^self concretizeConditionalJump: 16r3]. [JumpAbove] -> [^self concretizeConditionalJump: 16r7]. [JumpBelowOrEqual] -> [^self concretizeConditionalJump: 16r6]. [JumpFPEqual] -> [^self concretizeConditionalJump: 16r4]. [JumpFPNotEqual] -> [^self concretizeConditionalJump: 16r5]. [JumpFPLess] -> [^self concretizeConditionalJump: 16r2]. [JumpFPGreaterOrEqual] -> [^self concretizeConditionalJump: 16r3]. [JumpFPGreater] -> [^self concretizeConditionalJump: 16r7]. [JumpFPLessOrEqual] -> [^self concretizeConditionalJump: 16r6]. [JumpFPOrdered] -> [^self concretizeConditionalJump: 16rB]. [JumpFPUnordered] -> [^self concretizeConditionalJump: 16rA]. [RetN] -> [^self concretizeRetN]. [Stop] -> [^self concretizeStop]. "Arithmetic" [AddCqR] -> [^self concretizeArithCqRWithRO: 0 raxOpcode: 15r05]. [AddCwR] -> [^self concretizeArithCwR: 16r03]. [AddRR] -> [^self concretizeAddRR]. [AddRdRd] -> [^self concretizeSEE2OpRdRd: 16r58]. [AndCqR] -> [^self concretizeArithCqRWithRO: 4 raxOpcode: 16r25]. [AndCwR] -> [^self concretizeArithCwR: 16r23]. [AndRR] -> [^self concretizeAndRR]. [TstCqR] -> [^self concretizeTstCqR]. [CmpCqR] -> [^self concretizeArithCqRWithRO: 7 raxOpcode: 16r3D]. [CmpCwR] -> [^self concretizeArithCwR: 16r39]. [CmpRR] -> [^self concretizeCmpRR]. [CmpRdRd] -> [^self concretizeCmpRdRd]. [DivRdRd] -> [^self concretizeSEE2OpRdRd: 16r5E]. [MulRdRd] -> [^self concretizeSEE2OpRdRd: 16r59]. [OrCqR] -> [^self concretizeArithCqRWithRO: 1 raxOpcode: 16r0D]. [OrCwR] -> [^self concretizeArithCwR: 16r0B]. [OrRR] -> [^self concretizeOrRR]. [SubCqR] -> [^self concretizeArithCqRWithRO: 5 raxOpcode: 16r2D]. [SubCwR] -> [^self concretizeArithCwR: 16r2B]. [SubRR] -> [^self concretizeSubRR]. [SubRdRd] -> [^self concretizeSEE2OpRdRd: 16r5C]. [SqrtRd] -> [^self concretizeSqrtRd]. [XorCwR] -> [^self concretizeArithCwR: 16r33]. [XorRR] -> [^self concretizeXorRR]. [NegateR] -> [^self concretizeNegateR]. [LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR]. [ArithmeticShiftRightCqR] -> [^self concretizeShiftCqRegOpcode: 7]. [LogicalShiftRightCqR] -> [^self concretizeShiftCqRegOpcode: 5]. [LogicalShiftLeftCqR] -> [^self concretizeShiftCqRegOpcode: 4]. [ArithmeticShiftRightRR] -> [^self concretizeShiftRegRegOpcode: 7]. [LogicalShiftLeftRR] -> [^self concretizeShiftRegRegOpcode: 4]. "Data Movement" [MoveCqR] -> [^self concretizeMoveCqR]. [MoveCwR] -> [^self concretizeMoveCwR]. + [MoveC32R] -> [^self concretizeMoveC32R]. - [MoveC32R] -> [^self concretizeMoveC32R]. [MoveRR] -> [^self concretizeMoveRR]. [MoveAwR] -> [^self concretizeMoveAwR]. [MoveRAw] -> [^self concretizeMoveRAw]. + [MoveAbR] -> [^self concretizeMoveAbR]. + [MoveRAb] -> [^self concretizeMoveRAb]. [MoveMbrR] -> [^self concretizeMoveMbrR]. [MoveRMbr] -> [^self concretizeMoveRMbr]. [MoveM16rR] -> [^self concretizeMoveM16rR]. [MoveM64rRd] -> [^self concretizeMoveM64rRd]. [MoveMwrR] -> [^self concretizeMoveMwrR]. [MoveXbrRR] -> [^self concretizeMoveXbrRR]. [MoveRXbrR] -> [^self concretizeMoveRXbrR]. [MoveXwrRR] -> [^self concretizeMoveXwrRR]. [MoveRXwrR] -> [^self concretizeMoveRXwrR]. [MoveRMwr] -> [^self concretizeMoveRMwr]. [MoveRdM64r] -> [^self concretizeMoveRdM64r]. [PopR] -> [^self concretizePopR]. [PushR] -> [^self concretizePushR]. [PushCq] -> [^self concretizePushCq]. [PushCw] -> [^self concretizePushCw]. [PrefetchAw] -> [^self concretizePrefetchAw]. "Conversion" [ConvertRRd] -> [^self concretizeConvertRRd] }! Item was added: + ----- Method: CogX64CompilerTests>>addressIsInCurrentCompilation: (in category 'accessing') ----- + addressIsInCurrentCompilation: address + ^self currentCompilationBase <= address + and: [address - self currentCompilationBase < 1024]! Item was added: + ----- Method: CogX64CompilerTests>>currentCompilationBase (in category 'accessing') ----- + currentCompilationBase + ^16r8000! Item was added: + ----- Method: CogX64CompilerTests>>testMoveAbR (in category 'tests') ----- + testMoveAbR + "self neb testMoveAbR" + self concreteCompilerClass byteRegistersWithNamesDo: + [:reg :regname| | reg64name | + reg64name := self processor registerStateGetters at: reg + 1. + #(16r555555 16rAAAAAA 16r5A5A5A5A5A5A) do: + [:addr| | inst len totalsz | + inst := self gen: MoveAbR operand: addr operand: reg. + len := inst concretizeAt: 0. + totalsz := 0. + regname ~= '%al' ifTrue: + [self processor + disassembleInstructionAt: 0 + In: inst machineCode object + into: [:str :sz| | plainJane herIntended | + plainJane := self strip: str. + herIntended := 'xchgq %rax, %', reg64name. + self assert: (plainJane match: herIntended). + totalsz := sz]]. + self processor + disassembleInstructionAt: totalsz + In: inst machineCode object + into: [:str :sz| | plainJane herIntended | + plainJane := self strip: str. + herIntended := 'movb 0x', (addr printStringBase: 16 length: 16 padded: true), ', %al'. + self assert: (plainJane match: herIntended). + totalsz := totalsz + sz]. + regname ~= '%al' ifTrue: + [self processor + disassembleInstructionAt: totalsz + In: inst machineCode object + into: [:str :sz| | plainJane herIntended | + plainJane := self strip: str. + herIntended := 'xchgq %rax, %', reg64name. + self assert: (plainJane match: herIntended). + totalsz := totalsz + sz]]. + self assert: len = totalsz]]! Item was added: + ----- Method: CogX64CompilerTests>>testMoveRAb (in category 'tests') ----- + testMoveRAb + "self new testMoveRAb" + self concreteCompilerClass byteRegistersWithNamesDo: + [:reg :regname| | reg64name | + reg64name := self processor registerStateGetters at: reg + 1. + #(16r555555 16rAAAAAA 16r5A5A5A5A5A5A) do: + [:addr| | inst len totalsz | + inst := self gen: MoveRAb operand: reg operand: addr. + len := inst concretizeAt: 0. + totalsz := 0. + regname ~= '%al' ifTrue: + [self processor + disassembleInstructionAt: 0 + In: inst machineCode object + into: [:str :sz| | plainJane herIntended | + plainJane := self strip: str. + herIntended := 'xchgq %rax, %', reg64name. + self assert: (plainJane match: herIntended). + totalsz := sz]]. + self processor + disassembleInstructionAt: totalsz + In: inst machineCode object + into: [:str :sz| | plainJane herIntended | + plainJane := self strip: str. + herIntended := 'movb %al, 0x', (addr printStringBase: 16 length: 16 padded: true). + self assert: (plainJane match: herIntended). + totalsz := totalsz + sz]. + regname ~= '%al' ifTrue: + [self processor + disassembleInstructionAt: totalsz + In: inst machineCode object + into: [:str :sz| | plainJane herIntended | + plainJane := self strip: str. + herIntended := 'xchgq %rax, %', reg64name. + self assert: (plainJane match: herIntended). + totalsz := totalsz + sz]]. + self assert: len = totalsz]]! Item was added: + ----- Method: CogX64CompilerTests>>testMoveRIPRelativeCwR (in category 'as yet unclassified') ----- + testMoveRIPRelativeCwR + "test rip-relative constant generation" + "self new testMoveRIPRelativeCwR" + + | memory | + memory := ByteArray new: 16. + {self currentCompilationBase. self currentCompilationBase + 512} do: + [:n| | inst len | + self concreteCompilerClass dataRegistersWithAccessorsDo: + [ :r :rgetter :rset | + inst := self gen: MoveCwR operand: n operand: r. + len := inst concretizeAt: 0. + memory replaceFrom: 1 to: len with: inst machineCode object startingAt: 1. + self processor + reset. + [[processor pc < len] whileTrue: + [self processor singleStepIn: memory]] + on: Error + do: [:ex| ]. + self concreteCompilerClass dataRegistersWithAccessorsDo: + [:ireg :getter :setter| | expected | + expected := getter == rgetter ifTrue: [n] ifFalse: [0]. + self assert: (self processor perform: getter) = expected]. + self assert: self processor pc = inst machineCodeSize]] + + "processor disassembleFrom: 0 to: inst machineCodeSize in: memory on: Transcript"! Item was added: + ----- Method: Cogit>>MoveAb:R: (in category 'abstract instructions') ----- + MoveAb: address R: reg + <inline: true> + <returnTypeC: #'AbstractInstruction *'> + ^self gen: MoveAbR literal: address operand: reg! Item was added: + ----- Method: Cogit>>MoveR:Ab: (in category 'abstract instructions') ----- + MoveR: reg Ab: address + <inline: true> + <returnTypeC: #'AbstractInstruction *'> + ^self gen: MoveRAb operand: reg literal: address! Item was changed: ----- Method: Cogit>>addressIsInInstructions: (in category 'testing') ----- addressIsInInstructions: address <var: #address type: #'AbstractInstruction *'> + ^self cCode: '!!((unsigned)(address) & BytesPerWord-1) \ - ^self cCode: '!!((((unsigned)address) & BytesPerWord-1)) \ && (address) >= &abstractOpcodes[0] \ && (address) < &abstractOpcodes[opcodeIndex]' inSmalltalk: [(abstractOpcodes object identityIndexOf: address) between: 1 and: opcodeIndex]! Item was changed: ----- Method: SimpleStackBasedCogit>>genFastPrimTraceUsing:and: (in category 'primitive generators') ----- genFastPrimTraceUsing: r1 and: r2 "Suport for compileInterpreterPrimitive. Generate inline code so as to record the primitive trace as fast as possible." + self MoveAb: coInterpreter primTraceLogIndexAddress R: r2. - self MoveCq: 0 R: TempReg. - "Too lazy to add MoveAbR and MoveRAb, so misuse MoveMbrR and MoveRMbr" - self MoveMb: coInterpreter primTraceLogIndexAddress r: TempReg R: r2. self MoveR: r2 R: r1. self AddCq: 1 R: r1. + self MoveR: r1 Ab: coInterpreter primTraceLogIndexAddress. - self MoveR: r1 Mb: coInterpreter primTraceLogIndexAddress r: TempReg. methodLabel addDependent: (self annotateAbsolutePCRef: (self MoveCw: methodLabel asInteger R: r1)). self MoveMw: (self offset: CogMethod of: #selector) r: r1 R: TempReg. self MoveCw: coInterpreter primTraceLogAddress asInteger R: r1. self MoveR: TempReg Xwr: r2 R: r1! Item was changed: ----- Method: ThreadedFFIPlugin>>ffiAddressOf:startingAt:size: (in category 'primitive support') ----- ffiAddressOf: rcvr startingAt: byteOffset size: byteSize "return an int of the address of the byteSize slot (byte, short, int, whatever) at byteOffset in rcvr. Nominally intended for use with ExternalAddress objects, this code will work (for obscure historical reasons) with plain Byte or Word Arrays as well. " | rcvrClass rcvrSize addr | + self flag: 'This needs more thought. It is 32-bit specific. What about 64-bit platforms?'. (interpreterProxy isBytes: rcvr) ifFalse:[^interpreterProxy primitiveFail]. (byteOffset > 0) ifFalse:[^interpreterProxy primitiveFail]. rcvrClass := interpreterProxy fetchClassOf: rcvr. rcvrSize := interpreterProxy byteSizeOf: rcvr. rcvrClass = interpreterProxy classExternalAddress ifTrue:[ (rcvrSize = 4) ifFalse:[^interpreterProxy primitiveFail]. addr := interpreterProxy fetchPointer: 0 ofObject: rcvr. + self flag: 'This needs more thought. Instead of always allowing this couldn''t we allow it only if the address is associated with a pinned object?'. "don't you dare to read from object memory!!" + (addr = 0 "or: [interpreterProxy isInMemory: addr]") - (addr == 0 "or:[interpreterProxy isInMemory: addr]") ifTrue:[^interpreterProxy primitiveFail]. ] ifFalse:[ (byteOffset+byteSize-1 <= rcvrSize) ifFalse:[^interpreterProxy primitiveFail]. addr := self cCoerce: (interpreterProxy firstIndexableField: rcvr) to: 'int'. ]. addr := addr + byteOffset - 1. ^addr!

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VM Maker: Cog-eem.291.mcz
by commits＠source.squeak.org 03 Nov '15

03 Nov '15

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.291.mcz ==================== Summary ==================== Name: Cog-eem.291 Author: eem Time: 2 November 2015, 9:53:33.474 pm UUID: 5cab4ae5-87d4-438a-a9ae-9bf4a7394dd9 Ancestors: Cog-eem.290 Add support for failing register-indirect calls on x64 =============== Diff against Cog-eem.290 =============== Item was changed: + ----- Method: BochsX64Alien>>handleGroup5FailureAt:in:rex: (in category 'error handling') ----- - ----- Method: BochsX64Alien>>handleGroup5FailureAt:in:rex: (in category 'as yet unclassified') ----- handleGroup5FailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" rex: rexByteOrNil "<Integer|nil>" "Convert an execution primitive failure for a group 5 instruction into the relevant ProcessorSimulationTrap signal." | modrmByte getter | self assert: rexByteOrNil isNil. modrmByte := memoryArray byteAt: pc + 2. (modrmByte >> 3 bitAnd: 7) caseOf: { [2 "Call Ev"] -> [getter := self registerStateGetters at: (modrmByte bitAnd: 7) + 1. ^(ProcessorSimulationTrap pc: pc nextpc: pc + 2 address: (self perform: getter) type: #call) signal] }!

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[commit][3483] update midi & scratch plugins to support MIDI plugin improvements
by commits＠squeakvm.org 02 Nov '15

02 Nov '15

Revision: 3483 Author: rowledge Date: 2015-11-02 14:31:32 -0800 (Mon, 02 Nov 2015) Log Message: ----------- update midi & scratch plugins to support MIDI plugin improvements Modified Paths: -------------- branches/Cog/platforms/unix/plugins/MIDIPlugin/sqUnixMIDIALSA.inc branches/Cog/platforms/unix/plugins/ScratchPlugin/unixSeriaPort2Ops.c Modified: branches/Cog/platforms/unix/plugins/MIDIPlugin/sqUnixMIDIALSA.inc =================================================================== --- branches/Cog/platforms/unix/plugins/MIDIPlugin/sqUnixMIDIALSA.inc 2015-11-02 22:28:52 UTC (rev 3482) +++ branches/Cog/platforms/unix/plugins/MIDIPlugin/sqUnixMIDIALSA.inc 2015-11-02 22:31:32 UTC (rev 3483) @@ -30,7 +30,12 @@ * Reformatted for and integrated into Squeak build by: ian at * squeakland dot oh are gee * - * Last edited: 2009-08-19 04:39:12 by piumarta on emilia-2.local + * Modified for Scratch on Raspberry Pi by Manabu Sugiura + * - Compatibility of MIDI instruments on Raspbian + * - YAMAHA NSX-1 and NSX-39 + * http://yamaha-webmusic.github.io/nsx1-apps/specs/ANMW820A-001-10-j.pdf + * + * Last edited: 2014-09-17 22:33:32 by manabu on raspberrypi */ /*** MIDI Parameters (used with sqMIDIParameter function) ***/ @@ -143,6 +148,33 @@ 3, 1, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +/* Phonetic Symbols Buffer for YAMAHA NSX-1 */ +char ps[128]; +int ps_index = 0; + +/* Port information Buffers + +Sample: +-MIDI settings +% acconet -o +Port Client name Port name +14:0 Midi Through Midi Through Port-0 +20:0 NSX-39 NSX-39 MIDI 1 +128:0 TiMidity TiMidity port 0 +128:1 TiMidity TiMidity port 1 +128:2 TiMidity TiMidity port 2 +128:3 TiMidity TiMidity port 3 + +-Port information Buffers +portIds[14,20,128,128,128,128] +portNums[0,0,0,1,2,3] +*/ + +#define MAX_PORT_COUNT 256 +int portIds[MAX_PORT_COUNT]; // client ids +int portNums[MAX_PORT_COUNT]; // port numbers +int portTypes[MAX_PORT_COUNT] = {0}; // now ignore input client + static void performMIDICmd(snd_seq_event_t *ev, int cmdByte, int arg1, int arg2); static void processMIDIByte(snd_seq_event_t *ev, int aByte); static void startMIDICommand(snd_seq_event_t *ev, int cmdByte); @@ -155,23 +187,29 @@ */ int sqMIDIClosePort(int portNum) { - int ret= 0; + int ret = 0; + snd_seq_event_t ev; - if (portNum == 0) - { - if (out_port >= 0) - ret= snd_seq_delete_simple_port(seq, out_port); + if(portTypes[portNum] == 0){ + if (out_port >= 0) { + char all_note_off[] = {MIDI_CMD_CONTROL, 0x7b, 0x00}; + snd_seq_ev_set_sysex(&ev, sizeof(all_note_off), all_note_off); + snd_seq_ev_set_direct(&ev); + snd_seq_ev_set_source(&ev, 0); + snd_seq_ev_set_dest(&ev, portIds[portNum], 0); + snd_seq_event_output(seq, &ev); + snd_seq_drain_output(seq); + ret = snd_seq_delete_simple_port(seq, out_port); out_port= -1; } - else if (portNum == 1) - { - if (in_port >= 0) + } else if (portTypes[portNum] == 1) { + if (in_port >= 0) { ret= snd_seq_delete_simple_port(seq, in_port); in_port= -1; } - else + } else { return interpreterProxy->success(false); - + } return ret; } @@ -197,8 +235,40 @@ int sqMIDIGetPortCount(void) { DPRINTF("sqMIDIGetPortCount\n"); + snd_seq_client_info_t *cinfo; + snd_seq_port_info_t *pinfo; + + snd_seq_client_info_alloca(&cinfo); + snd_seq_client_info_set_client(cinfo, -1); + + int cap; + int count = 0; + int client; + + while (snd_seq_query_next_client(seq, cinfo) >= 0 ){ + client = snd_seq_client_info_get_client(cinfo); + + snd_seq_port_info_alloca(&pinfo); + snd_seq_port_info_set_client(pinfo, client); + snd_seq_port_info_set_port(pinfo, -1); + + // while the next port is available + while (snd_seq_query_next_port(seq, pinfo) >= 0) { + cap = snd_seq_port_info_get_capability(pinfo); + // select output ports + if ((cap & SND_SEQ_PORT_CAP_SUBS_WRITE) != 0 && snd_seq_client_id(seq) != snd_seq_port_info_get_client(pinfo)) { + if (snd_seq_client_id(seq) != snd_seq_port_info_get_client(pinfo)) { + if (count < MAX_PORT_COUNT && strcmp(snd_seq_client_info_get_name(cinfo), "Midi Through") != 0) { //skip Midi Through port + portIds[count] = snd_seq_port_info_get_client(pinfo); + portNums[count] = snd_seq_port_info_get_port(pinfo); + count++; + } + } + } + } + } success(true); - return 1; + return count; } /* Return an integer indicating the directionality of the given @@ -207,10 +277,11 @@ */ int sqMIDIGetPortDirectionality(int portNum) { - switch (portNum) + switch(portTypes[portNum]) { case 0: return 2; - case 1: return 1; + case 1: return 1; //TODO: modify + default: return 0; } return interpreterProxy->success(false); } @@ -221,17 +292,23 @@ */ int sqMIDIGetPortName(int portNum, int namePtr, int length) { - static char *userName[] = { "out", "in" }; + int count; + snd_seq_client_info_t *cinfo; + char name[128]; + char portNumStr[128]; - if (portNum == 0 || portNum == 1) - { - int count= strlen(userName[portNum]); + snd_seq_client_info_alloca(&cinfo); + snd_seq_client_info_set_client(cinfo, -1); + snd_seq_get_any_client_info(seq, portIds[portNum], cinfo); + sprintf(portNumStr, "%d", portNums[portNum]); + sprintf(name, "%s <port:%s>", snd_seq_client_info_get_name(cinfo) , portNumStr); + count = strlen(name); if (count > length) count= length; - memcpy((void *)namePtr, userName, count); + memcpy((void *)namePtr, name, count); + + success(true); return count; } - return interpreterProxy->success(false); -} /* Open the given port, if possible. If non-zero, readSemaphoreIndex specifies the index in the external objects array of a semaphore to @@ -245,9 +322,9 @@ int sqMIDIOpenPort(int portNum, int readSemaIndex, int interfaceClockRate) { DPRINTF(("sqMIDIOpenPort(%d, %d, %d)\n", portNum, readSemaIndex, interfaceClockRate)); + out_port = -1; int type= SND_SEQ_PORT_TYPE_APPLICATION; - - switch (portNum) + switch (portTypes[portNum]) { case 0: if (out_port < 0) @@ -259,6 +336,12 @@ success(false); return 0; } + + if (snd_seq_connect_to(seq, out_port, portIds[portNum], 0) < 0) + { + success(false); + return 0; + } } break; @@ -282,7 +365,7 @@ snd_seq_queue_tempo_t *tempo= 0; snd_seq_queue_tempo_alloca(&tempo); snd_seq_queue_tempo_set_tempo(tempo, interfaceClockRate); - snd_seq_set_queue_tempo(seq, queue, tempo); + snd_seq_set_queue_tempo(seq, queue, (snd_seq_queue_tempo_t*)tempo); success(true); return 0; @@ -333,7 +416,7 @@ { snd_seq_queue_tempo_t *tempo= 0; snd_seq_queue_tempo_alloca(&tempo); - snd_seq_get_queue_tempo(seq, queue, &tempo); + snd_seq_get_queue_tempo(seq, queue, tempo); return snd_seq_queue_tempo_get_tempo(tempo) / 1000.0; } break; @@ -380,7 +463,7 @@ snd_seq_queue_tempo_t *tempo= 0; snd_seq_queue_tempo_alloca(&tempo); snd_seq_queue_tempo_set_tempo(tempo, 1000.0 * newValue); - snd_seq_set_queue_tempo(seq, queue, tempo); + snd_seq_set_queue_tempo(seq, queue, (snd_seq_queue_tempo_t*)tempo); } break; @@ -420,8 +503,7 @@ */ int sqMIDIPortWriteFromAt(int portNum, int count, int bufferPtr, int time) { - if (portNum == 0) - { + if (portTypes[portNum] == 0 || portTypes[portNum] == 1) { int i; snd_seq_event_t ev; unsigned char *bytePtr= (unsigned char *)bufferPtr; @@ -449,8 +531,7 @@ int midiInit(void) { - if (snd_seq_open(&seq, "default", SND_SEQ_OPEN_INPUT|SND_SEQ_OPEN_OUTPUT, 0) < 0) - { + if (snd_seq_open(&seq, "default", SND_SEQ_OPEN_INPUT|SND_SEQ_OPEN_OUTPUT, 0) < 0) { success(false); return 0; } @@ -533,6 +614,7 @@ static void processMIDIByte(snd_seq_event_t *ev, int aByte) { + int i; if (aByte > 247) return; /* skip all real-time messages */ switch (state) @@ -577,6 +659,8 @@ if (aByte < 128) { /* skip a system exclusive data byte */ + ps[ps_index] = aByte; + ps_index++; } else { @@ -588,6 +672,13 @@ { processMIDIByte(ev, aByte); /* if not endSysExclusive, byte is the start the next command */ } + else{ + ps[ps_index] = aByte; + ps_index++; + //ev->type = SND_SEQ_EVENT_SYSEX; + snd_seq_ev_set_sysex(ev, ps_index +1 , ps); + ps_index = 0; + } } } break; @@ -619,7 +710,11 @@ case 3: /* start a variable length 'system exclusive' command */ /* a system exclusive command clears running status */ lastCmdByte= 0; + if(cmdByte == 240){ + ps[ps_index] = cmdByte; + ps_index++; + } state= sysExclusive; break; } -} +} \ No newline at end of file Modified: branches/Cog/platforms/unix/plugins/ScratchPlugin/unixSeriaPort2Ops.c =================================================================== --- branches/Cog/platforms/unix/plugins/ScratchPlugin/unixSeriaPort2Ops.c 2015-11-02 22:28:52 UTC (rev 3482) +++ branches/Cog/platforms/unix/plugins/ScratchPlugin/unixSeriaPort2Ops.c 2015-11-02 22:31:32 UTC (rev 3483) @@ -337,7 +337,7 @@ } int isSerialPortDev(char *s) { - return isPrefix("ttyusb", s); + return isPrefix("ttyusb", s) || isPrefix("ttyAMA", s); } int isPrefix(char *prefix, char *s) {

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[commit][3482] update cog-spur make stuf to support MIDI plugin improvements
by commits＠squeakvm.org 02 Nov '15

02 Nov '15

Revision: 3482 Author: rowledge Date: 2015-11-02 14:28:52 -0800 (Mon, 02 Nov 2015) Log Message: ----------- update cog-spur make stuf to support MIDI plugin improvements Modified Paths: -------------- branches/Cog/build.linux32ARM/squeak.cog.spur/build/mvm branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/mvm branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/mvm Modified: branches/Cog/build.linux32ARM/squeak.cog.spur/build/mvm =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build/mvm 2015-11-02 00:02:54 UTC (rev 3481) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build/mvm 2015-11-02 22:28:52 UTC (rev 3482) @@ -21,7 +21,7 @@ --without-vm-display-fbdev --without-npsqueak --enable-fast-bitblt \ CC="gcc -march=armv6 -mfpu=vfp -mfloat-abi=hard" \ CXX=g++ \ - CFLAGS="$OPT -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -DI_REALLY_DONT_CARE_HOW_UNSAFE_THIS_IS -DCOGMTVM=0" \ + CFLAGS="$OPT -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -DI_REALLY_DONT_CARE_HOW_UNSAFE_THIS_IS -DUSE_MIDI_ALSA -DCOGMTVM=0" \ LIBS="-lpthread -luuid -lasound" \ LDFLAGS=-Wl,-z,now rm -f vm/sqUnixMain.o # nuke version info Modified: branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/mvm =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/mvm 2015-11-02 00:02:54 UTC (rev 3481) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/mvm 2015-11-02 22:28:52 UTC (rev 3482) @@ -21,7 +21,7 @@ --without-vm-display-fbdev --without-npsqueak --enable-fast-bitblt \ CC="gcc -march=armv6 -mfpu=vfp -mfloat-abi=hard" \ CXX=g++ \ - CFLAGS="$OPT -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -DI_REALLY_DONT_CARE_HOW_UNSAFE_THIS_IS -DCOGMTVM=0" \ + CFLAGS="$OPT -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -DI_REALLY_DONT_CARE_HOW_UNSAFE_THIS_IS -DUSE_MIDI_ALSA -DCOGMTVM=0" \ LIBS="-lpthread -luuid -lasound" \ LDFLAGS=-Wl,-z,now rm -f vm/sqUnixMain.o # nuke version info Modified: branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/mvm =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/mvm 2015-11-02 00:02:54 UTC (rev 3481) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/mvm 2015-11-02 22:28:52 UTC (rev 3482) @@ -21,7 +21,7 @@ --without-vm-display-fbdev --without-npsqueak --enable-fast-bitblt \ CC="gcc -march=armv6 -mfpu=vfp -mfloat-abi=hard" \ CXX=g++ \ - CFLAGS="$OPT -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -DI_REALLY_DONT_CARE_HOW_UNSAFE_THIS_IS -DCOGMTVM=0" \ + CFLAGS="$OPT -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -DI_REALLY_DONT_CARE_HOW_UNSAFE_THIS_IS -DUSE_MIDI_ALSA -DCOGMTVM=0" \ LIBS="-lpthread -luuid -lasound" \ LDFLAGS=-Wl,-z,now rm -f vm/sqUnixMain.o # nuke version info

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[ANN] OopluCon 2016, San Francisco, April
by Chris Cunnington 02 Nov '15

02 Nov '15

OopluCon 2016 A Day for the Smalltalk Programming Language and its Friends Sunday 10 April 2016 8am - 4pm The Box SF 1069 Howard Street (between 6th and 7th) three blocks from Moscone Center, SoMa San Francisco, USA http://www.theboxsf.com/ The event is free A request for presentations will be announced in a future month A presentation called An Introduction To Smalltalk will promoted to the Ruby, Python and Objective C communities The latest details will be available at http://www.ooplu.com

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64bits spur DataStream assumes SmallInteger fit in 32bits
by Nicolas Cellier 01 Nov '15

01 Nov '15

Hi, as the title tells, DataStream>>writeInteger: anInteger "PRIVATE -- Write the contents of a SmallInteger." byteStream nextInt32Put: anInteger "signed!!!!!" Which strategy do we adopt? I suggest using a fake LargeInteger... objectToStore := (self objectIfBlocked: anObject) objectForDataStream: self. objectToStore == anObject ifFalse: [typeID := self typeIDFor: objectToStore]. Of course, we must also care of LargeInteger materialization in 64bits spur. I'm going to fix it unless someone has a better idea. Nicolas

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Vm-dev November 2015