A new version of VMMaker was added to project VM Maker Inbox: http://source.squeak.org/VMMakerInbox/VMMaker.oscog-KenD.3218.mcz
==================== Summary ====================
Name: VMMaker.oscog-KenD.3218 Author: KenD Time: 23 July 2022, 5:57:39.531648 pm UUID: 76a9d964-998d-4192-9b1b-f69265cdd95f Ancestors: VMMaker.oscog-eem.3217
Port to RiscV64/RV64gcv Note: ThreadedARM64FFIPlugin currently requires after-codegen float/double flow split
=============== Diff against VMMaker.oscog-eem.3217 ===============
Item was changed: CogAbstractInstruction subclass: #CogARMv8Compiler instanceVariableNames: '' + classVariableNames: 'AL ArithmeticAdd ArithmeticAddS ArithmeticSub ArithmeticSubS CASAL CArg0Reg CArg1Reg CArg2Reg CArg3Reg CArg4Reg CArg5Reg CArg6Reg CBNZ CBZ CC CCMPNE CLREX CS CSET D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 DC DC_CISW DC_CIVAC DC_CSW DC_CVAC DC_CVAU DC_ISW DC_IVAC DC_ZVA DMB DSB DSB_ALL DSB_ALLSY DSB_ISH DSB_NSH DSB_OSH DSB_READS DSB_SY DSB_WRITES DivRRR EQ FP GE GT HI IC IC_IALLU IC_IALLUIS IC_IVAU ISB LDAXR LE LR LS LT LogicalAnd LogicalAndS LogicalOr LogicalXor MI MRS_CTR_EL0 MRS_ID_AA64ISAR0_EL1 MSubRRR MoveAwRR MoveRRAw MulOverflowRRR MulRRR NE NativePopRR NativePushRR PJWPNChange PJWPNClear PJWPNSet PJWPNState PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 SMULHRRR SP STLR STLXR SXTB SXTH SXTW SXTX UXTB UXTH UXTW UXTX VC VS XZR' - classVariableNames: 'AL ArithmeticAdd ArithmeticAddS ArithmeticSub ArithmeticSubS CASAL CArg0Reg CArg1Reg CArg2Reg CArg3Reg CArg4Reg CArg5Reg CArg6Reg CBNZ CBZ CC CCMPNE CLREX CS CSET D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 DC DC_CISW DC_CIVAC DC_CSW DC_CVAC DC_CVAU DC_ISW DC_IVAC DC_ZVA DMB DSB DSB_ALL DSB_ALLSY DSB_ISH DSB_NSH DSB_OSH DSB_READS DSB_SY DSB_WRITES DataCacheFlushRequired DataCacheLineLength DivRRR EQ FP GE GT HI HasAtomicInstructions IC IC_IALLU IC_IALLUIS IC_IVAU ISB InstructionCacheFlushRequired InstructionCacheLineLength LDAXR LE LR LS LT LogicalAnd LogicalAndS LogicalOr LogicalXor MI MRS_CTR_EL0 MRS_ID_AA64ISAR0_EL1 MSubRRR MoveAwRR MoveRRAw MulOverflowRRR MulRRR NE NativePopRR NativePushRR PJWPNChange PJWPNClear PJWPNSet PJWPNState PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 SMULHRRR SP STLR STLXR SXTB SXTH SXTW SXTX UXTB UXTH UXTW UXTX VC VS XZR' poolDictionaries: 'ARMv8A64Opcodes' category: 'VMMaker-JIT'!
!CogARMv8Compiler commentStamp: 'eem 1/7/2021 23:01' prior: 0! I generate ARMv8 machine code instructions from CogAbstractInstructions with CogRTLOpcodes. Here in "Arm ARM" refers to Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-man...
Some things to know about ARMv8 instructions: Whether 31 in a register field implies the zero register or the SP register(s) depends on the specific instruction.
C3.2.1 Load/Store register If a Load instruction specifies writeback and the register being loaded is also the base register, then behavior is CONSTRAINED UNPREDICTABLE and one of the following behaviors must occur: - The instruction is treated as UNDEFINED. - The instruction is treated as a NOP. - The instruction performs the load using the specified addressing mode and the base register becomes UNKNOWN. In addition, if an exception occurs during the execution of such an instruction, the base address might be corrupted so that the instruction cannot be repeated. If a Store instruction performs a writeback and the register that is stored is also the base register, then behavior is CONSTRAINED UNPREDICTABLE and one of the following behaviors must occur: - The instruction is treated as UNDEFINED. - The instruction is treated as a NOP. - The instruction performs the store to the designated register using the specified addressing mode, but the value stored is UNKNOWN.!
Item was changed: ----- Method: CogSistaMethodSurrogate32>>counters: (in category 'accessing generated') ----- counters: aValue | index delta | index := address + 20 + baseHeaderSize. (delta := cogit getCodeToDataDelta) > 0 ifTrue: [self assert: (cogit addressIsInCodeZone: address - delta). objectMemory long32At: index - delta + put: aValue]. - put: ((aValue ifNotNil: [aValue asUnsignedInteger] ifNil: [0]))]. ^objectMemory long32At: index + put: aValue! - put: ((aValue ifNotNil: [aValue asUnsignedInteger] ifNil: [0]))!
Item was changed: ----- Method: CogSistaMethodSurrogate64>>counters: (in category 'accessing generated') ----- counters: aValue | index delta | index := address + 32 + baseHeaderSize. (delta := cogit getCodeToDataDelta) > 0 ifTrue: [self assert: (cogit addressIsInCodeZone: address - delta). objectMemory long64At: index - delta + put: aValue]. - put: ((aValue ifNotNil: [aValue asUnsignedInteger] ifNil: [0]))]. ^objectMemory long64At: index + put: aValue! - put: ((aValue ifNotNil: [aValue asUnsignedInteger] ifNil: [0]))!
Item was changed: ----- Method: ThreadedRiscV64FFIPlugin>>ffiPushFloat32:in: (in category 'marshalling') ----- ffiPushFloat32: value in: calloutState <var: #value type: #float> <var: #calloutState type: #'CalloutState *'> <inline: #always> "N.B. the RISCV ABI states that unused part should be -1, [RISC-V Instruction Set Manual - Volume I: User Level ISA, 12.2 NaN Boxing of Narrower Value" calloutState floatRegisterIndex < NumFloatRegArgs ifTrue: "Note: this is a 'memcopy', so size is preserved. Casting to #double changes the size" [(self cCoerceSimple: (self addressOf: (calloutState floatRegisters at: calloutState floatRegisterIndex)) to: #'long *') at: 0 put: -1. (self cCoerceSimple: (self addressOf: (calloutState floatRegisters at: calloutState floatRegisterIndex)) to: #'float *') at: 0 put: value. + calloutState floatRegisterIndex: calloutState floatRegisterIndex + 1 + ] + ifFalse: "Use integer register if available" + [ (calloutState integerRegisterIndex < NumIntRegArgs) + ifTrue: + [calloutState integerRegisters + at: calloutState integerRegisterIndex + put: -1. + self storeSingleFloatAtPointer: (self addressOf: (calloutState integerRegisters at: calloutState integerRegisterIndex)) + from: value. + calloutState integerRegisterIndex: calloutState integerRegisterIndex + 1 + ] + ifFalse: + [calloutState currentArg + self wordSize > calloutState limit ifTrue: [^FFIErrorCallFrameTooBig]. + interpreterProxy longAt: calloutState currentArg put: value. + calloutState currentArg: calloutState currentArg + self wordSize + ]. + ]. - calloutState floatRegisterIndex: calloutState floatRegisterIndex + 1] - ifFalse: - [calloutState currentArg + self wordSize > calloutState limit ifTrue: - [^FFIErrorCallFrameTooBig]. - interpreterProxy - longAt: calloutState currentArg put: -1; - storeSingleFloatAtPointer: calloutState currentArg from: value. - calloutState currentArg: calloutState currentArg + self wordSize]. ^0!
Item was added: + ----- Method: ThreadedRiscV64FFIPlugin>>ffiPushFloat64:in: (in category 'marshalling') ----- + ffiPushFloat64: value in: calloutState + <var: #value type: #double> + <var: #calloutState type: #'CalloutState *'> + <inline: #always> + + calloutState floatRegisterIndex < NumFloatRegArgs + ifTrue: + [calloutState floatRegisters + at: calloutState floatRegisterIndex + put: value. + calloutState floatRegisterIndex: calloutState floatRegisterIndex + 1 + ] + ifFalse: "Use integer register if available" + [(calloutState integerRegisterIndex < NumIntRegArgs) + ifTrue: [ + self storeFloatAtPointer: (self addressOf: (calloutState integerRegisters at: calloutState integerRegisterIndex)) + from: value. + calloutState integerRegisterIndex: calloutState integerRegisterIndex + 1 + ] + ifFalse: [ + calloutState currentArg + self wordSize > calloutState limit ifTrue: [^FFIErrorCallFrameTooBig]. + interpreterProxy longAt: calloutState currentArg put: value. + calloutState currentArg: calloutState currentArg + self wordSize + ] + ]. + ^0!
Item was added: + ----- Method: ThreadedRiscV64FFIPlugin>>numFloatRegArgs (in category 'accessing') ----- + numFloatRegArgs + + ^NumFloatRegArgs!
Item was added: + ----- Method: ThreadedRiscV64FFIPlugin>>numIntRegArgs (in category 'accessing') ----- + numIntRegArgs + + ^NumIntRegArgs!