Vm-dev December 2019

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[OpenSmalltalk/opensmalltalk-vm] Fix Metal window crash on resize. (#453)
by Ronie Salgado 09 Dec '19

09 Dec '19

This fixes an edge condition with the metal renderer where the update rect ends out of the bounds of the display texture. The texture update region ends with negative coordinates. You can view, comment on, or merge this pull request online at: https://github.com/OpenSmalltalk/opensmalltalk-vm/pull/453 -- Commit Summary -- * This fixed an edge condition with the metal renderer where the update rect ends out of the bounds of the display texture. -- File Changes -- M platforms/iOS/vm/OSX/sqSqueakOSXMetalView.m (10) -- Patch Links -- https://github.com/OpenSmalltalk/opensmalltalk-vm/pull/453.patch https://github.com/OpenSmalltalk/opensmalltalk-vm/pull/453.diff -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/pull/453

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[OpenSmalltalk/opensmalltalk-vm] 66e635: This fixed an edge condition with the metal render...
by Eliot Miranda 09 Dec '19

09 Dec '19

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 66e635d755ade763a5987a843d7e32cfc8292e15 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/66e635d755ade763a5… Author: Ronie Salgado <roniesalg(a)gmail.com> Date: 2019-12-09 (Mon, 09 Dec 2019) Changed paths: M platforms/iOS/vm/OSX/sqSqueakOSXMetalView.m Log Message: ----------- This fixed an edge condition with the metal renderer where the update rect ends out of the bounds of the display texture. Commit: 321f39825b03d47331bee82a476c1a9924850b7c https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/321f39825b03d47331… Author: Eliot Miranda <eliot.miranda(a)gmail.com> Date: 2019-12-09 (Mon, 09 Dec 2019) Changed paths: M platforms/iOS/vm/OSX/sqSqueakOSXMetalView.m Log Message: ----------- Merge pull request #453 from ronsaldo/bug/metal-window-resize-crash Fix Metal window crash on resize. Compare: https://github.com/OpenSmalltalk/opensmalltalk-vm/compare/a71f6337eb1d...32…

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VM Maker: VMMaker.oscog-eem.2598.mcz
by commits＠source.squeak.org 09 Dec '19

09 Dec '19

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2598.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2598 Author: eem Time: 28 November 2019, 2:59:35.467528 pm UUID: e195198a-a4ee-4bd9-92c2-42accc436f7a Ancestors: VMMaker.oscog-eem.2597 Fix plugin generation given renamed plugins =============== Diff against VMMaker.oscog-eem.2597 =============== Item was changed: ----- Method: VMMaker class>>generateVMPlugins (in category 'configurations') ----- generateVMPlugins ^VMMaker generatePluginsTo: self sourceTree, '/src' options: #() platformDir: self sourceTree, '/platforms' + including:#(ADPCMCodecPlugin AsynchFilePlugin - including:#( ADPCMCodecPlugin AsynchFilePlugin BalloonEnginePlugin B3DAcceleratorPlugin B3DEnginePlugin BMPReadWriterPlugin BitBltSimulation + BochsIA32Plugin BochsX64Plugin GdbARMv6Plugin GdbARMv8Plugin - BochsIA32Plugin BochsX64Plugin CameraPlugin CroquetPlugin DeflatePlugin DropPlugin "Cryptography Plugins:" DESPlugin DSAPlugin MD5Plugin SHA256Plugin "FT2Plugin" FFTPlugin FileCopyPlugin FilePlugin FileAttributesPlugin FloatArrayPlugin FloatMathPlugin + GeniePlugin HostWindowPlugin IA32ABIPlugin ImmX11Plugin InternetConfigPlugin - GeniePlugin GdbARMPlugin HostWindowPlugin IA32ABIPlugin ImmX11Plugin InternetConfigPlugin JPEGReadWriter2Plugin JPEGReaderPlugin JoystickTabletPlugin KlattSynthesizerPlugin LargeIntegersPlugin LocalePlugin MIDIPlugin MacMenubarPlugin Matrix2x3Plugin MiscPrimitivePlugin Mpeg3Plugin QuicktimePlugin RePlugin ScratchPlugin SecurityPlugin SerialPlugin SocketPlugin SoundCodecPlugin SoundGenerationPlugin SoundPlugin SqueakSSLPlugin StarSqueakPlugin ThreadedFFIPlugin ThreadedARM32FFIPlugin ThreadedARM64FFIPlugin ThreadedIA32FFIPlugin ThreadedX64SysVFFIPlugin ThreadedX64Win64FFIPlugin UnicodePlugin UnixAioPlugin UUIDPlugin UnixOSProcessPlugin Win32OSProcessPlugin VMProfileLinuxSupportPlugin VMProfileMacSupportPlugin WeDoPlugin XDisplayControlPlugin)!

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[OpenSmalltalk/opensmalltalk-vm] Declare the shared library depedencies for vm-sound-pulse. Fixes #360 (#452)
by Tom Beckmann 09 Dec '19

09 Dec '19

On my system, pulse was not picked as default driver. I had to manually add add -vm-sound-pulse as a startup parameter. After adding this line it worked without any LD hacks though and ldd reports a correctly linked so file. You can view, comment on, or merge this pull request online at: https://github.com/OpenSmalltalk/opensmalltalk-vm/pull/452 -- Commit Summary -- * declare the shared library depedencies for vm-sound-pulse -- File Changes -- A platforms/unix/vm-sound-pulse/Makefile.inc (1) -- Patch Links -- https://github.com/OpenSmalltalk/opensmalltalk-vm/pull/452.patch https://github.com/OpenSmalltalk/opensmalltalk-vm/pull/452.diff -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/pull/452

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[OpenSmalltalk/opensmalltalk-vm] Problem linking Linux Sound Library (#360)
by Eva 09 Dec '19

09 Dec '19

On Linux Mint Sylvia, I could not play sounds (e.g. ``SampledSound beep``). This occurred in the newest SWA VM build of Squeak. Underlying problem seems to be that the Linux sound libraries for PulseAudio are not linked correctly. (Maybe this is the same as #118) With @krono I found this workaround: `` LD_PRELOAD=/usr/lib/x86_64-linux-gnu/libpulse-simple.so.0.1.0 LD_LIBRARY_PATH=/home/user/Dokumente/SWA2018.app/Contents/Linux-i686/bin/../lib/squeak/5.0-201810071412:/lib/x86_64-linux-gnu:/lib:/usr/lib/x86_64-linux-gnu:/usr/lib: /home/user/Dokumente/SWA2018.app/Contents/Linux-i686/bin/../lib/squeak/5.0-201810071412/squeak -vm-sound-pulse /home/user/Dokumente/SWA2018.app/Contents/Resources/SWA2018.image `` -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/360

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[OpenSmalltalk/opensmalltalk-vm] e01e00: declare the shared library depedencies for vm-soun...
by Tobias Pape 09 Dec '19

09 Dec '19

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: e01e0076cd6c5fdace135edd36fca29c95c682cc https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/e01e0076cd6c5fdace… Author: Tom Beckmann <tomjonabc(a)gmail.com> Date: 2019-12-09 (Mon, 09 Dec 2019) Changed paths: A platforms/unix/vm-sound-pulse/Makefile.inc Log Message: ----------- declare the shared library depedencies for vm-sound-pulse Commit: a71f6337eb1d64d72910f3908b5437d3e8bcf10a https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/a71f6337eb1d64d729… Author: Tobias Pape <krono(a)users.noreply.github.com> Date: 2019-12-09 (Mon, 09 Dec 2019) Changed paths: A platforms/unix/vm-sound-pulse/Makefile.inc Log Message: ----------- Merge pull request #452 from tom95/pulse-build-fix Declare the shared library depedencies for vm-sound-pulse. Fixes #360 Compare: https://github.com/OpenSmalltalk/opensmalltalk-vm/compare/bb5c547ba5b0...a7…

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VM Maker: VMMaker.oscog-eem.2612.mcz
by commits＠source.squeak.org 09 Dec '19

09 Dec '19

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2612.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2612 Author: eem Time: 8 December 2019, 11:38:56.061854 pm UUID: e1e9823a-528b-4d8d-9234-874ead7f9e80 Ancestors: VMMaker.oscog-eem.2611 A64 Get the offset right in PopR =============== Diff against VMMaker.oscog-eem.2611 =============== Item was changed: ----- Method: CogARMv8Compiler>>concretizePopR (in category 'generate machine code - concretize') ----- concretizePopR <inline: true> "C6.2.273 LDR (immediate) C6-1239 Post-index" | reg | reg := operands at: 0. self deny: SP = reg. machineCode at: 0 put: 2r1111100001 << 22 + + ((8 bitAnd: 1 << 9 - 1) << 12) - + ((-8 bitAnd: 1 << 9 - 1) << 12) + (2r01 << 10) + (SP << 5) + reg. ^4!

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VM Maker: VMMaker.oscog-eem.2611.mcz
by commits＠source.squeak.org 09 Dec '19

09 Dec '19

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2611.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2611 Author: eem Time: 8 December 2019, 11:36:41.233693 pm UUID: a1c152a6-e044-4b14-9eac-4aedeeb61684 Ancestors: VMMaker.oscog-eem.2610 A64 Call, CallFull, MoveCqR, PopR, PushR. More ABI implementation, nameForRegister:. Eliminate duplication in genLoadStackPointers; implement in CogAbstractInstruction. Add a few subclass responsibilities. Correct 64-bit instruction printing (signedIntFromLong64 instead of signedIntFromLong). Add Extra6Reg & Extra7Reg to nameForRegister:. Now all send trampolines compile and generated code "looks ok" (which is potyentially very different from correwct). =============== Diff against VMMaker.oscog-eem.2610 =============== Item was removed: - ----- Method: CogARMCompiler>>genLoadStackPointers (in category 'smalltalk calling convention') ----- - genLoadStackPointers - "Switch back to the Smalltalk stack. Assign SPReg first - because typically it is used immediately afterwards." - cogit MoveAw: cogit stackPointerAddress R: SPReg. - cogit MoveAw: cogit framePointerAddress R: FPReg. - ^0! Item was changed: ----- Method: CogARMCompiler>>nameForRegister: (in category 'printing') ----- nameForRegister: reg "<Integer>" <doNotGenerate> | default | default := super nameForRegister: reg. ^default last = $? ifTrue: + [#(LR SP PC CArg0Reg CArg1Reg CArg2Reg CArg3Reg) - [#(LR SP PC CArg0Reg CArg0Reg CArg1Reg CArg2Reg CArg3Reg) detect: [:sym| (thisContext method methodClass classPool at: sym) = reg] ifNone: [default]] ifFalse: [default]! Item was changed: ----- Method: CogARMv8Compiler>>computeJumpTargetOffset (in category 'generate machine code') ----- computeJumpTargetOffset <inline: true> | jumpTarget | <var: #jumpTarget type: #'AbstractInstruction *'> jumpTarget := self jumpTargetAddress. + ^jumpTarget signedIntFromLong64 - address signedIntFromLong64! - ^jumpTarget signedIntFromLong - address signedIntFromLong.! Item was added: + ----- Method: CogARMv8Compiler>>concretizeCall (in category 'generate machine code - concretize') ----- + concretizeCall + | offset | + offset := ((operands at: 0) - address) signedIntFromLong64. + self assert: (offset noMask: 3). + self assert: (self isInImmediateBranchAndLinkRange: offset). + machineCode + at: 0 + put: 2r100101 << 26 + + (offset >> 2 bitAnd: 1 << 26 - 1). + ^4! Item was added: + ----- Method: CogARMv8Compiler>>concretizeCallFull (in category 'generate machine code - concretize') ----- + concretizeCallFull + "Will get inlined into concretizeAt: switch." + "Sizing/generating calls. + Jump targets can be to absolute addresses or other abstract instructions. + Generating initial trampolines instructions may have no maxSize and be to absolute addresses. + Otherwise instructions must have a machineCodeSize which must be kept to." + <inline: true> + | jumpTarget instrOffset| + <var: #jumpTarget type: #'AbstractInstruction *'> + jumpTarget := self longJumpTargetAddress. + instrOffset := self moveCw: jumpTarget intoR: RISCTempReg. + machineCode + at: instrOffset // 4 + put: (self cond: AL br: 1 reg: RISCTempReg). + self assert: instrOffset = self literalLoadInstructionBytes. + ^instrOffset + 4! Item was changed: ----- Method: CogARMv8Compiler>>concretizeConditionalJump: (in category 'generate machine code - concretize') ----- concretizeConditionalJump: conditionCode "Will get inlined into concretizeAt: switch." "Sizing/generating jumps. Jump targets can be to absolute addresses or other abstract instructions. Generating initial trampolines instructions may have no maxSize and be to absolute addresses. Otherwise instructions must have a machineCodeSize which must be kept to." <inline: true> | offset | offset := self computeJumpTargetOffset. self assert: (self isInImmediateBranchRange: offset). + machineCode at: 0 put: (self cond: conditionCode br: 0 offset: offset). "B offset" - self machineCodeAt: 0 put: (self cond: conditionCode br: 0 offset: offset). "B offset" ^4! Item was changed: ----- Method: CogARMv8Compiler>>concretizeLogicalShiftLeftCqR (in category 'generate machine code - concretize') ----- concretizeLogicalShiftLeftCqR + <inline: true> "C6.2.17 ASR (immediate) C6-785 100100110 (1) C6.2.177 LSL (immediate) C6-1075 110100110 (1) C6.2.180 LSR (immediate) C6-1081 110100110 (1)" | reg constant | constant := operands at: 0. reg := operands at: 1. self assert: (constant between: 1 and: 63). machineCode at: 0 put: 2r1101001101 << 22 + (64 - constant << 16) + (63 - constant << 10) + (reg << 5) + reg. ^4! Item was added: + ----- Method: CogARMv8Compiler>>concretizeMoveCqR (in category 'generate machine code') ----- + concretizeMoveCqR + "C3.3.4 Move (immediate) C3-215 + + The Move (immediate) instructions are aliases for a single MOVZ, MOVN, or ORR (immediate with zero register), + instruction to load an immediate value into the destination register. An assembler must permit a signed or + unsigned immediate, as long as its binary representation can be generated using one of these instructions, + and an assembler error results if the immediate cannot be generated in this way. On disassembly, it is + unspecified whether the immediate is output as a signed or an unsigned value. + + C6.2.191 MOVZ C6-1102 Move wide with zero moves an optionally-shifted 16-bit immediate value to a register. + C6.2.190 MOVN C6-1100 Move wide with NOT moves the inverse of an optionally-shifted 16-bit immediate value to a register. + C6.2.204 ORR (immediate) C6-1125 + Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate + register value, and writes the result to the destination register." + + | constant destReg | + constant := operands at: 0. + destReg := operands at: 1. + destReg ~= SP ifTrue: + [| lowBit lowBitMod16 mask | + lowBit := constant > 0 + ifTrue: [self cCode: [self lowBit: constant] inSmalltalk: [constant lowBit - 1]] + ifFalse: [0]. + lowBitMod16 := lowBit // 16 * 16. + mask := 1 << 16 - 1 << lowBitMod16. + (constant bitAnd: mask) = constant ifTrue: + ["Use MOVZ" + machineCode + at: 0 + put: 2r110100101 << 23 + + (lowBitMod16 // 16 << 21) + + (constant >> lowBitMod16 << 5) + + destReg. + ^4]. + lowBit := constant signedIntFromLong64 < -1 + ifTrue: [self cCode: [self lowBit: constant bitInvert64] inSmalltalk: [constant bitInvert64 lowBit - 1]] + ifFalse: [0]. + (constant bitOr: mask) signedIntFromLong64 = -1 ifTrue: + ["Use MOVN" + self assert: (constant bitInvert64 >> lowBitMod16) = ((constant bitInvert64 >> lowBitMod16) bitAnd: mask). + machineCode + at: 0 + put: 2r100100101 << 23 + + (lowBitMod16 // 16 << 21) + + (constant bitInvert64 >> lowBitMod16 << 5) + + destReg. + ^4]]. + self isImmNImmSImmREncodableBitmask: constant + ifTrue: + [:n :imms :immr| "Use ORR" + machineCode + at: 0 + put: 2r1011001001 << 22 + + (immr << 16) + + (imms << 10) + + (XZR << 5) + + destReg. + ^4] + ifFalse: []. + ^self moveCw: constant intoR: destReg! Item was changed: ----- Method: CogARMv8Compiler>>concretizeMoveM16rR (in category 'generate machine code - concretize') ----- concretizeMoveM16rR + <inline: true> "C6.2.136 LDRH (immediate) C6-990" | offset destReg srcReg | offset := operands at: 0. srcReg := operands at: 1. destReg := operands at: 2. (offset between: -2048 and: 2047) ifTrue: [machineCode at: 0 put: 2r0111100101 << 22 + ((offset bitAnd: 1 << 12 - 1) << 10) + (srcReg << 5) + destReg. ^4] ifFalse: [self shouldBeImplemented]! Item was changed: ----- Method: CogARMv8Compiler>>concretizeMoveMbrR (in category 'generate machine code - concretize') ----- concretizeMoveMbrR + <inline: true> "C6.2.134 LDRB (immediate) C6-985" | offset destReg srcReg | offset := operands at: 0. srcReg := operands at: 1. destReg := operands at: 2. (offset between: -2048 and: 2047) ifTrue: [machineCode at: 0 put: 2r0011100101 << 22 + ((offset bitAnd: 1 << 12 - 1) << 10) + (srcReg << 5) + destReg. ^4] ifFalse: [self shouldBeImplemented]! Item was changed: ----- Method: CogARMv8Compiler>>concretizeMoveXwrRR (in category 'generate machine code - concretize') ----- concretizeMoveXwrRR + <inline: true> "Xwr - memory word whose address is r * word size away from an address in a register" "C6.2.132 LDR (register) C6-981" | index base dest | index := operands at: 0. base := operands at: 1. dest := operands at: 2. self deny: SP = dest. machineCode at: 0 put: 2r11111000011 << 21 + (index << 16) + (UXTX << 13) + (3 << 11) + (base << 5) + dest. ^4! Item was changed: ----- Method: CogARMv8Compiler>>concretizeNegateR (in category 'generate machine code - concretize') ----- concretizeNegateR + <inline: true> "C6.2.313 SUBS (extended register) C6-1318" | reg | reg := operands at: 0. self deny: SP = reg. machineCode at: 0 put: 2r11101011001 << 21 + (31 << 16) + (UXTX << 13) + (reg << 5) + reg. ^4! Item was added: + ----- Method: CogARMv8Compiler>>concretizePopR (in category 'generate machine code - concretize') ----- + concretizePopR + <inline: true> + "C6.2.273 LDR (immediate) C6-1239 + Post-index" + | reg | + reg := operands at: 0. + self deny: SP = reg. + machineCode + at: 0 + put: 2r1111100001 << 22 + + ((-8 bitAnd: 1 << 9 - 1) << 12) + + (2r01 << 10) + + (SP << 5) + + reg. + ^4! Item was added: + ----- Method: CogARMv8Compiler>>concretizePushR (in category 'generate machine code - concretize') ----- + concretizePushR + <inline: true> + "C6.2.273 STR (immediate) C6-1239 + Pre-index" + | reg | + reg := operands at: 0. + self deny: SP = reg. + machineCode + at: 0 + put: 2r11111 << 27 + + ((-8 bitAnd: 1 << 9 - 1) << 12) + + (2r11 << 10) + + (SP << 5) + + reg. + ^4! Item was changed: ----- Method: CogARMv8Compiler>>concretizeSubRR (in category 'generate machine code - concretize') ----- concretizeSubRR + <inline: true> "C6.2.313 SUBS (extended register) C6-1318" | destReg srcReg | srcReg := operands at: 0. destReg := operands at: 1. self deny: SP = destReg. machineCode at: 0 put: 2r11101011001 << 21 + (destReg << 16) + (UXTX << 13) + (srcReg << 5) + destReg. ^4! Item was added: + ----- Method: CogARMv8Compiler>>cond:br:reg: (in category 'generate machine code - support') ----- + cond: cond br: link reg: reg + self assert: link = 1. + self assert: cond = AL. + ^2r1101011000111111 << 16 + (reg << 5)! Item was added: + ----- Method: CogARMv8Compiler>>fullCallsAreRelative (in category 'abi') ----- + fullCallsAreRelative + "Answer if CallFull and/or JumpFull are relative and hence need relocating on method + compation. If so, they are annotated with IsRelativeCall in methods and relocated in + relocateIfCallOrMethodReference:mcpc:delta:" + ^false! Item was added: + ----- Method: CogARMv8Compiler>>genPushRegisterArgsForAbortMissNumArgs: (in category 'smalltalk calling convention') ----- + genPushRegisterArgsForAbortMissNumArgs: numArgs + "Ensure that the register args are pushed before the outer and + inner retpcs at an entry miss for arity <= self numRegArgs. The + outer retpc is that of a call at a send site. The inner is the call + from a method or PIC abort/miss to the trampoline." + + "Putting the receiver and args above the return address means the + CoInterpreter has a single machine-code frame format which saves + us a lot of work." + + "Iff there are register args convert + sp -> outerRetpc (send site retpc) + linkReg = innerRetpc (PIC abort/miss retpc) + to + base -> receiver + (arg0) + (arg1) + sp -> outerRetpc (send site retpc) + sp -> linkReg/innerRetpc (PIC abort/miss retpc)" + numArgs <= cogit numRegArgs ifTrue: + [self assert: cogit numRegArgs <= 2. + cogit MoveMw: 0 r: SPReg R: TempReg. "Save return address" + cogit MoveR: ReceiverResultReg Mw: 0 r: SPReg. + numArgs > 0 ifTrue: + [cogit PushR: Arg0Reg. + numArgs > 1 ifTrue: + [cogit PushR: Arg1Reg]]. + cogit PushR: TempReg]. "push back return address" + cogit PushR: LinkReg! Item was added: + ----- Method: CogARMv8Compiler>>genRemoveNArgsFromStack: (in category 'abi') ----- + genRemoveNArgsFromStack: n + "This is a no-op on ARM64 since the ABI passes up to 6 args in registers and trampolines currently observe that limit, using only 4." + <inline: true> + self assert: n <= 6. + ^0! Item was added: + ----- Method: CogARMv8Compiler>>genRestoreRegs: (in category 'abi') ----- + genRestoreRegs: regMask + "Restore the registers in regMask as saved by genSaveRegs:." + R0 to: R17 do: + [:reg| + (regMask anyMask: (cogit registerMaskFor: reg)) ifTrue: + [cogit PopR: reg]]. + ^0! Item was added: + ----- Method: CogARMv8Compiler>>isInImmediateBranchAndLinkRange: (in category 'testing') ----- + isInImmediateBranchAndLinkRange: offset + "ARM64 calls span +/- 128 mb. + C6.2.33 BL C6-812" + <var: #offset type: #'usqIntptr_t'> + self assert: (offset noMask: 3). + ^offset signedIntFromLong64 >> 27 between: -16r1 and: 0! Item was changed: ----- Method: CogARMv8Compiler>>isInImmediateBranchRange: (in category 'testing') ----- isInImmediateBranchRange: offset "ARM64 calls and jumps span +/- 1 mb." <var: #offset type: #'usqIntptr_t'> + self assert: (offset noMask: 3). + ^offset signedIntFromLong64 >> 18 between: -16r1 and: 0! - ^offset signedIntFromLong between: -16r100000 and: 16rFFFFC! Item was added: + ----- Method: CogARMv8Compiler>>literalLoadInstructionBytes (in category 'accessing') ----- + literalLoadInstructionBytes + "Answer the size of a literal load instruction (which does not include the size of the literal). + With out-of-line literals this is always a single LDR instruction that refers to the literal." + <inline: true> + ^4! Item was added: + ----- Method: CogARMv8Compiler>>nameForRegister: (in category 'printing') ----- + nameForRegister: reg "<Integer>" + <doNotGenerate> + | default | + default := super nameForRegister: reg. + ^default last = $? + ifTrue: + [reg = 31 + ifTrue: + ['SP/XZR'] + ifFalse: + [#(LR CArg0Reg CArg1Reg CArg2Reg CArg3Reg) + detect: [:sym| (thisContext method methodClass classPool at: sym) = reg] + ifNone: [default]]] + ifFalse: + [default]! Item was changed: ----- Method: CogAbstractInstruction>>computeJumpTargetOffsetPlus: (in category 'generate machine code') ----- computeJumpTargetOffsetPlus: anPCOffset <inline: true> "Since it's an extraction from other methods." | jumpTarget | <var: #jumpTarget type: #'AbstractInstruction *'> jumpTarget := self jumpTargetAddress. + ^objectMemory wordSize = 8 + ifTrue: [jumpTarget signedIntFromLong64 - (address + anPCOffset) signedIntFromLong64] + ifFalse: [jumpTarget signedIntFromLong - (address + anPCOffset) signedIntFromLong]! - ^jumpTarget signedIntFromLong - (address + anPCOffset) signedIntFromLong.! Item was changed: ----- Method: CogAbstractInstruction>>genLoadStackPointers (in category 'smalltalk calling convention') ----- genLoadStackPointers "Switch back to the Smalltalk stack. Assign SPReg first because typically it is used immediately afterwards." + cogit MoveAw: cogit stackPointerAddress R: SPReg. + cogit MoveAw: cogit framePointerAddress R: FPReg. + ^0! - self subclassResponsibility! Item was added: + ----- Method: CogAbstractInstruction>>genRemoveNArgsFromStack: (in category 'abi') ----- + genRemoveNArgsFromStack: n + "Remove n arguments from teh stack (iff any of the N arguments was passed on the stack)." + self subclassResponsibility! Item was added: + ----- Method: CogAbstractInstruction>>genRestoreRegs: (in category 'abi') ----- + genRestoreRegs: regMask + "Restore the registers in regMask as saved by genSaveRegs:." + self subclassResponsibility! Item was changed: ----- Method: CogAbstractInstruction>>printStateOn: (in category 'printing') ----- printStateOn: aStream | opcodeName orneryOperands format | <doNotGenerate> "Smalltalk-side only" opcode ifNil: [^self]. aStream space; nextPut: $(; nextPutAll: (opcodeName := self class nameForOpcode: opcode). orneryOperands := operands isCObjectAccessor ifTrue: [operands object] ifFalse: [operands]. format := ((CogRTLOpcodes classPool includesKey: opcodeName) ifTrue: [CogRTLOpcodes] ifFalse: [self class]) printFormatForOpcodeName: opcodeName. orneryOperands withIndexDo: [:operand :index| operand ifNotNil: [aStream space. index >= (orneryOperands identityIndexOf: nil ifAbsent: [orneryOperands size + 1]) ifTrue: [aStream print: index - 1; nextPut: $:]. (format notNil and: ['rf' includes: (format at: index ifAbsent: $-)]) ifTrue: [aStream nextPutAll: ((format at: index) = $r ifTrue: [self nameForRegister: operand] ifFalse: [self nameForFPRegister: operand])] ifFalse: [aStream print: operand. (operand isInteger and: [operand > 16 and: [opcode ~= Label]]) ifTrue: + [objectMemory wordSize = 8 + ifTrue: + [(operand allMask: 1 << 63) ifTrue: + [aStream nextPut: $/; print: operand signedIntFromLong64]] + ifFalse: + [(operand allMask: 1 << 31) ifTrue: + [aStream nextPut: $/; print: operand signedIntFromLong]]. - [(operand allMask: 16r80000000) ifTrue: - [aStream nextPut: $/; print: operand signedIntFromLong]. aStream nextPut: $/. operand printOn: aStream base: 16]]]]. machineCodeSize ifNotNil: [(machineCodeSize between: 1 and: machineCode size) ifTrue: [0 to: machineCodeSize - 1 by: self codeGranularity do: [:i| aStream space. (self machineCodeAt: i) ifNil: [aStream nextPut: $.] ifNotNil: [:mc| mc isInteger ifTrue: [mc printOn: aStream base: 16] ifFalse: [mc printOn: aStream]]]]]. address ifNotNil: [aStream nextPut: $@. address printOn: aStream base: 16]. aStream nextPut: $)! Item was changed: ----- Method: CogAbstractInstruction>>symbolicOn: (in category 'printing') ----- symbolicOn: aStream | orneryOperands | <doNotGenerate> "Smalltalk-side only" (machineCodeSize isNil or: [opcode = 16rAAA]) ifTrue: [^aStream nextPut: 'uninitialized opcode']. aStream space; nextPut: $(; nextPutAll: (self class nameForOpcode: opcode). orneryOperands := operands isCObjectAccessor ifTrue: [operands object] ifFalse: [operands]. orneryOperands withIndexDo: [:operand :index| operand ifNotNil: [aStream space. index >= (orneryOperands identityIndexOf: nil ifAbsent: [orneryOperands size + 1]) ifTrue: [aStream print: index - 1; nextPut: $:]. operand class == self class ifTrue: [operand symbolicOn: aStream] ifFalse: [aStream print: operand. (operand isInteger and: [operand > 16]) ifTrue: + [objectMemory wordSize = 8 + ifTrue: + [(operand allMask: 1 << 63) ifTrue: + [aStream nextPut: $/; print: operand signedIntFromLong64]] + ifFalse: + [(operand allMask: 1 << 31) ifTrue: + [aStream nextPut: $/; print: operand signedIntFromLong]]. - [(operand allMask: 16r80000000) ifTrue: - [aStream nextPut: $/; print: operand signedIntFromLong]. aStream nextPut: $/. operand printOn: aStream base: 16]]]]. machineCodeSize > 0 ifTrue: [machineCodeSize > machineCode size ifTrue: [aStream nextPutAll: ' no mcode'] ifFalse: [0 to: machineCodeSize - 1 by: self codeGranularity do: [:i| aStream space. (self machineCodeAt: i) printOn: aStream base: 16]]]. aStream nextPut: $)! Item was changed: ----- Method: CogAbstractRegisters class>>nameForRegister: (in category 'debug printing') ----- nameForRegister: reg "<Integer>" ^#(Arg0Reg Arg1Reg ClassReg FPReg ReceiverResultReg SPReg SendNumArgsReg TempReg LinkReg RISCTempReg VarBaseReg PCReg + Extra0Reg Extra1Reg Extra2Reg Extra3Reg Extra4Reg Extra5Reg Extra6Reg Extra7Reg) - Extra0Reg Extra1Reg Extra2Reg Extra3Reg Extra4Reg Extra5Reg) detect: [:sym| (classPool at: sym) = reg] ifNone: ['REG', reg printString, '?']! Item was removed: - ----- Method: CogIA32Compiler>>genLoadStackPointers (in category 'smalltalk calling convention') ----- - genLoadStackPointers - "Switch back to the Smalltalk stack. Assign SPReg first - because typically it is used immediately afterwards." - cogit MoveAw: cogit stackPointerAddress R: SPReg. - cogit MoveAw: cogit framePointerAddress R: FPReg. - ^0! Item was removed: - ----- Method: CogMIPSELCompiler>>genLoadStackPointers (in category 'smalltalk calling convention') ----- - genLoadStackPointers - "Switch back to the Smalltalk stack. Assign SPReg first - because typically it is used immediately afterwards." - cogit MoveAw: cogit stackPointerAddress R: SPReg. - cogit MoveAw: cogit framePointerAddress R: FPReg. - ^0! Item was removed: - ----- Method: CogX64Compiler>>genLoadStackPointers (in category 'smalltalk calling convention') ----- - genLoadStackPointers - "Switch back to the Smalltalk stack. Assign SPReg first - because typically it is used immediately afterwards." - cogit MoveAw: cogit stackPointerAddress R: SPReg. - cogit MoveAw: cogit framePointerAddress R: FPReg. - ^0! Item was changed: ----- Method: Cogit>>compileCallFor:numArgs:arg:arg:arg:arg:floatResultReg:regsToSave: (in category 'initialization') ----- compileCallFor: aRoutine numArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3 floatResultReg: resultRegOrNone regsToSave: regMask "Generate a call to aRoutine with up to 4 arguments. If resultRegOrNone is not NoReg assign the C result to resultRegOrNone. If saveRegs, save all registers. Hack: a negative arg value indicates an abstract register, a non-negative value indicates a constant." <var: #aRoutine type: #'void *'> <inline: false> | regsToSave | regsToSave := resultRegOrNone = NoReg ifTrue: [regMask] ifFalse: [regMask bitClear: (self registerMaskFor: resultRegOrNone)]. cStackAlignment > objectMemory wordSize ifTrue: [backEnd genAlignCStackSavingRegisters: regsToSave numArgs: numArgs wordAlignment: cStackAlignment / objectMemory wordSize]. backEnd genSaveRegs: regsToSave; genMarshallNArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3. self CallFullRT: (self cCode: [aRoutine asUnsignedInteger] inSmalltalk: [self simulatedTrampolineFor: aRoutine]). resultRegOrNone ~= NoReg ifTrue: [backEnd cFloatResultToRd: resultRegOrNone]. + backEnd + genRemoveNArgsFromStack: numArgs; + genRestoreRegs: regsToSave! - backEnd genRemoveNArgsFromStack: numArgs. - backEnd genRestoreRegs: regsToSave!

1 0

VM Maker: VMMaker.oscog-eem.2610.mcz
by commits＠source.squeak.org 09 Dec '19

09 Dec '19

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2610.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2610 Author: eem Time: 8 December 2019, 9:04:37.440523 pm UUID: fc46f0b9-0842-4d46-88b0-98097a972574 Ancestors: VMMaker.oscog-eem.2609 A64 several parts of the ABI-compliant call glue filled out. Eliminate duplication in genLoadCStackPointers, genSaveStackPointers, genSaveRegs:. These can all be implemented in CogAbstractInstruction. =============== Diff against VMMaker.oscog-eem.2609 =============== Item was removed: - ----- Method: CogARMCompiler>>genLoadCStackPointers (in category 'smalltalk calling convention') ----- - genLoadCStackPointers - "Load the frame and stack pointer registers with those of the C stack, - effecting a switch to the C stack. Used when machine code calls into - the CoInterpreter run-time (e.g. to invoke interpreter primitives)." - cogit MoveAw: cogit cStackPointerAddress R: SPReg. - cogit MoveAw: cogit cFramePointerAddress R: FPReg. - ^0! Item was changed: ----- Method: CogARMCompiler>>genPushRegisterArgsForNumArgs:scratchReg: (in category 'smalltalk calling convention') ----- genPushRegisterArgsForNumArgs: numArgs scratchReg: ignored "Ensure that the register args are pushed before the retpc for arity <= self numRegArgs." "This is easy on a RISC like ARM because the return address is in the link register. Putting the receiver and args above the return address means the CoInterpreter has a single machine-code frame format which saves us a lot of work NOTA BENE: we do NOT push the return address here, which means it must be dealt with later." numArgs <= cogit numRegArgs ifTrue: [self assert: cogit numRegArgs <= 2. cogit PushR: ReceiverResultReg. + numArgs > 0 ifTrue: - numArgs > 0 ifTrue: [cogit PushR: Arg0Reg. numArgs > 1 ifTrue: [cogit PushR: Arg1Reg]]]! Item was removed: - ----- Method: CogARMCompiler>>genSaveStackPointers (in category 'smalltalk calling convention') ----- - genSaveStackPointers - "Save the frame and stack pointer registers to the framePointer - and stackPointer variables. Used to save the machine code frame - for use by the run-time when calling into the CoInterpreter run-time." - cogit MoveR: FPReg Aw: cogit framePointerAddress. - cogit MoveR: SPReg Aw: cogit stackPointerAddress. - ^0! Item was changed: CogAbstractInstruction subclass: #CogARMv8Compiler instanceVariableNames: '' + classVariableNames: 'AL AddOpcode AndOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CS CmpOpcode D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 EQ FP GE GT HI LE LR LS LT MI NE OrOpcode PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 SP SXTB SXTH SXTW SXTX SubOpcode UXTB UXTH UXTW UXTX VC VS XZR XorOpcode' - classVariableNames: 'AL AddOpcode AndOpcode CC CS CmpOpcode D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 EQ FP GE GT HI LE LR LS LT MI NE OrOpcode PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 SP SXTB SXTH SXTW SXTX SubOpcode UXTB UXTH UXTW UXTX VC VS XZR XorOpcode' poolDictionaries: 'ARMv8A64Opcodes' category: 'VMMaker-JIT'! !CogARMv8Compiler commentStamp: 'eem 12/3/2019 08:45' prior: 0! I generate ARMv8 machine code instructions from CogAbstractInstructions with CogRTLOpcodes. Here in "Arm ARM" refers to Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-ma… Some things to know about ARMv8 instructions: Whether 31 in a register field implies the zero register or the SP register(s) depends on the specific instruction. C3.2.1 Load/Store register If a Load instruction specifies writeback and the register being loaded is also the base register, then behavior is CONSTRAINED UNPREDICTABLE and one of the following behaviors must occur: - The instruction is treated as UNDEFINED. - The instruction is treated as a NOP. - The instruction performs the load using the specified addressing mode and the base register becomes UNKNOWN. In addition, if an exception occurs during the execution of such an instruction, the base address might be corrupted so that the instruction cannot be repeated. If a Store instruction performs a writeback and the register that is stored is also the base register, then behavior is CONSTRAINED UNPREDICTABLE and one of the following behaviors must occur: - The instruction is treated as UNDEFINED. - The instruction is treated as a NOP. - The instruction performs the store to the designated register using the specified addressing mode, but the value stored is UNKNOWN.! Item was changed: ----- Method: CogARMv8Compiler class>>initialize (in category 'class initialization') ----- initialize "Initialize various ARM64 instruction-related constants." "self initialize" "main registers; a minor complication in reading the doc. ARM refer to the 64bit registers as X0...30 and use R0...30 to refer to the 32bit lower halves.They also use a whole suite of names for the floating point/SIMD registers. See ARMARM DDI0487 B1.2.1 etc for the gory details. Note that R30 (yes, yes, X30) is used as the link register and as such is not really a general purpose register. Also note that R31 (named XZR in ARM doc) is a pseudo-register that always reads as 0 and writes to /dev/null. And note that unlike the ARM32, there is no general purpose register for either the PC or SP; a big difference. See ARMARM DDI0487 C1.2.5. wrt to both issues. We will stick with R0...30 to refer to the 64 bit general regs and D0...31 (note the extra reg here!!) for the FP/SIMD regs" #( (D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31) (R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31)) do: [:classVarNames| classVarNames doWithIndex: [:k :v| CogARMv8Compiler classPool at: k put: v - 1]]. SP := XZR := R31. LR := R30. FP := R29. + CArg0Reg := R0. + CArg1Reg := R1. + CArg2Reg := R2. + CArg3Reg := R3. + "Condition Codes. Note that cc=16rF is mapped back to AL in AARCH64. Generally it shouldn't be used" "Perhaps have these in the ARMv8A64Opcodes pool?" EQ := 0. NE := 1. CS := 2. CC := 3. MI := 4. PL := 5. VS := 6. VC := 7. HI := 8. LS := 9. GE := 10. LT := 11. GT := 12. LE := 13. AL := 14. "Extension Methods " UXTB := 2r000. UXTH := 2r001. UXTW := 2r010. UXTX := 2r011. "a.k.a. LSL" SXTB := 2r100. SXTH := 2r101. SXTW := 2r110. SXTX := 2r111! Item was added: + ----- Method: CogARMv8Compiler>>genMarshallNArgs:arg:arg:arg:arg: (in category 'abi') ----- + genMarshallNArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3 + "Generate the code to pass up to four arguments in a C run-time call. Hack: each argument is + either a negative number, which encodes a constant, or a non-negative number, that of a register. + + Run-time calls have no more than four arguments, so chosen so that on ARM, where in its C ABI the + first four integer arguments are passed in registers, all arguments can be passed in registers. We + defer to the back end to generate this code not so much that the back end knows whether it uses + the stack or registers to pass arguments (it does, but...). In fact we defer for an extremely evil reason. + Doing so allows the x64 (where up to 6 args are passed) to assign the register arguments in an order + that allows some of the argument registers to be used for specific abstract registers, specifically + ReceiverResultReg and ClassReg. This is evil, evil, evil, but also it's really nice to keep using the old + register assignments the original author has grown accustomed to." + <inline: true> + numArgs = 0 ifTrue: [^self]. + "Avoid arg regs being overwritten before they are read." + numArgs > 1 ifTrue: + [((cogit isTrampolineArgConstant: regOrConst1) not + and: [regOrConst1 = CArg0Reg]) ifTrue: + [cogit MoveR: regOrConst1 R: Extra0Reg. + ^self genMarshallNArgs: numArgs arg: regOrConst0 arg: Extra0Reg arg: regOrConst2 arg: regOrConst3]. + numArgs > 2 ifTrue: + [((cogit isTrampolineArgConstant: regOrConst2) not + and: [regOrConst2 = CArg0Reg or: [regOrConst2 = CArg1Reg]]) ifTrue: + [cogit MoveR: regOrConst2 R: Extra1Reg. + ^self genMarshallNArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: Extra1Reg arg: regOrConst3]. + numArgs > 3 ifTrue: + [((cogit isTrampolineArgConstant: regOrConst3) not + and: [regOrConst3 = CArg0Reg or: [regOrConst3 = CArg1Reg or: [regOrConst3 = CArg2Reg]]]) ifTrue: + [cogit MoveR: regOrConst3 R: Extra2Reg. + ^self genMarshallNArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: Extra2Reg]]]]. + (cogit isTrampolineArgConstant: regOrConst0) + ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst0) R: CArg0Reg] + ifFalse: [cogit MoveR: regOrConst0 R: CArg0Reg]. + numArgs = 1 ifTrue: [^self]. + (cogit isTrampolineArgConstant: regOrConst1) + ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst1) R: CArg1Reg] + ifFalse: [cogit MoveR: regOrConst1 R: CArg1Reg]. + numArgs = 2 ifTrue: [^self]. + (cogit isTrampolineArgConstant: regOrConst2) + ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst2) R: CArg2Reg] + ifFalse: [cogit MoveR: regOrConst2 R: CArg2Reg]. + numArgs = 3 ifTrue: [^self]. + (cogit isTrampolineArgConstant: regOrConst3) + ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst3) R: CArg3Reg] + ifFalse: [cogit MoveR: regOrConst3 R: CArg3Reg]! Item was added: + ----- Method: CogARMv8Compiler>>genPushRegisterArgsForNumArgs:scratchReg: (in category 'smalltalk calling convention') ----- + genPushRegisterArgsForNumArgs: numArgs scratchReg: ignored + "Ensure that the register args are pushed before the retpc for arity <= self numRegArgs." + "This is easy on a RISC like ARM because the return address is in the link register. Putting + the receiver and args above the return address means the CoInterpreter has a single + machine-code frame format which saves us a lot of work + NOTA BENE: we do NOT push the return address here, which means it must be dealt with later." + numArgs <= cogit numRegArgs ifTrue: + [self assert: cogit numRegArgs <= 2. + cogit PushR: ReceiverResultReg. + numArgs > 0 ifTrue: + [cogit PushR: Arg0Reg. + numArgs > 1 ifTrue: + [cogit PushR: Arg1Reg]]]! Item was added: + ----- Method: CogARMv8Compiler>>genSaveRegs: (in category 'abi') ----- + genSaveRegs: regMask + "Save the registers in regMask for a call into the C run-time from a trampoline." + R17 to: R0 by: -1 do: + [:reg| + (regMask anyMask: (cogit registerMaskFor: reg)) ifTrue: + [cogit PushR: reg]]. + ^0! Item was added: + ----- Method: CogARMv8Compiler>>numIntRegArgs (in category 'accessing') ----- + numIntRegArgs + "See e.g. http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_… + Table 3-1 Register Usage in AArch64 SMC32, HVC32, SMC64, and HVC64 calls" + ^6! Item was changed: ----- Method: CogARMv8Compiler>>usesOutOfLineLiteral (in category 'testing') ----- usesOutOfLineLiteral "Answer if the receiver uses an out-of-line literal. Needs only to work for the opcodes created with gen:literal:operand: et al." opcode caseOf: { [CallFull] -> [^true]. [JumpFull] -> [^true]. "Arithmetic" [AddCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [AndCqR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. [AndCqRR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. [CmpCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [OrCqR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. [SubCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [TstCqR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. [XorCqR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. [AddCwR] -> [^true]. [AndCwR] -> [^true]. [CmpCwR] -> [^true]. [OrCwR] -> [^true]. [SubCwR] -> [^true]. [XorCwR] -> [^true]. "[LoadEffectiveAddressMwrR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| false] ifFalse: [true]]." "Data Movement" + [MoveCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. - "[MoveCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| false] ifFalse: [true]]." [MoveCwR] -> [^(self inCurrentCompilation: (operands at: 0)) not]. [MoveAwR] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) not]. [MoveRAw] -> [^(self isAddressRelativeToVarBase: (operands at: 1)) not]. [MoveAbR] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) not]. [MoveRAb] -> [^(self isAddressRelativeToVarBase: (operands at: 1)) not]. [MoveMwrR] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveRMwr] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 1) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveMbrR] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveRMbr] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 1) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveM16rR] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveRM16r] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 1) ifTrue: [:shift12|false] ifFalse:[true]]. "[MoveRdM64r] -> [^self is12BitValue: (operands at: 1) ifTrue: [:u :i| false] ifFalse: [true]]. [MoveM64rRd] -> [^self is12BitValue: (operands at: 0) ifTrue: [:u :i| false] ifFalse: [true]]." [PushCw] -> [^(self inCurrentCompilation: (operands at: 0)) not]. "[PushCq] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| false] ifFalse: [true]]." [PrefetchAw] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) not]. } otherwise: [self assert: false]. ^false "to keep C compiler quiet" ! Item was changed: ----- Method: CogAbstractInstruction>>genLoadCStackPointers (in category 'smalltalk calling convention') ----- genLoadCStackPointers "Load the frame and stack pointer registers with those of the C stack, effecting a switch to the C stack. Used when machine code calls into the CoInterpreter run-time (e.g. to invoke interpreter primitives)." + cogit MoveAw: cogit cStackPointerAddress R: SPReg. + cogit MoveAw: cogit cFramePointerAddress R: FPReg. + ^0! - self subclassResponsibility! Item was added: + ----- Method: CogAbstractInstruction>>genSaveRegs: (in category 'abi') ----- + genSaveRegs: regMask + "Save the registers in regMask for a call into the C run-time from a trampoline" + self subclassResponsibility! Item was changed: ----- Method: CogAbstractInstruction>>genSaveStackPointers (in category 'smalltalk calling convention') ----- genSaveStackPointers "Save the frame and stack pointer registers to the framePointer and stackPointer variables. Used to save the machine code frame for use by the run-time when calling into the CoInterpreter run-time." + cogit MoveR: FPReg Aw: cogit framePointerAddress. + cogit MoveR: SPReg Aw: cogit stackPointerAddress. + ^0! - self subclassResponsibility! Item was removed: - ----- Method: CogIA32Compiler>>genLoadCStackPointers (in category 'smalltalk calling convention') ----- - genLoadCStackPointers - "Load the frame and stack pointer registers with those of the C stack, - effecting a switch to the C stack. Used when machine code calls into - the CoInterpreter run-time (e.g. to invoke interpreter primitives)." - cogit MoveAw: cogit cStackPointerAddress R: SPReg. - cogit MoveAw: cogit cFramePointerAddress R: FPReg. - ^0! Item was removed: - ----- Method: CogIA32Compiler>>genSaveStackPointers (in category 'smalltalk calling convention') ----- - genSaveStackPointers - "Save the frame and stack pointer registers to the framePointer - and stackPointer variables. Used to save the machine code frame - for use by the run-time when calling into the CoInterpreter run-time." - cogit MoveR: FPReg Aw: cogit framePointerAddress. - cogit MoveR: SPReg Aw: cogit stackPointerAddress. - ^0! Item was removed: - ----- Method: CogMIPSELCompiler>>genLoadCStackPointers (in category 'smalltalk calling convention') ----- - genLoadCStackPointers - "Load the frame and stack pointer registers with those of the C stack, - effecting a switch to the C stack. Used when machine code calls into - the CoInterpreter run-time (e.g. to invoke interpreter primitives)." - cogit MoveAw: cogit cStackPointerAddress R: SPReg. - cogit MoveAw: cogit cFramePointerAddress R: FPReg. - ^0! Item was removed: - ----- Method: CogMIPSELCompiler>>genSaveStackPointers (in category 'smalltalk calling convention') ----- - genSaveStackPointers - "Save the frame and stack pointer registers to the framePointer - and stackPointer variables. Used to save the machine code frame - for use by the run-time when calling into the CoInterpreter run-time." - cogit MoveR: FPReg Aw: cogit framePointerAddress. - cogit MoveR: SPReg Aw: cogit stackPointerAddress. - ^0! Item was removed: - ----- Method: CogX64Compiler>>genLoadCStackPointers (in category 'smalltalk calling convention') ----- - genLoadCStackPointers - "Load the frame and stack pointer registers with those of the C stack, - effecting a switch to the C stack. Used when machine code calls into - the CoInterpreter run-time (e.g. to invoke interpreter primitives)." - cogit MoveAw: cogit cStackPointerAddress R: SPReg. - cogit MoveAw: cogit cFramePointerAddress R: FPReg. - ^0! Item was removed: - ----- Method: CogX64Compiler>>genSaveStackPointers (in category 'smalltalk calling convention') ----- - genSaveStackPointers - "Save the frame and stack pointer registers to the framePointer - and stackPointer variables. Used to save the machine code frame - for use by the run-time when calling into the CoInterpreter run-time." - cogit MoveR: FPReg Aw: cogit framePointerAddress. - cogit MoveR: SPReg Aw: cogit stackPointerAddress. - ^0!

1 0

VM Maker: VMMaker.oscog-eem.2609.mcz
by commits＠source.squeak.org 09 Dec '19

09 Dec '19

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2609.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2609 Author: eem Time: 8 December 2019, 8:41:23.17819 pm UUID: 0fb74a7b-5bfc-48f0-a4c0-4d56b0f20c62 Ancestors: VMMaker.oscog-eem.2608 A64 fix bugs in LogicalShiftLeftCqR, MoveM16rR, MoveMbrR, MoveXwrRR & cond:br:offset:. =============== Diff against VMMaker.oscog-eem.2608 =============== Item was changed: ----- Method: CogARMv8Compiler>>concretizeLogicalShiftLeftCqR (in category 'generate machine code - concretize') ----- concretizeLogicalShiftLeftCqR "C6.2.17 ASR (immediate) C6-785 100100110 (1) C6.2.177 LSL (immediate) C6-1075 110100110 (1) C6.2.180 LSR (immediate) C6-1081 110100110 (1)" | reg constant | constant := operands at: 0. reg := operands at: 1. self assert: (constant between: 1 and: 63). machineCode at: 0 put: 2r1101001101 << 22 + + (64 - constant << 16) + + (63 - constant << 10) - + (constant << 16) - + (63 << 10) + (reg << 5) + reg. ^4! Item was changed: ----- Method: CogARMv8Compiler>>concretizeMoveM16rR (in category 'generate machine code - concretize') ----- concretizeMoveM16rR + "C6.2.136 LDRH (immediate) C6-990" - "C6.2.168 LDURH C6-1061" | offset destReg srcReg | offset := operands at: 0. srcReg := operands at: 1. destReg := operands at: 2. + (offset between: -2048 and: 2047) - (offset between: -256 and: 255) ifTrue: [machineCode at: 0 + put: 2r0111100101 << 22 + + ((offset bitAnd: 1 << 12 - 1) << 10) - put: 2r0111100001 << 22 - + ((offset bitAnd: 1 << 9 - 1) << 12) + (srcReg << 5) + destReg. ^4] ifFalse: [self shouldBeImplemented]! Item was changed: ----- Method: CogARMv8Compiler>>concretizeMoveMbrR (in category 'generate machine code - concretize') ----- concretizeMoveMbrR + "C6.2.134 LDRB (immediate) C6-985" - "C6.2.167 LDURB C6-1060" | offset destReg srcReg | offset := operands at: 0. srcReg := operands at: 1. destReg := operands at: 2. + (offset between: -2048 and: 2047) - (offset between: -256 and: 255) ifTrue: [machineCode at: 0 + put: 2r0011100101 << 22 + + ((offset bitAnd: 1 << 12 - 1) << 10) - put: 2r0011100001 << 22 - + ((offset bitAnd: 1 << 9 - 1) << 12) + (srcReg << 5) + destReg. ^4] ifFalse: [self shouldBeImplemented]! Item was changed: ----- Method: CogARMv8Compiler>>concretizeMoveXwrRR (in category 'generate machine code - concretize') ----- concretizeMoveXwrRR "Xwr - memory word whose address is r * word size away from an address in a register" "C6.2.132 LDR (register) C6-981" + | index base dest | + index := operands at: 0. + base := operands at: 1. + dest := operands at: 2. + self deny: SP = dest. - | destReg srcReg | - srcReg := operands at: 0. - destReg := operands at: 1. - self deny: SP = destReg. machineCode at: 0 put: 2r11111000011 << 21 + + (index << 16) - + (destReg << 16) + (UXTX << 13) + + (3 << 11) + + (base << 5) + + dest. - + (1 << 12) - + (srcReg << 5) - + destReg. ^4! Item was changed: ----- Method: CogARMv8Compiler>>cond:br:offset: (in category 'generate machine code - support') ----- cond: cond br: link offset: offset self assert: link = 0. + self assert: (offset bitAnd: 3) = 0. ^2r010101 << 26 + + ((offset bitAnd: 1 << 19 - 1) << 3) - + ((offset bitAnd: 1 << 19 - 1) << 5) + cond! Item was changed: ----- Method: CogARMv8Compiler>>dispatchConcretize (in category 'generate machine code') ----- dispatchConcretize "Attempt to generate concrete machine code for the instruction at address. This is the inner dispatch of concretizeAt: actualAddress which exists only to get around the branch size limits in the SqueakV3 (blue book derived) bytecode set." opcode caseOf: { "Noops & Pseudo Ops" [Label] -> [^self concretizeLabel]. [Literal] -> [^self concretizeLiteral]. [AlignmentNops] -> [^self concretizeAlignmentNops]. [Fill32] -> [^self concretizeFill32]. [Nop] -> [^self concretizeNop]. "Control" [Call] -> [^self concretizeCall]. "call code within code space" [CallFull] -> [^self concretizeCallFull]. "call code anywhere in address space" [JumpR] -> [^self concretizeJumpR]. [JumpFull] -> [^self concretizeJumpFull]."jump within address space" [JumpLong] -> [^self concretizeConditionalJump: AL]."jumps witihn code space" [JumpLongZero] -> [^self concretizeConditionalJump: EQ]. [JumpLongNonZero] -> [^self concretizeConditionalJump: NE]. [Jump] -> [^self concretizeConditionalJump: AL]. [JumpZero] -> [^self concretizeConditionalJump: EQ]. [JumpNonZero] -> [^self concretizeConditionalJump: NE]. [JumpNegative] -> [^self concretizeConditionalJump: MI]. [JumpNonNegative] -> [^self concretizeConditionalJump: PL]. [JumpOverflow] -> [^self concretizeConditionalJump: VS]. [JumpNoOverflow] -> [^self concretizeConditionalJump: VC]. [JumpCarry] -> [^self concretizeConditionalJump: CS]. [JumpNoCarry] -> [^self concretizeConditionalJump: CC]. [JumpLess] -> [^self concretizeConditionalJump: LT]. [JumpGreaterOrEqual] -> [^self concretizeConditionalJump: GE]. [JumpGreater] -> [^self concretizeConditionalJump: GT]. [JumpLessOrEqual] -> [^self concretizeConditionalJump: LE]. [JumpBelow] -> [^self concretizeConditionalJump: CC]. "unsigned lower" [JumpAboveOrEqual] -> [^self concretizeConditionalJump: CS]. "unsigned greater or equal" [JumpAbove] -> [^self concretizeConditionalJump: HI]. [JumpBelowOrEqual] -> [^self concretizeConditionalJump: LS]. [JumpFPEqual] -> [^self concretizeFPConditionalJump: EQ]. [JumpFPNotEqual] -> [^self concretizeFPConditionalJump: NE]. [JumpFPLess] -> [^self concretizeFPConditionalJump: LT]. [JumpFPGreaterOrEqual] -> [^self concretizeFPConditionalJump: GE]. [JumpFPGreater] -> [^self concretizeFPConditionalJump: GT]. [JumpFPLessOrEqual] -> [^self concretizeFPConditionalJump: LE]. [JumpFPOrdered] -> [^self concretizeFPConditionalJump: VC]. [JumpFPUnordered] -> [^self concretizeFPConditionalJump: VS]. [RetN] -> [^self concretizeRetN]. [Stop] -> [^self concretizeStop]. "Arithmetic" [AddCqR] -> [^self concretizeAddCqR]. + [AndCqR] -> [^self concretizeAndCqRDest: (operands at: 1)]. + [AndCqRR] -> [^self concretizeAndCqRDest: (operands at: 2)]. - [AndCqR] -> [^self concretizeInvertibleDataOperationCqR: AndOpcode]. - [AndCqRR] -> [^self concretizeAndCqRDest: (operands at: 1)]. [CmpCqR] -> [^self concretizeCmpCqR]. [OrCqR] -> [^self concretizeDataOperationCqR: OrOpcode]. [SubCqR] -> [^self concretizeSubCqR]. [TstCqR] -> [^self concretizeAndCqRDest: XZR]. [XorCqR] -> [^self concretizeInvertibleDataOperationCqR: XorOpcode]. [AddCwR] -> [^self concretizeDataOperationCwR: AddOpcode]. [AndCwR] -> [^self concretizeDataOperationCwR: AndOpcode]. [CmpCwR] -> [^self concretizeDataOperationCwR: CmpOpcode]. [OrCwR] -> [^self concretizeDataOperationCwR: OrOpcode]. [SubCwR] -> [^self concretizeDataOperationCwR: SubOpcode]. [XorCwR] -> [^self concretizeDataOperationCwR: XorOpcode]. [AddRR] -> [^self concretizeAddRR]. [AndRR] -> [^self concretizeDataOperationRR: AndOpcode]. [CmpRR] -> [^self concretizeDataOperationRR: CmpOpcode]. [OrRR] -> [^self concretizeDataOperationRR: OrOpcode]. [SubRR] -> [^self concretizeSubRR]. [XorRR] -> [^self concretizeDataOperationRR: XorOpcode]. [AddRdRd] -> [^self concretizeAddRdRd]. [CmpRdRd] -> [^self concretizeCmpRdRd]. [DivRdRd] -> [^self concretizeDivRdRd]. [MulRdRd] -> [^self concretizeMulRdRd]. [SubRdRd] -> [^self concretizeSubRdRd]. [SqrtRd] -> [^self concretizeSqrtRd]. [NegateR] -> [^self concretizeNegateR]. [LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR]. [ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR]. [LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR]. [LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR]. [ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR]. [LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR]. [LogicalShiftRightRR] -> [^self concretizeLogicalShiftRightRR]. [ClzRR] -> [^self concretizeClzRR]. "Data Movement" [MoveCqR] -> [^self concretizeMoveCqR]. [MoveCwR] -> [^self concretizeMoveCwR]. [MoveRR] -> [^self concretizeMoveRR]. [MoveAwR] -> [^self concretizeMoveAwR]. [MoveRAw] -> [^self concretizeMoveRAw]. [MoveAbR] -> [^self concretizeMoveAbR]. [MoveRAb] -> [^self concretizeMoveRAb]. [MoveMbrR] -> [^self concretizeMoveMbrR]. [MoveRMbr] -> [^self concretizeMoveRMbr]. [MoveRM16r] -> [^self concretizeMoveRM16r]. [MoveM16rR] -> [^self concretizeMoveM16rR]. [MoveM64rRd] -> [^self concretizeMoveM64rRd]. [MoveMwrR] -> [^self concretizeMoveMwrR]. [MoveXbrRR] -> [^self concretizeMoveXbrRR]. [MoveRXbrR] -> [^self concretizeMoveRXbrR]. [MoveXwrRR] -> [^self concretizeMoveXwrRR]. [MoveRXwrR] -> [^self concretizeMoveRXwrR]. [MoveRMwr] -> [^self concretizeMoveRMwr]. [MoveRdM64r] -> [^self concretizeMoveRdM64r]. [PopR] -> [^self concretizePopR]. [PushR] -> [^self concretizePushR]. [PushCq] -> [^self concretizePushCq]. [PushCw] -> [^self concretizePushCw]. [PrefetchAw] -> [^self concretizePrefetchAw]. "Conversion" [ConvertRRd] -> [^self concretizeConvertRRd]. [ConvertRdR] -> [^self concretizeConvertRdR]. [ConvertRRs] -> [^self concretizeConvertRRs]. [ConvertRsR] -> [^self concretizeConvertRsR]. [ConvertRsRd] -> [^self concretizeConvertRsRd]. [ConvertRdRs] -> [^self concretizeConvertRdRs]. [SignExtend8RR] -> [^self concretizeSignExtend8RR]. [SignExtend16RR] -> [^self concretizeSignExtend16RR]. [SignExtend32RR] -> [^self concretizeSignExtend32RR]. [ZeroExtend8RR] -> [^self concretizeZeroExtend8RR]. [ZeroExtend16RR] -> [^self concretizeZeroExtend16RR]. [ZeroExtend32RR] -> [^self concretizeZeroExtend32RR] }. ^0 "keep Slang happy"! Item was changed: ----- Method: CogARMv8Compiler>>isImmNImmSImmREncodableBitmask:ifTrue:ifFalse: (in category 'generate machine code - support') ----- isImmNImmSImmREncodableBitmask: constant ifTrue: trinaryBlock "[:n :imms :immr|...]" ifFalse: nullaryBlock "See DecodeBitMasks J1-7389. See https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/ This method is adapted from The LLVM Compiler Infrastructure, AArch64AddressingModes.h processLogicalImmediate" <inline: #always> | imm size mask countLeadingOnes countTrailingOnes immr n nImms rotateCount | (constant between: -1 and: 0) ifTrue: [^nullaryBlock value]. + imm := self cCode: [constant] inSmalltalk: [constant signedIntToLong64]. - imm := constant. "First, determine the element size." size := 32. [mask := 1 << size - 1. (imm bitAnd: mask) ~= (imm >> size) ifTrue: [size := size * 2. false] ifFalse: [size > 2]] whileTrue: [size := size / 2]. "Second, determine the rotation to make the element be: 0^m 1^n." mask := 1 << 64 - 1 >> (64 - size). imm := imm bitAnd: mask. (self isShiftedMask: imm) ifTrue: [rotateCount := self countTrailingZeros: imm. countTrailingOnes := self countTrailingOnes: imm >> rotateCount] ifFalse: [imm := imm bitOr: mask bitInvert64. (self isShiftedMask: imm) ifFalse: [^nullaryBlock value]. countLeadingOnes := self countLeadingOnes: imm. rotateCount := 64 - countLeadingOnes. countTrailingOnes := countLeadingOnes + (self countTrailingOnes: imm) - (64 - size)]. "Encode in Immr the number of RORs it would take to get *from* 0^m 1^n to our target value, where I is the number of RORs to go the opposite direction." self assert: size > rotateCount. "rotateCount should be smaller than element size" immr := size - rotateCount bitAnd: size - 1. "If size has a 1 in the n'th bit, create a value that has zeroes in bits [0, n] and ones above that." nImms := (size - 1) bitInvert64 << 1. "Or the CTO value into the low bits, which must be below the Nth bit mentioned above." nImms := nImms bitOr: countTrailingOnes - 1. "Extract the seventh bit and toggle it to create the N field." n := ((nImms >> 6) bitAnd: 1) bitXor: 1. nImms := nImms bitAnd: 16r3F. + self assert: (self decode64Imms: nImms immr: immr) = constant signedIntToLong64. - self assert: (self decode64Imms: nImms immr: immr) = constant. ^trinaryBlock value: n value: nImms value: immr ! Item was changed: ----- Method: CogARMv8Compiler>>usesOutOfLineLiteral (in category 'testing') ----- usesOutOfLineLiteral "Answer if the receiver uses an out-of-line literal. Needs only to work for the opcodes created with gen:literal:operand: et al." opcode caseOf: { [CallFull] -> [^true]. [JumpFull] -> [^true]. "Arithmetic" [AddCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. + [AndCqR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. + [AndCqRR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. - [AndCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. - [AndCqRR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [CmpCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. + [OrCqR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. - [OrCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [SubCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. + [TstCqR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. + [XorCqR] -> [^self isImmNImmSImmREncodableBitmask: (operands at: 0) ifTrue: [:n :imms :immr|false] ifFalse:[true]]. - [TstCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. - [XorCqR] -> [^self isPossiblyShiftableImm12: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [AddCwR] -> [^true]. [AndCwR] -> [^true]. [CmpCwR] -> [^true]. [OrCwR] -> [^true]. [SubCwR] -> [^true]. [XorCwR] -> [^true]. "[LoadEffectiveAddressMwrR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| false] ifFalse: [true]]." "Data Movement" "[MoveCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| false] ifFalse: [true]]." [MoveCwR] -> [^(self inCurrentCompilation: (operands at: 0)) not]. [MoveAwR] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) not]. [MoveRAw] -> [^(self isAddressRelativeToVarBase: (operands at: 1)) not]. [MoveAbR] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) not]. [MoveRAb] -> [^(self isAddressRelativeToVarBase: (operands at: 1)) not]. [MoveMwrR] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveRMwr] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 1) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveMbrR] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveRMbr] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 1) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveM16rR] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 0) ifTrue: [:shift12|false] ifFalse:[true]]. [MoveRM16r] -> [^self isPossiblyShiftableImm12orImm9: (operands at: 1) ifTrue: [:shift12|false] ifFalse:[true]]. "[MoveRdM64r] -> [^self is12BitValue: (operands at: 1) ifTrue: [:u :i| false] ifFalse: [true]]. [MoveM64rRd] -> [^self is12BitValue: (operands at: 0) ifTrue: [:u :i| false] ifFalse: [true]]." [PushCw] -> [^(self inCurrentCompilation: (operands at: 0)) not]. "[PushCq] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| false] ifFalse: [true]]." [PrefetchAw] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) not]. } otherwise: [self assert: false]. ^false "to keep C compiler quiet" !

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Vm-dev December 2019