Vm-dev December 2016

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[OpenSmalltalk/opensmalltalk-vm] a67572: Don't try and trace the stack/code zone until the ...
by GitHub 08 Dec '16

08 Dec '16

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: a675723975e3a42aba3fbf7be43f62f5b7cd5792 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/a675723975e3a42aba… Author: Eliot Miranda <eliot.miranda(a)gmail.com> Date: 2016-12-07 (Wed, 07 Dec 2016) Changed paths: M platforms/iOS/vm/Common/Classes/sqSqueakMainApp.m M platforms/unix/vm/sqUnixMain.c M platforms/win32/vm/sqWin32Backtrace.c Log Message: ----------- Don't try and trace the stack/code zone until the interpreter (and by implication the Cogit) has been initialized. Doing so can cause breakonwarn to crash when an assert fails early in startup (i.e. PIC prototype generation).

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[OpenSmalltalk/opensmalltalk-vm] 400df4: update version of libpng because 1.2.49 does not c...
by GitHub 07 Dec '16

07 Dec '16

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 400df41fac120ed4c6abd82ca5d1da1619f00cbe https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/400df41fac120ed4c6… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-07 (Wed, 07 Dec 2016) Changed paths: M build.win32x86/third-party/pixman/Makefile.lib M third-party/libpng.spec Log Message: ----------- update version of libpng because 1.2.49 does not compiles on windows Commit: 91c7a21cdb1c9c509b2775d447811a308e5cfb97 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/91c7a21cdb1c9c509b… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-07 (Wed, 07 Dec 2016) Changed paths: M build.win32x86/third-party/libpng/Makefile.lib M third-party/libpng.spec A third-party/libpng.spec.win Log Message: ----------- split libpng to windows Commit: 695e2d67e1fc6aab9b0890746ab8f182ff75bc46 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/695e2d67e1fc6aab9b… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-07 (Wed, 07 Dec 2016) Changed paths: M build.win32x86/third-party/libpng/Makefile.lib M build.win32x86/third-party/pixman/Makefile.lib A third-party/libpng.spec.win Log Message: ----------- Merge pull request #106 from estebanlm/Cog use special spec for libpng on windows Compare: https://github.com/OpenSmalltalk/opensmalltalk-vm/compare/e3bc947d19a2...69…

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VM Maker: VMMaker.oscog-eem.2028.mcz
by commits＠source.squeak.org 07 Dec '16

07 Dec '16

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2028.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2028 Author: eem Time: 6 December 2016, 6:08:48.407545 pm UUID: a66fd6b5-4adb-4770-83b4-a29622cc4314 Ancestors: VMMaker.oscog-eem.2027 RegisterAllocatingCogit: No longer flush on conditional branch; instead leave it up to the merge logic to harmonise the stacks on join. Consequently, fix the order of generating fixups and pushing the dummyValue when no deadCode in genSpecialSelectorEqalsEquals:. This didn't matter with the StackToRegisterMappingCogit but in the RegisterAllocatingCogit now that teh stack is not flushed on conditional branch, it is critical; the fixup must be established before the dummyValue is pushed. Also consequently make mergeCurrentSimStackWith:/reconcileForwardsWith: more intelligent, able to merge when the target has spills and the current does not. At least mark that mustBeBoolean: will switch to an interpreted frame (yet to be implementd). Fix a slip in genSubConstant:R: which always used TempReg and didn't use its argument. Fix a slip in temp name printing for sim stack printing. Use = to compare objectmemory falseObject and objectMemory trueObject swith SSConstant entry constants. These are integeger oops, not objects, and so integral comparison shoudl be used. =============== Diff against VMMaker.oscog-eem.2027 =============== Item was added: + ----- Method: CoInterpreter>>ceSendMustBeBooleanInterpreting: (in category 'trampolines') ----- + ceSendMustBeBooleanInterpreting: anObject + "For RegisterAllocatingCogit we want the address following a conditional branch not to be reachable, so we + don't have to generate code to reload registers. Instead simply convert to an interpreter frame." + <api> + self shouldBeImplemented. + instructionPointer := self popStack. + self push: anObject. + self push: instructionPointer. + ^self + ceSendAbort: (objectMemory splObj: SelectorMustBeBoolean) + to: anObject + numArgs: 0! Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>reconcileForwardsWith: (in category 'compile abstract instructions') ----- reconcileForwardsWith: targetEntry "Make the state of the receiver, a stack entry at the end of a basic block, the same as the corresponding simStackEntry at the target of a preceding jump to the beginning of the next basic block. Make sure targetEntry reflects the state of the merged simStack; it will be installed as the current entry by restoreSimStackAtMergePoint: in mergeWithFixupIfRequired:. Answer if the liveRegister for the targetEntry (if any) should be deassigned; this is because if merging a non-temp with a temp that has a live register we can assign to the register, but must unassign the register from the temp, otherwise the temp will acquire the merged value without an assignment." <var: #targetEntry type: #'targetEntry *'> | targetReg | (targetReg := targetEntry registerOrNone) = NoReg ifTrue: + [| reg | + self assert: targetEntry spilled. + (self isSameEntryAs: targetEntry) ifTrue: + [self assert: spilled. + ^false]. + (reg := self registerOrNone) = NoReg ifTrue: [reg := TempReg]. + self storeToReg: reg. + spilled + ifTrue: [cogit MoveR: reg Mw: targetEntry offset r: targetEntry register] + ifFalse: [cogit PushR: reg]. - [self assert: (self isSameEntryAs: targetEntry). ^false]. liveRegister ~= NoReg ifTrue: [liveRegister ~= targetReg ifTrue: [cogit MoveR: liveRegister R: targetReg]. (spilled and: [targetEntry spilled not]) ifTrue: [cogit AddCq: objectRepresentation wordSize R: SPReg]. ^false]. spilled ifTrue: [targetEntry spilled ifFalse: [cogit PopR: targetReg. "KISS; generate the least number of instructions..." ^false]] ifFalse: [targetEntry spilled ifTrue: [cogit SubCq: objectRepresentation wordSize R: SPReg]]. type caseOf: { [SSBaseOffset] -> [cogit MoveMw: offset r: register R: targetReg]. [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg]. [SSConstant] -> [cogit genMoveConstant: constant R: targetReg]. [SSRegister] -> [register ~= targetReg ifTrue: [cogit MoveR: register R: targetReg]] }. (targetEntry type = SSConstant and: [type ~= SSConstant or: [constant ~= targetEntry constant]]) ifTrue: [targetEntry register: targetReg; type: SSRegister]. "If merging a non-temp with a temp that has a live register we can assign to the register, but must unassign the register from the temp, otherwise the temp will acquire the merged value without an assignment." ^targetEntry type = SSBaseOffset and: [targetEntry register = FPReg and: [(self isSameEntryAs: targetEntry) not]]! Item was added: + ----- Method: RegisterAllocatingCogit>>directionForMergeWith: (in category 'bytecode generator support') ----- + directionForMergeWith: mergeSimStack + "Answer > 0 if values must be pushed from simStack to merge with mergeSimStack, otherwise < 0 (the default)." + <var: #mergeSimStack type: #'SimStackEntry *'> + <inline: true> + simStackPtr to: methodOrBlockNumArgs by: -1 do: + [:i| + (self simStack: mergeSimStack at: i) spilled ifTrue: + [(self simStack: simStack at: i) spilled ifFalse: + [^1]]]. + ^-1! Item was changed: ----- Method: RegisterAllocatingCogit>>genForwardersInlinedIdenticalOrNotIf: (in category 'bytecode generators') ----- genForwardersInlinedIdenticalOrNotIf: orNot | nextPC branchDescriptor unforwardRcvr argReg targetBytecodePC unforwardArg rcvrReg postBranchPC label fixup | <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #label type: #'AbstractInstruction *'> self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. "If an operand is an annotable constant, it may be forwarded, so we need to store it into a register so the forwarder check can jump back to the comparison after unforwarding the constant. However, if one of the operand is an unnanotable constant, does not allocate a register for it (machine code will use operations on constants) and does not generate forwarder checks." unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. self allocateEqualsEqualsRegistersArgNeedsReg: unforwardArg rcvrNeedsReg: unforwardRcvr into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^ self genIdenticalNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg orNotIf: orNot]. label := self Label. self genCmpArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." (self fixupAt: nextPC - initialPC) notAFixup ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: + [self deny: deadCode]. "push dummy value below" - [self ssPushConstant: objectMemory trueObject]. "dummy value" self assert: (unforwardArg or: [unforwardRcvr]). "We could use (branchDescriptor isBranchTrue xor: orNot) to simplify this." orNot ifFalse: [branchDescriptor isBranchTrue ifTrue: [ fixup := (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger ] ifFalse: "branchDescriptor is branchFalse" [ fixup := (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger ]] ifTrue: [branchDescriptor isBranchTrue ifFalse: "branchDescriptor is branchFalse" [ fixup := (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger ] ifTrue: [ fixup := (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger ]]. + + deadCode ifFalse: + [self ssPushConstant: objectMemory trueObject]. "dummy value" - "The forwarders checks need to jump back to the comparison (label) if a forwarder is found, else jump forward either to the next forwarder check or to the postBranch or branch target (fixup)." unforwardArg ifTrue: [ unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] ifFalse: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ] ]. unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ]. "Not reached, execution flow have jumped to fixup" ^0! Item was added: + ----- Method: RegisterAllocatingCogit>>genJumpIf:to: (in category 'bytecode generator support') ----- + genJumpIf: boolean to: targetBytecodePC + <inline: false> + | desc reg fixup ok | + <var: #desc type: #'CogSimStackEntry *'> + <var: #fixup type: #'BytecodeFixup *'> + <var: #ok type: #'AbstractInstruction *'> + desc := self ssTop. + self ssPop: 1. + (desc type == SSConstant + and: [desc constant = objectMemory trueObject or: [desc constant = objectMemory falseObject]]) ifTrue: + ["Must arrange there's a fixup at the target whether it is jumped to or + not so that the simStackPtr can be kept correct." + fixup := self ensureFixupAt: targetBytecodePC - initialPC. + "Must annotate the bytecode for correct pc mapping." + self annotateBytecode: (desc constant = boolean + ifTrue: [self Jump: fixup] + ifFalse: [self prevInstIsPCAnnotated + ifTrue: [self Nop] + ifFalse: [self Label]]). + extA := 0. + ^0]. + "try and use the top entry's register if anty, but only if it can be destroyed." + reg := (desc type ~= SSRegister + or: [(self anyReferencesToRegister: desc register inAllButTopNItems: 0) + or: [(desc register = ReceiverResultReg and: [optStatus isReceiverResultRegLive])]]) + ifTrue: [TempReg] + ifFalse: [desc register]. + desc popToReg: reg. + "Cunning trick by LPD. If true and false are contiguous subtract the smaller. + Correct result is either 0 or the distance between them. If result is not 0 or + their distance send mustBeBoolean." + self assert: (objectMemory objectAfter: objectMemory falseObject) = objectMemory trueObject. + self genSubConstant: boolean R: reg. + self JumpZero: (self ensureFixupAt: targetBytecodePC - initialPC). + + self extASpecifiesNoMustBeBoolean ifTrue: + [extA := 0. + self annotateBytecode: self lastOpcode. + ^0]. + extA := 0. + + . self CmpCq: (boolean = objectMemory falseObject + ifTrue: [objectMemory trueObject - objectMemory falseObject] + ifFalse: [objectMemory falseObject - objectMemory trueObject]) + R: reg. + ok := self JumpZero: 0. + reg ~= TempReg ifTrue: + [self MoveR: reg R: TempReg]. + self copySimStackToScratch: simSpillBase. + self ssFlushTo: simStackPtr. + self CallRT: (boolean = objectMemory falseObject + ifTrue: [ceSendMustBeBooleanAddFalseTrampoline] + ifFalse: [ceSendMustBeBooleanAddTrueTrampoline]). + "NOTREACHED" + ok jmpTarget: (self annotateBytecode: self Label). + self restoreSimStackFromScratch. + ^0! Item was added: + ----- Method: RegisterAllocatingCogit>>genMustBeBooleanTrampolineFor:called: (in category 'initialization') ----- + genMustBeBooleanTrampolineFor: boolean called: trampolineName + <var: #trampolineName type: #'char *'> + "For RegisterAllocatingCogit we want the address following a conditional branch not to be reachable, so we + don't have to generate code to reload registers. Instead simply convert to an interpreter frame." + <inline: false> + self zeroOpcodeIndex. + "If the objectRepresentation does want true & false to be mobile then we need to record these addresses." + self assert: (objectRepresentation shouldAnnotateObjectReference: boolean) not. + self AddCq: boolean R: TempReg. + ^self genTrampolineFor: #ceSendMustBeBooleanInterpreting: + called: trampolineName + numArgs: 1 + arg: TempReg + arg: nil + arg: nil + arg: nil + regsToSave: self emptyRegisterMask + pushLinkReg: true + resultReg: NoReg + appendOpcodes: true! Item was added: + ----- Method: RegisterAllocatingCogit>>genVanillaInlinedIdenticalOrNotIf: (in category 'bytecode generators') ----- + genVanillaInlinedIdenticalOrNotIf: orNot + | nextPC postBranchPC targetBytecodePC branchDescriptor + rcvrReg argReg argIsConstant rcvrIsConstant | + <var: #branchDescriptor type: #'BytecodeDescriptor *'> + + self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | + branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. + + argIsConstant := self ssTop type = SSConstant. + "They can't be both constants to use correct machine opcodes. + However annotable constants can't be resolved statically, hence we need to careful." + rcvrIsConstant := argIsConstant not and: [(self ssValue: 1) type = SSConstant]. + + self + allocateEqualsEqualsRegistersArgNeedsReg: argIsConstant not + rcvrNeedsReg: rcvrIsConstant not + into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. + + "If not followed by a branch, resolve to true or false." + (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: + [^ self + genIdenticalNoBranchArgIsConstant: argIsConstant + rcvrIsConstant: rcvrIsConstant + argReg: argReg + rcvrReg: rcvrReg + orNotIf: orNot]. + + self genCmpArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg. + self ssPop: 2. + + "Further since there is a following conditional jump bytecode, define + non-merge fixups and leave the cond bytecode to set the mergeness." + (self fixupAt: nextPC - initialPC) notAFixup + ifTrue: "The next instruction is dead. we can skip it." + [deadCode := true. + self ensureFixupAt: targetBytecodePC - initialPC. + self ensureFixupAt: postBranchPC - initialPC] + ifFalse: + [self deny: deadCode]. "push dummy value below" + + "We could simplify this with a xor:" + self genConditionalBranch: (orNot + ifFalse: [branchDescriptor isBranchTrue ifTrue: [JumpZero] ifFalse: [JumpNonZero]] + ifTrue: [branchDescriptor isBranchTrue ifTrue: [JumpNonZero] ifFalse: [JumpZero]]) + operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. + + "If the branch is dead, then we can just fall through postBranchPC (only a nop in-between), else + we need to jump over the code of the branch" + deadCode ifFalse: + [self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). + self ssPushConstant: objectMemory trueObject]. "dummy value" + ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup <var: #fixup type: #'BytecodeFixup *'> + | mergeSimStack direction currentEntry targetEntry | - | mergeSimStack currentEntry targetEntry | <var: #mergeSimStack type: #'SimStackEntry *'> "At a merge point the cogit expects the stack to be in the same state as mergeSimStack. mergeSimStack is the state as of some jump forward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. The state of optStatus must agree." <var: #targetEntry type: #'SimStackEntry *'> <var: #currentEntry type: #'SimStackEntry *'> <var: #duplicateEntry type: #'SimStackEntry *'> (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. "Assignments amongst the registers must be made in order to avoid overwriting. If necessary exchange registers amongst simStack's entries to resolve any conflicts." self resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: mergeSimStack. self assert: (self conflcitsResolvedBetweenSimStackAnd: mergeSimStack). + "Must determine if we will push or pop values. + If pushing values must enumerate from bottom to top. + If popping, must enumerate from top to bottom." + direction := self directionForMergeWith: mergeSimStack. + direction > 0 + ifTrue: + [0 to: simStackPtr do: + [:i| + currentEntry := self simStack: simStack at: i. + targetEntry := self simStack: mergeSimStack at: i. + (currentEntry reconcileForwardsWith: targetEntry) ifTrue: + [self assert: i >= methodOrBlockNumArgs. + self deassignRegisterForTempVar: targetEntry in: mergeSimStack]. + "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: + spilled ifFalse: + [simSpillBase := i - 1]. + simStack + at: i + put: (self + cCode: [mergeSimStack at: i] + inSmalltalk: [(mergeSimStack at: i) copy])"]] + ifFalse: + [simStackPtr to: 0 by: -1 do: + [:i| + currentEntry := self simStack: simStack at: i. + targetEntry := self simStack: mergeSimStack at: i. + (currentEntry reconcileForwardsWith: targetEntry) ifTrue: + [self assert: i >= methodOrBlockNumArgs. + self deassignRegisterForTempVar: targetEntry in: mergeSimStack]. + "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: + spilled ifFalse: + [simSpillBase := i - 1]. + simStack + at: i + put: (self + cCode: [mergeSimStack at: i] + inSmalltalk: [(mergeSimStack at: i) copy])"]]. - simStackPtr to: 0 by: -1 do: - [:i| - currentEntry := self simStack: simStack at: i. - targetEntry := self simStack: mergeSimStack at: i. - (currentEntry reconcileForwardsWith: targetEntry) ifTrue: - [self assert: i >= methodOrBlockNumArgs. - self deassignRegisterForTempVar: targetEntry in: mergeSimStack]. - "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: - spilled ifFalse: - [simSpillBase := i - 1]. - simStack - at: i - put: (self - cCode: [mergeSimStack at: i] - inSmalltalk: [(mergeSimStack at: i) copy])"]. "a.k.a. fixup isReceiverResultRegSelf: (fixup isReceiverResultRegSelf and: [optStatus isReceiverResultRegLive])" optStatus isReceiverResultRegLive ifFalse: [fixup isReceiverResultRegSelf: false]! Item was added: + ----- Method: RegisterAllocatingCogit>>restoreSimStackFromScratch (in category 'bytecode generator support') ----- + restoreSimStackFromScratch + <inline: true> + self cCode: [self mem: simStack cp: scratchSimStack y: self simStackSlots * (self sizeof: CogSimStackEntry)] + inSmalltalk: [0 to: simStackPtr do: + [:i| + simStack at: i put: (scratchSimStack at: i)]]. + simSpillBase := scratchSpillBase. + optStatus := scratchOptStatus! Item was changed: ----- Method: SimpleStackBasedCogit>>genJumpIf:to: (in category 'bytecode generator support') ----- genJumpIf: boolean to: targetBytecodePC <inline: false> "Cunning trick by LPD. If true and false are contiguous subtract the smaller. Correct result is either 0 or the distance between them. If result is not 0 or their distance send mustBeBoolean." | ok | <var: #ok type: #'AbstractInstruction *'> extA := 0. self assert: (objectMemory objectAfter: objectMemory falseObject) = objectMemory trueObject. self PopR: TempReg. self genSubConstant: boolean R: TempReg. self JumpZero: (self ensureFixupAt: targetBytecodePC - initialPC). self CmpCq: (boolean == objectMemory falseObject ifTrue: [objectMemory trueObject - objectMemory falseObject] ifFalse: [objectMemory falseObject - objectMemory trueObject]) R: TempReg. ok := self JumpZero: 0. + self CallRT: (boolean = objectMemory falseObject - self CallRT: (boolean == objectMemory falseObject ifTrue: [ceSendMustBeBooleanAddFalseTrampoline] ifFalse: [ceSendMustBeBooleanAddTrueTrampoline]). ok jmpTarget: (self annotateBytecode: self Label). ^0! Item was changed: ----- Method: SimpleStackBasedCogit>>genSubConstant:R: (in category 'constant support') ----- genSubConstant: constant R: reg "If the objectMemory allows it, generates a quick constant sub, else generates a word constant sub" <inline: true> ^ (objectRepresentation shouldAnnotateObjectReference: constant) + ifTrue: [ self annotate: (self SubCw: constant R: reg) objRef: reg. ] + ifFalse: [ self SubCq: constant R: reg ]! - ifTrue: [ self annotate: (self SubCw: constant R: TempReg) objRef: reg. ] - ifFalse: [ self SubCq: constant R: TempReg ]! Item was changed: ----- Method: StackToRegisterMappingCogit>>genForwardersInlinedIdenticalOrNotIf: (in category 'bytecode generators') ----- genForwardersInlinedIdenticalOrNotIf: orNot | nextPC branchDescriptor unforwardRcvr argReg targetBytecodePC unforwardArg rcvrReg postBranchPC label fixup | <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #label type: #'AbstractInstruction *'> self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. "If an operand is an annotable constant, it may be forwarded, so we need to store it into a register so the forwarder check can jump back to the comparison after unforwarding the constant. However, if one of the operand is an unnanotable constant, does not allocate a register for it (machine code will use operations on constants) and does not generate forwarder checks." unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. self allocateEqualsEqualsRegistersArgNeedsReg: unforwardArg rcvrNeedsReg: unforwardRcvr into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^ self genIdenticalNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg orNotIf: orNot]. "If branching the stack must be flushed for the merge" self ssFlushTo: simStackPtr - 2. label := self Label. self genCmpArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." (self fixupAt: nextPC - initialPC) notAFixup ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: + [self deny: deadCode]. "push dummy value below" - [self ssPushConstant: objectMemory trueObject]. "dummy value" self assert: (unforwardArg or: [unforwardRcvr]). "We could use (branchDescriptor isBranchTrue xor: orNot) to simplify this." orNot ifFalse: [branchDescriptor isBranchTrue ifTrue: [ fixup := (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger ] ifFalse: "branchDescriptor is branchFalse" [ fixup := (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger ]] ifTrue: [branchDescriptor isBranchTrue ifFalse: "branchDescriptor is branchFalse" [ fixup := (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger ] ifTrue: [ fixup := (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger ]]. + + deadCode ifFalse: + [self ssPushConstant: objectMemory trueObject]. "dummy value" "The forwarders checks need to jump back to the comparison (label) if a forwarder is found, else jump forward either to the next forwarder check or to the postBranch or branch target (fixup)." unforwardArg ifTrue: [ unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] ifFalse: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ] ]. unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ]. "Not reached, execution flow have jumped to fixup" ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genJumpIf:to: (in category 'bytecode generator support') ----- genJumpIf: boolean to: targetBytecodePC <inline: false> | desc fixup ok | <var: #desc type: #'CogSimStackEntry *'> <var: #fixup type: #'BytecodeFixup *'> <var: #ok type: #'AbstractInstruction *'> self ssFlushTo: simStackPtr - 1. desc := self ssTop. self ssPop: 1. (desc type == SSConstant and: [desc constant = objectMemory trueObject or: [desc constant = objectMemory falseObject]]) ifTrue: ["Must arrange there's a fixup at the target whether it is jumped to or not so that the simStackPtr can be kept correct." fixup := self ensureFixupAt: targetBytecodePC - initialPC. "Must annotate the bytecode for correct pc mapping." self annotateBytecode: (desc constant = boolean ifTrue: [self Jump: fixup] ifFalse: [self prevInstIsPCAnnotated ifTrue: [self Nop] ifFalse: [self Label]]). extA := 0. ^0]. desc popToReg: TempReg. "Cunning trick by LPD. If true and false are contiguous subtract the smaller. Correct result is either 0 or the distance between them. If result is not 0 or their distance send mustBeBoolean." self assert: (objectMemory objectAfter: objectMemory falseObject) = objectMemory trueObject. self genSubConstant: boolean R: TempReg. self JumpZero: (self ensureFixupAt: targetBytecodePC - initialPC). self extASpecifiesNoMustBeBoolean ifTrue: [ extA := 0. self annotateBytecode: self lastOpcode. ^ 0]. extA := 0. + . self CmpCq: (boolean = objectMemory falseObject - . self CmpCq: (boolean == objectMemory falseObject ifTrue: [objectMemory trueObject - objectMemory falseObject] ifFalse: [objectMemory falseObject - objectMemory trueObject]) R: TempReg. ok := self JumpZero: 0. + self CallRT: (boolean = objectMemory falseObject - self CallRT: (boolean == objectMemory falseObject ifTrue: [ceSendMustBeBooleanAddFalseTrampoline] ifFalse: [ceSendMustBeBooleanAddTrueTrampoline]). ok jmpTarget: (self annotateBytecode: self Label). ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genVanillaInlinedIdenticalOrNotIf: (in category 'bytecode generators') ----- genVanillaInlinedIdenticalOrNotIf: orNot | nextPC postBranchPC targetBytecodePC branchDescriptor rcvrReg argReg argIsConstant rcvrIsConstant | <var: #branchDescriptor type: #'BytecodeDescriptor *'> self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. argIsConstant := self ssTop type = SSConstant. "They can't be both constants to use correct machine opcodes. However annotable constants can't be resolved statically, hence we need to careful." rcvrIsConstant := argIsConstant not and: [(self ssValue: 1) type = SSConstant]. self allocateEqualsEqualsRegistersArgNeedsReg: argIsConstant not rcvrNeedsReg: rcvrIsConstant not into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^ self genIdenticalNoBranchArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg orNotIf: orNot]. "If branching the stack must be flushed for the merge" self ssFlushTo: simStackPtr - 2. self genCmpArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." (self fixupAt: nextPC - initialPC) notAFixup ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: + [self deny: deadCode]. "push dummy value below" - [self ssPushConstant: objectMemory trueObject]. "dummy value" "We could simplify this with a xor:" self genConditionalBranch: (orNot ifFalse: [branchDescriptor isBranchTrue ifTrue: [JumpZero] ifFalse: [JumpNonZero]] ifTrue: [branchDescriptor isBranchTrue ifTrue: [JumpNonZero] ifFalse: [JumpZero]]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. "If the branch is dead, then we can just fall through postBranchPC (only a nop in-between), else we need to jump over the code of the branch" + deadCode ifFalse: + [self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). + self ssPushConstant: objectMemory trueObject]. "dummy value" - deadCode ifFalse: [self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC)]. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>printSimStack:toDepth:spillBase:on: (in category 'simulation only') ----- printSimStack: aSimStack toDepth: limit spillBase: spillBase on: aStream <doNotGenerate> | tempNamesOrNil width tabWidth | aStream ensureCr. limit < 0 ifTrue: [^aStream nextPutAll: 'simStackEmpty'; cr; flush]. inBlock ~~ true ifTrue: [(tempNamesOrNil := self class initializationOptions at: #tempNames ifAbsent: [#()]) isEmpty ifFalse: [| tab longest | longest := tempNamesOrNil inject: '' into: [:m :t| m size >= t size ifTrue: [m] ifFalse: [t]]. tabWidth := self widthInDefaultFontOf: (tab := String with: Character tab). width := self widthInDefaultFontOf: longest, tab. width <= ((self widthInDefaultFontOf: longest, (String with: Character space)) + 4) ifTrue: [width := width + tabWidth]]]. 0 to: limit do: [:i| + width ifNotNil: - tempNamesOrNil ifNotNil: [self put: (tempNamesOrNil at: i + 1 ifAbsent: ['']) paddedTo: width tabWidth: tabWidth on: aStream]. aStream print: i. i = spillBase ifTrue: [aStream nextPutAll: ' sb'; tab] ifFalse: [aStream tab; tab]. (aSimStack at: i) printStateOn: aStream. aStream cr; flush]!

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VM Maker: VMMaker.oscog-eem.2027.mcz
by commits＠source.squeak.org 06 Dec '16

06 Dec '16

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2027.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2027 Author: eem Time: 6 December 2016, 1:44:30.689018 pm UUID: e23772e4-15c7-4549-aab8-b4d28043c460 Ancestors: VMMaker.oscog-eem.2026 Add temp names to simStack printing during in-image compilation. =============== Diff against VMMaker.oscog-eem.2026 =============== Item was changed: ----- Method: Cogit class>>cog:selectorOrNumCopied:options: (in category 'in-image compilation') ----- cog: aCompiledMethod selectorOrNumCopied: selectorOrNumCopied options: optionsDictionaryOrArray "StackToRegisterMappingCogit cog: (Integer >> #benchFib) selector: #benchFib options: #(COGMTVM false)" | cogit coInterpreter | cogit := self instanceForTests: optionsDictionaryOrArray. + (aCompiledMethod respondsTo: #tempNames) ifTrue: + [initializationOptions at: #tempNames put: aCompiledMethod tempNames]. coInterpreter := CurrentImageCoInterpreterFacade forCogit: cogit. [cogit setInterpreter: coInterpreter; singleStep: true; initializeCodeZoneFrom: 1024 upTo: coInterpreter memory size / 2. "leave space for rump C stack" cogit methodZone freeStart: (cogit methodZone freeStart roundUpTo: 1024)] on: Notification do: [:ex| (ex messageText beginsWith: 'cannot find receiver for') ifTrue: [ex resume: coInterpreter]. ex pass]. ^{ coInterpreter. cogit. selectorOrNumCopied isInteger ifTrue: [ cogit cogFullBlockMethod: (coInterpreter oopForObject: aCompiledMethod) numCopied: selectorOrNumCopied ] ifFalse: [ cogit cog: (coInterpreter oopForObject: aCompiledMethod) selector: (coInterpreter oopForObject: selectorOrNumCopied) ] }! Item was changed: ----- Method: StackToRegisterMappingCogit>>printSimStack:toDepth:spillBase:on: (in category 'simulation only') ----- printSimStack: aSimStack toDepth: limit spillBase: spillBase on: aStream <doNotGenerate> + | tempNamesOrNil width tabWidth | aStream ensureCr. limit < 0 ifTrue: [^aStream nextPutAll: 'simStackEmpty'; cr; flush]. + inBlock ~~ true ifTrue: + [(tempNamesOrNil := self class initializationOptions at: #tempNames ifAbsent: [#()]) isEmpty ifFalse: + [| tab longest | + longest := tempNamesOrNil inject: '' into: [:m :t| m size >= t size ifTrue: [m] ifFalse: [t]]. + tabWidth := self widthInDefaultFontOf: (tab := String with: Character tab). + width := self widthInDefaultFontOf: longest, tab. + width <= ((self widthInDefaultFontOf: longest, (String with: Character space)) + 4) ifTrue: + [width := width + tabWidth]]]. 0 to: limit do: [:i| + tempNamesOrNil ifNotNil: + [self put: (tempNamesOrNil at: i + 1 ifAbsent: ['']) paddedTo: width tabWidth: tabWidth on: aStream]. aStream print: i. i = spillBase ifTrue: [aStream nextPutAll: ' sb'; tab] ifFalse: [aStream tab; tab]. (aSimStack at: i) printStateOn: aStream. aStream cr; flush]! Item was added: + ----- Method: StackToRegisterMappingCogit>>put:paddedTo:tabWidth:on: (in category 'simulation only') ----- + put: aString paddedTo: compositionWidth tabWidth: tabWidth on: aStream + <doNotGenerate> + | fittedString size width | + fittedString := aString. + size := fittedString size. + [(width := self widthInDefaultFontOf: fittedString) > compositionWidth] whileTrue: + [size := size - 2. + fittedString := aString contractTo: size]. + aStream + nextPutAll: fittedString; + tab: compositionWidth - width + (width \\ tabWidth) // tabWidth! Item was added: + ----- Method: StackToRegisterMappingCogit>>widthInDefaultFontOf: (in category 'simulation only') ----- + widthInDefaultFontOf: aString + <doNotGenerate> + ^(NewParagraph new + compose: aString asText + style: TextStyle default + from: 1 + in: Display boundingBox; + adjustRightX) + extent x!

1 0

running squeak from network
by Vaidotas Didžbalis 06 Dec '16

06 Dec '16

Hello, Can Squeak.exe be run from network drive, what are requirements for it to run form it? I have limited information about environment it is crashing, cannot get log file yet, but it does crash for our user after 10 seconds or so. Maybe the location is read only. VM is COG VM Apr 16 2015 Image version is 4.4 Message box displayed during crash event is attached. Thank you thank you, Vaidotas

1 1

VM Maker: VMMaker.oscog-eem.2026.mcz
by commits＠source.squeak.org 06 Dec '16

06 Dec '16

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2026.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2026 Author: eem Time: 6 December 2016, 11:07:43.390182 am UUID: e24cd05c-d1c9-490c-8994-b0cf94152a18 Ancestors: VMMaker.oscog-eem.2025 RegisterAllocatingCogit: 3+4=7 :-) genSpecialSelectorComparison must create merge fixups at the targets (fall-through after the following branch and jump destination) for register assignments to be carried forwards. Doing so eliminates the merge conflicts seen in SequenceableCollection>>#findBinaryIndex:do:ifNone: and so means that, for now, the code in resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: is not used. Make sure that ensureNonMergeFixupAt: reciords bytecodePC for debugging. Hack implement swapCurrentRegistersInMask:accordingToRegisterOrderIn: for the trivial two-registers-in-conflict case. =============== Diff against VMMaker.oscog-eem.2025 =============== Item was changed: ----- Method: RegisterAllocatingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor rcvrIsInt argIsInt argInt jumpNotSmallInts inlineCAB index rcvrReg argReg regMask | <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> primDescriptor := self generatorAt: byte0. argIsInt := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := (self ssValue: 1) type = SSConstant and: [objectMemory isIntegerObject: (self ssValue: 1) constant]. (argIsInt and: [rcvrIsInt]) ifTrue: [^ self genStaticallyResolvedSpecialSelectorComparison]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsInt or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. "In-line the comparison and the jump, but if the types are not SmallInteger then we will need to do a send and fall through to the following conditional branch. Since we're allocating values in registers we would like to keep those registers live on the inlined path and reload registers along the non-inlined send path. The merge logic at the branch destinations handles this." argIsInt ifTrue: [rcvrReg := self allocateRegForStackEntryAt: 1. (self ssValue: 1) popToReg: rcvrReg. self MoveR: rcvrReg R: TempReg. regMask := self registerMaskFor: rcvrReg] ifFalse: [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. rcvrReg = Arg0Reg ifTrue: [rcvrReg := argReg. argReg := Arg0Reg]. self ssTop popToReg: argReg. (self ssValue: 1) popToReg: rcvrReg. self MoveR: argReg R: TempReg. regMask := self registerMaskFor: rcvrReg and: argReg]. self ssPop: 2. jumpNotSmallInts := (argIsInt or: [rcvrIsInt]) ifTrue: [objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: rcvrReg andScratch: TempReg scratch: ClassReg]. argIsInt ifTrue: [self CmpCq: argInt R: rcvrReg] ifFalse: [self CmpR: argReg R: rcvrReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) + operand: (self ensureFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. + self Jump: (self ensureFixupAt: postBranchPC - initialPC). - operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. - self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). jumpNotSmallInts jmpTarget: self Label. self ssFlushTo: simStackPtr. self deny: rcvrReg = Arg0Reg. argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg] ifFalse: [argReg ~= Arg0Reg ifTrue: [self MoveR: argReg R: Arg0Reg]]. rcvrReg ~= ReceiverResultReg ifTrue: [self MoveR: rcvrReg R: ReceiverResultReg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: (in category 'bytecode generator support') ----- resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: mergeSimStack <var: #mergeSimStack type: #'SimStackEntry *'> "One simple algorithm is to spill everything if there are any conflicts and then pop back. But this is terrible :-( Can we do better? Yes... Consider the following two simStacks target: 0: | rA | __ | rB | rC | rD | <- sp current: 0: | __ | __ | rD | rA | rC | <- sp If we were to assign in a naive order, 0 through sp rA would be overwritten before its value in current[3] is written to rC, and rC would be overwritten before its value in current[4] is written to rD. But if we swap the registers in current so that they respect the reverse ordering in target we can assign directly: swap current[3] & current[4] 0: | __ | __ | rD | rC | rA | <- sp now do the assignment in the order target[0] := current[0], target[1] := current[1], ... target[4] := current[4], i.e. rA := current[0]; rB := rD; (rC := rC); (rD := rD). So find any conflicts, and if there are any, swap registers in the simStack to resolve them. + The trivial case of a single conflict is resolved by assigning that conflict to TempReg." - The trivial case of a single conflict is resolved by assigning that conflict to TempReg. - " | currentRegsMask mergeRegsMask potentialConflictRegMask conflictingRegsMask currentRegMask mergeRegMask currentEntry targetEntry | <var: #currentEntry type: #'SimStackEntry *'> <var: #targetEntry type: #'SimStackEntry *'> currentRegsMask := mergeRegsMask := potentialConflictRegMask := 0. 0 to: simStackPtr do: [:i| currentRegMask := (currentEntry := self simStack: simStack at: i) registerMaskOrNone. mergeRegMask := (targetEntry := self simStack: mergeSimStack at: i) registerMaskOrNone. (currentRegMask ~= mergeRegMask and: [currentRegMask ~= 0 or: [mergeRegMask ~= 0]]) ifTrue: [potentialConflictRegMask := potentialConflictRegMask bitOr: (currentRegMask bitOr: mergeRegMask)]. currentRegsMask := currentRegsMask bitOr: currentRegMask. mergeRegsMask := mergeRegsMask bitOr: mergeRegMask]. conflictingRegsMask := potentialConflictRegMask bitAnd: (currentRegsMask bitAnd: mergeRegsMask). conflictingRegsMask ~= 0 ifTrue: [(self isAPowerOfTwo: conflictingRegsMask) "Multiple conflicts mean we have to sort" + ifFalse: [self swapCurrentRegistersInMask: conflictingRegsMask accordingToRegisterOrderIn: mergeSimStack] - ifFalse: [self swapCurrentRegistersInMask: currentRegsMask accordingToRegisterOrderIn: mergeSimStack] ifTrue: [self assignToTempRegConflictingRegisterIn: conflictingRegsMask]].! Item was added: + ----- Method: RegisterAllocatingCogit>>swapCurrentRegistersInMask:accordingToRegisterOrderIn: (in category 'bytecode generator support') ----- + swapCurrentRegistersInMask: conflictingRegsMask accordingToRegisterOrderIn: mergeSimStack + <var: #mergeSimStack type: #'SimStackEntry *'> + "Swap liveRegisters in simStack entries according to their order in mergeSimStack so as to avoid + overwriting live registers when merging simStack into mergeSimStack. Consider the following two simStacks + target: 0: | rA | __ | rB | rC | rD | <- sp + current: 0: | __ | __ | rD | rA | rC | <- sp + If we were to assign in a naive order, 0 through sp rA would be overwritten before its value in current[3] is written to rC, + and rC would be overwritten before its value in current[4] is written to rD. But if we swap the registers in current so that + they respect the reverse ordering in target we can assign directly: + swap current[3] & current[4] + 0: | __ | __ | rD | rC | rA | <- sp + now do the assignment in the order target[0] := current[0], target[1] := current[1], ... target[4] := current[4], + i.e. rA := current[0]; rB := rD; (rC := rC); (rD := rD). + + See https://hal.inria.fr/inria-00435844/file/article-hal.pdf + Florent Bouchez, Quentin Colombet, Alain Darte, Christophe Guillon, Fabrice Rastello. + Parallel Copy Motion. SCOPES, ACM, 2010, pp.0. <inria-00435844> + + So find any conflicts, and if there are any, swap registers in the simStack to resolve them." + + "self printSimStack; printSimStack: mergeSimStack" + + "Some processors have a SwapRR but not all. Write one-size-fits-all code that moves things through TempReg." + | order n visitedMask ssEntry regA regB | + <var: 'order' declareC: 'sqInt order[8*BytesPerWord]'> + <var: 'ssEntry' type: #'SimStackEntry *'> + self cCode: [self me: order ms: 0 et: (self sizeof: order)] + inSmalltalk: [order := CArrayAccessor on: (Array new: 8*BytesPerWord withAll: 0)]. + n := 0. + visitedMask := conflictingRegsMask. + 0 to: methodOrBlockNumTemps - 1 do: + [:i| + ssEntry := self simStack: mergeSimStack at: i. + (ssEntry registerMaskOrNone anyMask: visitedMask) ifTrue: + [order at: ssEntry registerOrNone put: (n := n + 1). + visitedMask := visitedMask - ssEntry registerMaskOrNone]]. + self assert: n > 1. + n = 2 ifTrue: "simple case; here to show me what I have to do in addition to the sort" + [regA := conflictingRegsMask highBit - 1. + regB := (conflictingRegsMask - (1 << regA)) highBit - 1. + self MoveR: regA R: TempReg. + self MoveR: regB R: regA. + self MoveR: TempReg R: regB. + 0 to: simStackPtr do: + [:i| + ssEntry := self simStackAt: i. + (ssEntry registerMaskOrNone anyMask: conflictingRegsMask) ifTrue: + [| reg | + reg := ssEntry registerOrNone = regA ifTrue: [regB] ifFalse: [regA]. + ssEntry type = SSRegister ifTrue: + [ssEntry register: reg]. + ssEntry liveRegister: reg]]. + ^self]. + + self halt! Item was changed: ----- Method: StackToRegisterMappingCogit>>ensureNonMergeFixupAt: (in category 'compile abstract instructions') ----- ensureNonMergeFixupAt: targetIndex "Make sure there's a flagged fixup at the targetIndex (pc relative to first pc) in fixups. Initially a fixup's target is just a flag. Later on it is replaced with a proper instruction." <returnTypeC: #'BytecodeFixup *'> | fixup | <var: #fixup type: #'BytecodeFixup *'> fixup := self fixupAt: targetIndex. fixup notAFixup ifTrue: [fixup becomeNonMergeFixup]. self cCode: '' inSmalltalk: [fixup isMergeFixupOrIsFixedUp ifTrue: [self assert: (fixup isBackwardBranchFixup or: [fixup simStackPtr = (self debugStackPointerFor: targetIndex + initialPC)])]]. + fixup recordBcpc: bytecodePC. ^fixup!

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[OpenSmalltalk/opensmalltalk-vm] 5a7ee7: Merge commit '21b488e00c991284c8e81835f377107dafd7...
by GitHub 05 Dec '16

05 Dec '16

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 5a7ee7b5b24fbdb58e74a122e7d23c52ed4262ad https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/5a7ee7b5b24fbdb58e… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-11-29 (Tue, 29 Nov 2016) Changed paths: M build.linux32ARMv6/newspeak.cog.spur/plugins.ext M build.linux32ARMv6/newspeak.stack.spur/plugins.ext M build.linux32x86/newspeak.cog.spur/plugins.ext M build.linux32x86/newspeak.sista.spur/plugins.ext M build.linux32x86/newspeak.stack.spur/plugins.ext M build.linux32x86/nsnac.cog.spur/plugins.ext M build.linux64x64/newspeak.cog.spur/plugins.ext M build.linux64x64/newspeak.sista.spur/plugins.ext M build.linux64x64/newspeak.stack.spur/plugins.ext M build.linux64x64/nsnac.cog.spur/plugins.ext Log Message: ----------- Merge commit '21b488e00c991284c8e81835f377107dafd77233' # Conflicts: # opensmalltalk-vm/build.linux32ARMv6/newspeak.cog.spur/plugins.ext # opensmalltalk-vm/build.linux32ARMv6/newspeak.stack.spur/plugins.ext # opensmalltalk-vm/build.linux32x86/newspeak.cog.spur/plugins.ext # opensmalltalk-vm/build.linux32x86/newspeak.sista.spur/plugins.ext # opensmalltalk-vm/build.linux32x86/newspeak.stack.spur/plugins.ext # opensmalltalk-vm/build.linux32x86/nsnac.cog.spur/plugins.ext # opensmalltalk-vm/build.linux64x64/newspeak.cog.spur/plugins.ext # opensmalltalk-vm/build.linux64x64/newspeak.sista.spur/plugins.ext # opensmalltalk-vm/build.linux64x64/newspeak.stack.spur/plugins.ext # opensmalltalk-vm/build.linux64x64/nsnac.cog.spur/plugins.ext Commit: 6c9cbfb2023af6841957d12f12e602191d9cfd80 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/6c9cbfb2023af68419… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-11-29 (Tue, 29 Nov 2016) Changed paths: M build.win32x86/common/Makefile.plugin M build.win32x86/pharo.cog.spur/Makefile Log Message: ----------- adding STACK_ALIGN_BYTES=16, ALLOCA_LIES_SO_USE_GETSP=0 flags to win32 builds. ensuriung plugins also uses COGDEFS variable Commit: ef56de7559606c116ee92076b75569ff8c332aa0 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/ef56de7559606c116e… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-01 (Thu, 01 Dec 2016) Changed paths: M platforms/Cross/vm/sqCogStackAlignment.h Log Message: ----------- Merge commit '386330591639b3056ae67586530f7a6d9dcea87d' Commit: 9097bc29aaabc679aae92cad3a59969ecd34f864 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/9097bc29aaabc679aa… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-01 (Thu, 01 Dec 2016) Changed paths: M build.macos32x86/third-party/libgit2/Makefile.lib Log Message: ----------- mac: add support for openssl in libgit2 Commit: 9bc2954529e3d8dc23466a0f3291f1ecb76653fb https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/9bc2954529e3d8dc23… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-02 (Fri, 02 Dec 2016) Changed paths: A third-party/cairo.spec A third-party/example.spec A third-party/freetype2.spec A third-party/libgit2.spec A third-party/libpng.spec A third-party/libsdl2.spec A third-party/libssh2.spec A third-party/openssl.spec A third-party/pixman.spec A third-party/pkgconfig.spec Log Message: ----------- add third-party specs (version definitons) Commit: 2e1d08e47ebbca614c35547f31ecc127ff5b8381 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/2e1d08e47ebbca614c… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-02 (Fri, 02 Dec 2016) Changed paths: M build.macos32x86/third-party/cairo/Makefile.lib M build.macos32x86/third-party/freetype2/Makefile.lib M build.macos32x86/third-party/libgit2/Makefile.lib M build.macos32x86/third-party/libpng/Makefile.lib M build.macos32x86/third-party/libsdl2/Makefile.lib M build.macos32x86/third-party/libssh2/Makefile.lib M build.macos32x86/third-party/openssl/Makefile.lib M build.macos32x86/third-party/pixman/Makefile.lib M build.macos32x86/third-party/pkgconfig/Makefile.lib Log Message: ----------- mac32 third-party using specs Commit: 7fc17861cef9a4015aec02262b242d03002707c1 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/7fc17861cef9a4015a… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-02 (Fri, 02 Dec 2016) Changed paths: M build.macos32x86/third-party/cairo/Makefile.lib M build.macos32x86/third-party/freetype2/Makefile.lib M build.macos32x86/third-party/libgit2/Makefile.lib M build.macos32x86/third-party/libpng/Makefile.lib M build.macos32x86/third-party/libsdl2/Makefile.lib M build.macos32x86/third-party/libssh2/Makefile.lib M build.macos32x86/third-party/openssl/Makefile.lib M build.macos32x86/third-party/pixman/Makefile.lib M build.macos32x86/third-party/pkgconfig/Makefile.lib Log Message: ----------- added condition to avoid warnings Commit: acd5916f729703162e0aef4cb12ccc2cce114876 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/acd5916f729703162e… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-02 (Fri, 02 Dec 2016) Changed paths: M build.macos64x64/common/Makefile.app M build.macos64x64/common/Makefile.lib.extra M build.macos64x64/common/Makefile.vm M build.macos64x64/pharo.cog.spur/Makefile M build.macos64x64/pharo.cog.spur/plugins.int M build.macos64x64/third-party/cairo/Makefile.lib M build.macos64x64/third-party/freetype2/Makefile.lib M build.macos64x64/third-party/libgit2/Makefile.lib M build.macos64x64/third-party/libpng/Makefile.lib M build.macos64x64/third-party/libsdl2/Makefile.lib M build.macos64x64/third-party/libssh2/Makefile.lib M build.macos64x64/third-party/openssl/Makefile.lib M build.macos64x64/third-party/pixman/Makefile.lib M build.macos64x64/third-party/pkgconfig/Makefile.lib Log Message: ----------- using spec versions for third-party libraries on mac 64bits Commit: de333792d954672182f6fafdb020ffd06cbc7ad5 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/de333792d954672182… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-02 (Fri, 02 Dec 2016) Changed paths: M build.linux32x86/third-party/libgit2/Makefile.lib M build.linux32x86/third-party/libsdl2/Makefile.lib M build.linux32x86/third-party/libssh2/Makefile.lib M build.linux32x86/third-party/pkgconfig/Makefile.lib M third-party/libgit2.spec M third-party/libsdl2.spec M third-party/libssh2.spec Log Message: ----------- linux32 third-party using specs Commit: 6bad1379de7ff64bc5f9fdcba5e5e592a27457ab https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/6bad1379de7ff64bc5… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-02 (Fri, 02 Dec 2016) Changed paths: M build.linux32ARMv6/third-party/libgit2/Makefile.lib M build.linux32ARMv6/third-party/libsdl2/Makefile.lib M build.linux32ARMv6/third-party/libssh2/Makefile.lib Log Message: ----------- linux32 ARMv6 third-party using specs Commit: 057b42b018f5818c04e888747b7c752c5510193f https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/057b42b018f5818c04… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-02 (Fri, 02 Dec 2016) Changed paths: M build.linux64x64/third-party/libgit2/Makefile.lib M build.linux64x64/third-party/libsdl2/Makefile.lib M build.linux64x64/third-party/libssh2/Makefile.lib Log Message: ----------- linux64 third-party using specs Commit: c6a0317a13811049e8fb98908fee0fcc5845ff66 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/c6a0317a13811049e8… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-02 (Fri, 02 Dec 2016) Changed paths: M build.win32x86/third-party/cairo/Makefile.lib M build.win32x86/third-party/freetype2/Makefile.lib M build.win32x86/third-party/libgit2/Makefile.lib M build.win32x86/third-party/libpng/Makefile.lib M build.win32x86/third-party/libsdl2/Makefile.lib M build.win32x86/third-party/libssh2/Makefile.lib M build.win32x86/third-party/openssl/Makefile.lib M build.win32x86/third-party/pixman/Makefile.lib M build.win32x86/third-party/pkgconfig/Makefile.lib M build.win32x86/third-party/zlib/Makefile.lib M third-party/cairo.spec M third-party/freetype2.spec M third-party/libgit2.spec M third-party/libpng.spec M third-party/libsdl2.spec M third-party/libssh2.spec M third-party/openssl.spec M third-party/pixman.spec M third-party/pkgconfig.spec A third-party/zlib.spec Log Message: ----------- win32 third-party using specs Commit: a3510c70b37730044f2a1f9b5a8c265749918c67 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/a3510c70b37730044f… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-05 (Mon, 05 Dec 2016) Changed paths: M .travis_test.sh M tests/smalltalkCI.sh Log Message: ----------- Merge commit 'bccc47a7622661b4e6218ac5ac924b8f0f9804ed' Commit: 43fd03a93c5760e3a3f5ace9476c8fb41c208328 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/43fd03a93c5760e3a3… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-05 (Mon, 05 Dec 2016) Changed paths: M third-party/pkgconfig.spec Log Message: ----------- using pkgconfig 0.23 because 0.29 is not working for mac (it looks glibc >= 2.6 and mac has 2.0) Commit: 91cd9cb8e77f0775d176cc268bb43768e116457b https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/91cd9cb8e77f0775d1… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-05 (Mon, 05 Dec 2016) Changed paths: M build.win32x86/third-party/pkgconfig/Makefile.lib A third-party/pkgconfig.spec.win Log Message: ----------- split spec for Windows because macOS and Windows have incompatible pkgconfig versions. Commit: afffa800d2362d0f952188b7dfa7979f140bf183 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/afffa800d2362d0f95… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-05 (Mon, 05 Dec 2016) Changed paths: M third-party/libpng.spec Log Message: ----------- using libpng 1.2.49 Commit: e3bc947d19a2f157cb8122396e293f5c2ba62a8f https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/e3bc947d19a2f157cb… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2016-12-05 (Mon, 05 Dec 2016) Changed paths: M build.linux32ARMv6/third-party/libgit2/Makefile.lib M build.linux32ARMv6/third-party/libsdl2/Makefile.lib M build.linux32ARMv6/third-party/libssh2/Makefile.lib M build.linux32x86/third-party/libgit2/Makefile.lib M build.linux32x86/third-party/libsdl2/Makefile.lib M build.linux32x86/third-party/libssh2/Makefile.lib M build.linux32x86/third-party/pkgconfig/Makefile.lib M build.linux64x64/third-party/libgit2/Makefile.lib M build.linux64x64/third-party/libsdl2/Makefile.lib M build.linux64x64/third-party/libssh2/Makefile.lib M build.macos32x86/third-party/cairo/Makefile.lib M build.macos32x86/third-party/freetype2/Makefile.lib M build.macos32x86/third-party/libgit2/Makefile.lib M build.macos32x86/third-party/libpng/Makefile.lib M build.macos32x86/third-party/libsdl2/Makefile.lib M build.macos32x86/third-party/libssh2/Makefile.lib M build.macos32x86/third-party/openssl/Makefile.lib M build.macos32x86/third-party/pixman/Makefile.lib M build.macos32x86/third-party/pkgconfig/Makefile.lib M build.macos64x64/common/Makefile.app M build.macos64x64/common/Makefile.lib.extra M build.macos64x64/common/Makefile.vm M build.macos64x64/pharo.cog.spur/Makefile M build.macos64x64/pharo.cog.spur/plugins.int M build.macos64x64/third-party/cairo/Makefile.lib M build.macos64x64/third-party/freetype2/Makefile.lib M build.macos64x64/third-party/libgit2/Makefile.lib M build.macos64x64/third-party/libpng/Makefile.lib M build.macos64x64/third-party/libsdl2/Makefile.lib M build.macos64x64/third-party/libssh2/Makefile.lib M build.macos64x64/third-party/openssl/Makefile.lib M build.macos64x64/third-party/pixman/Makefile.lib M build.macos64x64/third-party/pkgconfig/Makefile.lib M build.win32x86/common/Makefile.plugin M build.win32x86/pharo.cog.spur/Makefile M build.win32x86/third-party/cairo/Makefile.lib M build.win32x86/third-party/freetype2/Makefile.lib M build.win32x86/third-party/libgit2/Makefile.lib M build.win32x86/third-party/libpng/Makefile.lib M build.win32x86/third-party/libsdl2/Makefile.lib M build.win32x86/third-party/libssh2/Makefile.lib M build.win32x86/third-party/openssl/Makefile.lib M build.win32x86/third-party/pixman/Makefile.lib M build.win32x86/third-party/pkgconfig/Makefile.lib M build.win32x86/third-party/zlib/Makefile.lib A third-party/cairo.spec A third-party/example.spec A third-party/freetype2.spec A third-party/libgit2.spec A third-party/libpng.spec A third-party/libsdl2.spec A third-party/libssh2.spec A third-party/openssl.spec A third-party/pixman.spec A third-party/pkgconfig.spec A third-party/pkgconfig.spec.win A third-party/zlib.spec Log Message: ----------- Merge pull request #105 from estebanlm/Cog fix PharoVM-win32 build + enhancements Compare: https://github.com/OpenSmalltalk/opensmalltalk-vm/compare/bccc47a76226...e3…

1 0

VM Maker: VMMaker.oscog-eem.2025.mcz
by commits＠source.squeak.org 05 Dec '16

05 Dec '16

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2025.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2025 Author: eem Time: 5 December 2016, 11:37:37.687804 am UUID: fabd1a90-44f2-4c24-a717-0ddf8f524bdb Ancestors: VMMaker.oscog-EstebanLorenzano.2024 RegisterAllocatingCogit: Clean up reconcilePoppingWith: Fix bug with merging results into temp vars with live regs. If merging a non-temp with a temp that has a live register we can assign to the register, but must unassign the register from the temp, otherwise the temp will acquire the merged value without an assignment. Fix bug with allocateRegForStackEntryAt:; use the register of the entry if it has one. Nuke captureUnspilledSpillsForSpecialSelectorSend:. With the recent changes to merge logic this is no longer necessary. Fix bugs with genSpecialSelectorArithmetic. Assign a new register for the result unless rcvr is otherwise unused register or constant; do /not/ overwrite rcvrReg (which could be a temp). If rcvr or arg are live ensure they're restored correctly after tag removal or overflow during arithmetic. Improve printing of cogMethods with nil selectors. Execution now gets much further; up to the compilation of findBinaryIndex:do:ifNone: in the context of restoring the display. This method requires swapCurrentRegistersInMask:accordingToRegisterOrderIn: to be implemented. Clément, please review especially genSpecialSelectorArithmetic carefully. Thanks! =============== Diff against VMMaker.oscog-EstebanLorenzano.2024 =============== Item was changed: ----- Method: CoInterpreter>>printCogMethod: (in category 'debug printing') ----- printCogMethod: cogMethod <api> <var: #cogMethod type: #'CogMethod *'> | address primitive | self cCode: '' inSmalltalk: [self transcript ensureCr. cogMethod isInteger ifTrue: [^self printCogMethod: (self cCoerceSimple: cogMethod to: #'CogMethod *')]]. address := cogMethod asInteger. self printHex: address; print: ' <-> '; printHex: address + cogMethod blockSize. cogMethod cmType = CMMethod ifTrue: [self print: ': method: '; printHex: cogMethod methodObject. primitive := self primitiveIndexOfMethod: cogMethod methodObject header: cogMethod methodHeader. primitive ~= 0 ifTrue: [self print: ' prim '; printNum: primitive]]. cogMethod cmType = CMBlock ifTrue: [self print: ': block home: '; printHex: (self cCoerceSimple: cogMethod to: #'CogBlockMethod *') cmHomeMethod asUnsignedInteger]. cogMethod cmType = CMClosedPIC ifTrue: [self print: ': Closed PIC N: '; printHex: cogMethod cPICNumCases]. cogMethod cmType = CMOpenPIC ifTrue: [self print: ': Open PIC ']. self print: ' selector: '; printHex: cogMethod selector. cogMethod selector = objectMemory nilObject + ifTrue: [| s | + (cogMethod cmType = CMMethod + and: [(s := self maybeSelectorOfMethod: cogMethod methodObject) notNil]) + ifTrue: [self print: ' (nil: '; printStringOf: s; print: ')'] + ifFalse: [self print: ' (nil)']] - ifTrue: [self print: ' (nil)'] ifFalse: [self space; printStringOf: cogMethod selector]. self cr! Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>reconcileForwardsWith: (in category 'compile abstract instructions') ----- reconcileForwardsWith: targetEntry "Make the state of the receiver, a stack entry at the end of a basic block, the same as the corresponding simStackEntry at the target of a preceding jump to the beginning of the next basic block. Make sure targetEntry reflects the state of the merged simStack; it will be installed as the current + entry by restoreSimStackAtMergePoint: in mergeWithFixupIfRequired:. + + Answer if the liveRegister for the targetEntry (if any) should be deassigned; + this is because if merging a non-temp with a temp that has a live register we + can assign to the register, but must unassign the register from the temp, + otherwise the temp will acquire the merged value without an assignment." - entry by restoreSimStackAtMergePoint: in mergeWithFixupIfRequired:." <var: #targetEntry type: #'targetEntry *'> | targetReg | (targetReg := targetEntry registerOrNone) = NoReg ifTrue: [self assert: (self isSameEntryAs: targetEntry). + ^false]. - ^self]. liveRegister ~= NoReg ifTrue: [liveRegister ~= targetReg ifTrue: [cogit MoveR: liveRegister R: targetReg]. (spilled and: [targetEntry spilled not]) ifTrue: [cogit AddCq: objectRepresentation wordSize R: SPReg]. + ^false]. - ^self]. spilled ifTrue: [targetEntry spilled ifFalse: [cogit PopR: targetReg. "KISS; generate the least number of instructions..." + ^false]] - ^self]] ifFalse: + [targetEntry spilled ifTrue: + [cogit SubCq: objectRepresentation wordSize R: SPReg]]. - [self deny: targetEntry spilled]. type caseOf: { [SSBaseOffset] -> [cogit MoveMw: offset r: register R: targetReg]. [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg]. [SSConstant] -> [cogit genMoveConstant: constant R: targetReg]. [SSRegister] -> [register ~= targetReg ifTrue: [cogit MoveR: register R: targetReg]] }. (targetEntry type = SSConstant and: [type ~= SSConstant or: [constant ~= targetEntry constant]]) ifTrue: [targetEntry register: targetReg; + type: SSRegister]. + "If merging a non-temp with a temp that has a live register we can assign + to the register, but must unassign the register from the temp, otherwise + the temp will acquire the merged value without an assignment." + ^targetEntry type = SSBaseOffset + and: [targetEntry register = FPReg + and: [(self isSameEntryAs: targetEntry) not]]! - type: SSRegister]! Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>reconcilePoppingWith: (in category 'compile abstract instructions') ----- reconcilePoppingWith: targetEntry "Make the state of a targetEntry, a stack entry following a non-inlined special selector send, the same as the corresponding entry (the receiver) along the inlined path." <var: #targetEntry type: #'targetEntry *'> | targetReg | targetEntry spilled ifTrue: [self assert: (self isSameEntryAs: targetEntry). (targetReg := targetEntry registerOrNone) = NoReg ifTrue: [^self]. type caseOf: { [SSBaseOffset] -> [cogit MoveMw: offset r: register R: targetReg]. [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg]. [SSConstant] -> [cogit genMoveConstant: constant R: targetReg]. [SSRegister] -> [targetReg ~= register ifTrue: [cogit MoveR: register R: targetReg]] }. ^self]. + (targetEntry type ~= SSConstant + and: [(targetReg := targetEntry registerOrNone) ~= NoReg]) + ifTrue: [cogit PopR: targetReg] + ifFalse: [cogit AddCq: objectRepresentation wordSize R: SPReg]! - targetEntry type = SSConstant ifTrue: - [self assert: (targetEntry registerOrNone) = NoReg. - cogit AddCq: objectRepresentation wordSize R: SPReg. - ^self]. - (targetReg := targetEntry registerOrNone) ~= NoReg ifTrue: - [cogit PopR: targetReg. - ^self]. - self halt! Item was changed: ----- Method: Cogit>>recordProcessing (in category 'simulation only') ----- recordProcessing | inst | self recordRegisters. inst := self recordLastInstruction. "Set RRRName ito the selector that accesses ReceiverResultReg (RRR) to alter instruction printing to add the value of RRR as a suffix (RRRName := #rdx) (RRRName := #edx) + (RRRName := nil)" - (RRRName := #nil)" printRegisters ifTrue: [RRRName ifNil: [processor printRegistersOn: coInterpreter transcript]. printInstructions ifFalse: [coInterpreter transcript cr]]. printInstructions ifTrue: [printRegisters ifTrue: [coInterpreter transcript cr]. coInterpreter transcript nextPutAll: inst. RRRName ifNotNil: [coInterpreter transcript space; nextPutAll: RRRName; space. (processor perform: RRRName) printOn: coInterpreter transcript base: 16 length: 8 padded: false]. coInterpreter transcript cr; flush]! Item was changed: ----- Method: RegisterAllocatingCogit>>allocateRegForStackEntryAt: (in category 'simulation stack') ----- allocateRegForStackEntryAt: index "If the stack entry is already in a register, answers it, else allocate a new register for it" <inline: true> + | reg | + (reg := (self ssValue: index) registerOrNone) ~= NoReg ifTrue: + [^reg]. + ^self allocateRegForStackEntryAt: index notConflictingWith: (self liveRegisters bitOr: (self registerMaskFor: FPReg and: SPReg and: TempReg))! - ^self allocateRegForStackEntryAt: index notConflictingWith: (self registerMaskFor: FPReg and: SPReg and: TempReg)! Item was removed: - ----- Method: RegisterAllocatingCogit>>captureUnspilledSpillsForSpecialSelectorSend: (in category 'bytecode generator support') ----- - captureUnspilledSpillsForSpecialSelectorSend: liveRegisterMask - "Since we're allocating values in registers we would like to keep those registers live on the inlined path - and reload registers along the non-inlined send path. But any values that would need to be spilled - along the non-inlined path must be captured before the split so that both paths can join. If we don't - capture the values on the non-inlined path we could access stale values. So for all stack entries that - would be spilled along the non-inlined path, assign them to registers, or spill if none are available." - | i liveRegs reg | - liveRegs := liveRegisterMask. - self assert: (simSelf liveRegister = ReceiverResultReg) = optStatus isReceiverResultRegLive. - optStatus isReceiverResultRegLive ifTrue: - [liveRegs := liveRegs + (self registerMaskFor: ReceiverResultReg)]. - reg := TempReg. "Anything but NoReg" - i := simStackPtr + 1. "We must spill a contiguous range at the hot top of stack, so we assign coldest first :-(" - [reg ~= NoReg and: [i > simSpillBase and: [i > 0]]] whileTrue: - [i := i - 1. - ((self simStackAt: i) spilled not - and: [(self simStackAt: i) type = SSBaseOffset]) ifTrue: - [reg := self allocateRegNotConflictingWith: liveRegs. - reg ~= NoReg ifTrue: - [(self simStackAt: i) storeToReg: reg. - liveRegs := liveRegs bitOr: (self registerMaskFor: reg)]]]. - reg = NoReg ifTrue: - [self ssFlushTo: i]! Item was added: + ----- Method: RegisterAllocatingCogit>>deassignRegisterForTempVar:in: (in category 'bytecode generator support') ----- + deassignRegisterForTempVar: targetEntry in: mergeSimStack + "If merging a non-temp with a temp that has a live register we can assign + to the register, but must unassign the register from the temp, otherwise + the temp will acquire the merged value without an assignment. The targetEntry + must also be transmogrified into an SSRegister entry." + <var: #targetEntry type: #'SimStackEntry *'> + <var: #mergeSimStack type: #'SimStackEntry *'> + <inline: true> + | reg | + reg := targetEntry liveRegister. + self assert: (targetEntry type = SSBaseOffset and: [targetEntry register = FPReg]). + simStackPtr to: 0 by: -1 do: + [:j| | duplicateEntry | + duplicateEntry := self simStack: mergeSimStack at: j. + (targetEntry isSameEntryAs: duplicateEntry) ifTrue: + [duplicateEntry liveRegister: NoReg]]. + targetEntry + type: SSRegister; + register: reg! Item was changed: ----- Method: RegisterAllocatingCogit>>genSpecialSelectorArithmetic (in category 'bytecode generators') ----- genSpecialSelectorArithmetic + | primDescriptor rcvrIsConst argIsConst rcvrIsInt argIsInt rcvrInt argInt destReg + jumpNotSmallInts jumpContinue jumpOverflow index rcvrReg argReg regMask | + <var: #jumpOverflow type: #'AbstractInstruction *'> - | primDescriptor rcvrIsConst argIsConst rcvrIsInt argIsInt rcvrInt argInt result - jumpNotSmallInts jumpContinue index rcvrReg argReg regMask | <var: #jumpContinue type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> primDescriptor := self generatorAt: byte0. argIsInt := (argIsConst := self ssTop type = SSConstant) and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := (rcvrIsConst := (self ssValue: 1) type = SSConstant) and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]. (argIsInt and: [rcvrIsInt]) ifTrue: + [| result | + rcvrInt := objectMemory integerValueOf: rcvrInt. - [rcvrInt := objectMemory integerValueOf: rcvrInt. argInt := objectMemory integerValueOf: argInt. primDescriptor opcode caseOf: { [AddRR] -> [result := rcvrInt + argInt]. [SubRR] -> [result := rcvrInt - argInt]. [AndRR] -> [result := rcvrInt bitAnd: argInt]. + [OrRR] -> [result := rcvrInt bitOr: argInt] }. - [OrRR] -> [result := rcvrInt bitOr: argInt] }. (objectMemory isIntegerValue: result) ifTrue: ["Must annotate the bytecode for correct pc mapping." ^self ssPop: 2; ssPushAnnotatedConstant: (objectMemory integerObjectOf: result)]. ^self genSpecialSelectorSend]. "If there's any constant involved other than a SmallInteger don't attempt to inline." ((rcvrIsConst and: [rcvrIsInt not]) or: [argIsConst and: [argIsInt not]]) ifTrue: [^self genSpecialSelectorSend]. "If we know nothing about the types then better not to inline as the inline cache and primitive code is not terribly slow so wasting time on duplicating tag tests is pointless." (argIsInt or: [rcvrIsInt]) ifFalse: [^self genSpecialSelectorSend]. "Since one or other of the arguments is an integer we can very likely profit from inlining. + But if the other type is not SmallInteger or if the operation overflows then we will need + to do a send. Since we're allocating values in registers we would like to keep those + registers live on the inlined path and reload registers along the non-inlined send path. + See reconcileRegisterStateForJoinAfterSpecialSelectorSend below." - But if the other type is not SmallInteger or if the operation overflows then we will need to do a send. - Since we're allocating values in registers we would like to keep those registers live on the inlined path - and reload registers along the non-inlined send path. But any values that would need to be spilled - along the non-inlined path must be captured before the split so that both paths can join. If we don't - capture the values on the non-iblined path we could access stale values. So for all stack entries that - would be spilled along the non-inlined path, assign them to registers, or spill if none are available." argIsInt ifTrue: [rcvrReg := self allocateRegForStackEntryAt: 1. (self ssValue: 1) popToReg: rcvrReg. self MoveR: rcvrReg R: TempReg. regMask := self registerMaskFor: rcvrReg] ifFalse: [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. self ssTop popToReg: argReg. (self ssValue: 1) popToReg: rcvrReg. self MoveR: argReg R: TempReg. regMask := self registerMaskFor: rcvrReg and: argReg]. + + "rcvrReg can be reused for the result iff the receiver is a constant or is an SSRegister that is not used elsewhere." + destReg := (rcvrIsInt + or: [(self ssValue: 1) type = SSRegister + and: [(self anyReferencesToRegister: rcvrReg inAllButTopNItems: 2) not]]) + ifTrue: [rcvrReg] + ifFalse: [self allocateRegNotConflictingWith: regMask]. self ssPop: 2. - self captureUnspilledSpillsForSpecialSelectorSend: regMask. jumpNotSmallInts := (argIsInt or: [rcvrIsInt]) ifTrue: [objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: rcvrReg andScratch: TempReg scratch: ClassReg]. + rcvrReg ~= destReg ifTrue: + [self MoveR: rcvrReg R: destReg]. primDescriptor opcode caseOf: { [AddRR] -> [argIsInt ifTrue: + [self AddCq: argInt - ConstZero R: destReg. - [self AddCq: argInt - ConstZero R: rcvrReg. jumpContinue := self JumpNoOverflow: 0. + "overflow; must undo the damage before doing send" + rcvrReg = destReg ifTrue: + [self SubCq: argInt - ConstZero R: rcvrReg]] - "overflow; must undo the damage before continuing" - self SubCq: argInt - ConstZero R: rcvrReg] ifFalse: + [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: destReg. + self AddR: argReg R: destReg. + jumpContinue := self JumpNoOverflow: 0. + "overflow; must undo the damage before doing send" + destReg = rcvrReg ifTrue: + [rcvrIsInt + ifTrue: [self MoveCq: rcvrInt R: rcvrReg] + ifFalse: + [self SubR: argReg R: rcvrReg. + objectRepresentation genSetSmallIntegerTagsIn: rcvrReg]]]]. - [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: rcvrReg. - self AddR: argReg R: rcvrReg. - jumpContinue := self JumpNoOverflow: 0. - "overflow; must undo the damage before continuing" - rcvrIsInt - ifTrue: [self MoveCq: rcvrInt R: rcvrReg] - ifFalse: - [self SubR: argReg R: rcvrReg. - objectRepresentation genSetSmallIntegerTagsIn: rcvrReg]]]. [SubRR] -> [argIsInt ifTrue: + [self SubCq: argInt - ConstZero R: destReg. - [self SubCq: argInt - ConstZero R: rcvrReg. jumpContinue := self JumpNoOverflow: 0. + "overflow; must undo the damage before doing send" + rcvrReg = destReg ifTrue: + [self AddCq: argInt - ConstZero R: rcvrReg]] - "overflow; must undo the damage before continuing" - self AddCq: argInt - ConstZero R: rcvrReg] ifFalse: + [(self anyReferencesToRegister: argReg inAllButTopNItems: 0) + ifTrue: "argReg is live; cannot strip tags and continue on no overflow without restoring tags" + [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: argReg. + self SubR: argReg R: destReg. + jumpOverflow := self JumpOverflow: 0. + "no overflow; must undo the damage before continuing" + objectRepresentation genSetSmallIntegerTagsIn: argReg. + jumpContinue := self Jump: 0. + jumpOverflow jmpTarget: self Label. + "overflow; must undo the damage before doing send" + (rcvrIsInt or: [destReg ~= rcvrReg]) ifFalse: + [self AddR: argReg R: destReg]. + objectRepresentation genSetSmallIntegerTagsIn: argReg] + ifFalse: + [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: argReg. + self SubR: argReg R: destReg. + jumpContinue := self JumpNoOverflow: 0. + "overflow; must undo the damage before doing send" + (rcvrIsInt or: [destReg ~= rcvrReg]) ifFalse: + [self AddR: argReg R: rcvrReg]. + objectRepresentation genSetSmallIntegerTagsIn: argReg]]]. - [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: argReg. - self SubR: argReg R: rcvrReg. - jumpContinue := self JumpNoOverflow: 0. - "overflow; must undo the damage before continuing" - self AddR: argReg R: rcvrReg. - objectRepresentation genSetSmallIntegerTagsIn: argReg]]. [AndRR] -> [argIsInt + ifTrue: [self AndCq: argInt R: destReg] + ifFalse: [self AndR: argReg R: destReg]. - ifTrue: [self AndCq: argInt R: rcvrReg] - ifFalse: [self AndR: argReg R: rcvrReg]. jumpContinue := self Jump: 0]. [OrRR] -> [argIsInt + ifTrue: [self OrCq: argInt R: destReg] + ifFalse: [self OrR: argReg R: destReg]. - ifTrue: [self OrCq: argInt R: rcvrReg] - ifFalse: [self OrR: argReg R: rcvrReg]. jumpContinue := self Jump: 0] }. jumpNotSmallInts jmpTarget: self Label. + self ssPushRegister: destReg. - self ssPushRegister: rcvrReg. self copySimStackToScratch: (simSpillBase min: simStackPtr - 1). self ssPop: 1. self ssFlushTo: simStackPtr. self deny: rcvrReg = Arg0Reg. argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg] ifFalse: [argReg ~= Arg0Reg ifTrue: [self MoveR: argReg R: Arg0Reg]]. rcvrReg ~= ReceiverResultReg ifTrue: [self MoveR: rcvrReg R: ReceiverResultReg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines. self reconcileRegisterStateForJoinAfterSpecialSelectorSend. jumpContinue jmpTarget: self Label. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor rcvrIsInt argIsInt argInt jumpNotSmallInts inlineCAB index rcvrReg argReg regMask | <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> primDescriptor := self generatorAt: byte0. argIsInt := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := (self ssValue: 1) type = SSConstant and: [objectMemory isIntegerObject: (self ssValue: 1) constant]. (argIsInt and: [rcvrIsInt]) ifTrue: [^ self genStaticallyResolvedSpecialSelectorComparison]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsInt or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. + "In-line the comparison and the jump, but if the types are not SmallInteger then we will need + to do a send and fall through to the following conditional branch. Since we're allocating values + in registers we would like to keep those registers live on the inlined path and reload registers + along the non-inlined send path. The merge logic at the branch destinations handles this." - "In-line, but if the types are not SmallInteger then we will need to do a send. - Since we're allocating values in registers we would like to keep those registers live on the inlined path - and reload registers along the non-inlined send path. But any values that would need to be spilled - along the non-inlined path must be captured before the split so that both paths can join. If we don't - capture the values on the non-iblined path we could access stale values. So for all stack entries that - would be spilled along the non-inlined path, assign them to registers, or spill if none are available." argIsInt ifTrue: [rcvrReg := self allocateRegForStackEntryAt: 1. (self ssValue: 1) popToReg: rcvrReg. self MoveR: rcvrReg R: TempReg. regMask := self registerMaskFor: rcvrReg] ifFalse: [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. rcvrReg = Arg0Reg ifTrue: [rcvrReg := argReg. argReg := Arg0Reg]. self ssTop popToReg: argReg. (self ssValue: 1) popToReg: rcvrReg. self MoveR: argReg R: TempReg. regMask := self registerMaskFor: rcvrReg and: argReg]. self ssPop: 2. - self captureUnspilledSpillsForSpecialSelectorSend: regMask. jumpNotSmallInts := (argIsInt or: [rcvrIsInt]) ifTrue: [objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: rcvrReg andScratch: TempReg scratch: ClassReg]. argIsInt ifTrue: [self CmpCq: argInt R: rcvrReg] ifFalse: [self CmpR: argReg R: rcvrReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). jumpNotSmallInts jmpTarget: self Label. self ssFlushTo: simStackPtr. self deny: rcvrReg = Arg0Reg. argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg] ifFalse: [argReg ~= Arg0Reg ifTrue: [self MoveR: argReg R: Arg0Reg]]. rcvrReg ~= ReceiverResultReg ifTrue: [self MoveR: rcvrReg R: ReceiverResultReg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup <var: #fixup type: #'BytecodeFixup *'> | mergeSimStack currentEntry targetEntry | <var: #mergeSimStack type: #'SimStackEntry *'> "At a merge point the cogit expects the stack to be in the same state as mergeSimStack. mergeSimStack is the state as of some jump forward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. The state of optStatus must agree." - <var: #currentEntry type: #'SimStackEntry *'> <var: #targetEntry type: #'SimStackEntry *'> + <var: #currentEntry type: #'SimStackEntry *'> + <var: #duplicateEntry type: #'SimStackEntry *'> (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. "Assignments amongst the registers must be made in order to avoid overwriting. If necessary exchange registers amongst simStack's entries to resolve any conflicts." self resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: mergeSimStack. self assert: (self conflcitsResolvedBetweenSimStackAnd: mergeSimStack). simStackPtr to: 0 by: -1 do: [:i| currentEntry := self simStack: simStack at: i. targetEntry := self simStack: mergeSimStack at: i. + (currentEntry reconcileForwardsWith: targetEntry) ifTrue: + [self assert: i >= methodOrBlockNumArgs. + self deassignRegisterForTempVar: targetEntry in: mergeSimStack]. - currentEntry reconcileForwardsWith: targetEntry. "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: spilled ifFalse: [simSpillBase := i - 1]. simStack at: i put: (self cCode: [mergeSimStack at: i] inSmalltalk: [(mergeSimStack at: i) copy])"]. "a.k.a. fixup isReceiverResultRegSelf: (fixup isReceiverResultRegSelf and: [optStatus isReceiverResultRegLive])" optStatus isReceiverResultRegLive ifFalse: [fixup isReceiverResultRegSelf: false]! Item was added: + ----- Method: StackToRegisterMappingCogit>>anyReferencesToRegister:inAllButTopNItems: (in category 'simulation stack') ----- + anyReferencesToRegister: reg inAllButTopNItems: n + | regMask | + regMask := self registerMaskFor: reg. + simStackPtr - n to: 0 by: -1 do: + [:i| + ((self simStackAt: i) registerMask anyMask: regMask) ifTrue: + [^true]]. + ^false!

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Just had a "doh!" moment with literal variable unforwarding...
by Eliot Miranda 05 Dec '16

05 Dec '16

Hi Clément, I just realized that if we maintain a list of machine code methods that reference global variables, in a similar fashion to the list of methods that refer to new literals, then we can scan the list post-become and ensure that all are unforwarded. hence the code generator can avoid generating the unforwarding code on access. We could probably use the same list for both methods with global references and methods with new references. Since a method is marked as referring to new objects (cmRefersToYoung) we can avoid scanning methods that simply refer to globals when we scavenge. That we have to visit a few extra methods after become (the cmRefersToYoung methods that don't refer to globals) is unlikely to be a hardship; there are very few methods on the youngReferrers list. What do you think? _,,,^..^,,,_ best, Eliot

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VM Maker: VMMaker.oscog-EstebanLorenzano.2024.mcz
by commits＠source.squeak.org 05 Dec '16

05 Dec '16

Esteban Lorenzano uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-EstebanLorenzano.2024.mcz ==================== Summary ==================== Name: VMMaker.oscog-EstebanLorenzano.2024 Author: EstebanLorenzano Time: 5 December 2016, 9:57:01.004046 am UUID: 7870434f-e14e-4873-b8b9-5f639ef5d66d Ancestors: VMMaker.oscog-eem.2023 rename temp var to avoid conflict with global while generating sources. =============== Diff against VMMaker.oscog-eem.2023 =============== Item was changed: ----- Method: CogBytecodeFixup>>recordBcpc: (in category 'simulation') ----- + recordBcpc: theBytecodePC - recordBcpc: bytecodePC <inline: true> self cCode: '' inSmalltalk: [bcpc + ifNil: [bcpc := theBytecodePC] - ifNil: [bcpc := bytecodePC] ifNotNil: [bcpc := bcpc isInteger + ifTrue: [{bcpc. theBytecodePC}] + ifFalse: [bcpc, {theBytecodePC}]]]! - ifTrue: [{bcpc. bytecodePC}] - ifFalse: [bcpc, {bytecodePC}]]]!

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Vm-dev December 2016