tim Rowledge uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1530.mcz
==================== Summary ====================
Name: VMMaker.oscog-tpr.1530 Author: tpr Time: 22 November 2015, 11:18:39.8 am UUID: 0f807d01-9fc9-4fd6-8c9d-8763700efed1 Ancestors: VMMaker.oscog-eem.1529
Split out testing of ARM instrucction condition codes and make sure it is checked for CMP/ORR - just in case.
=============== Diff against VMMaker.oscog-eem.1529 ===============
Item was added: + ----- Method: CogARMCompiler>>conditionIsNotNever: (in category 'testing') ----- + conditionIsNotNever: instr + "test for the NV condition code; this isn't allowed as an actual condition and is used to encdoe many of the newer instructions" + ^instr >> 28 < 16rF !
Item was changed: ----- Method: CogARMCompiler>>instructionIsB: (in category 'testing') ----- instructionIsB: instr "is this a B <offset> instruction?" + ^(self conditionIsNotNever: instr) and: [(instr bitAnd: (16rF<<24)) = (16rA<<24)]! - ^instr >> 28 < 16rF "test for allowed condcode - 0xF is extension" and: [(instr bitAnd: (16rF<<24)) = (16rA<<24)]!
Item was changed: ----- Method: CogARMCompiler>>instructionIsBL: (in category 'testing') ----- instructionIsBL: instr "is this a BL <offset> instruction?" + ^(self conditionIsNotNever: instr) and: [(instr bitAnd: (16rF<<24)) = (16rB<<24)]! - ^instr >> 28 < 16rF "test for allowed condcode - 0xF is extension" and: [(instr bitAnd: (16rF<<24)) = (16rB<<24)]!
Item was changed: ----- Method: CogARMCompiler>>instructionIsBLX: (in category 'testing') ----- instructionIsBLX: instr "is this a BLX <targetReg> instruction?" + ^(self conditionIsNotNever: instr) and: [(instr bitAnd: 16r0FFFFFF0) = 16r12FFF30]! - ^instr >> 28 < 16rF "test for allowed condcode - 0xF is extension" and: [(instr bitAnd: 16r0FFFFFF0) = 16r12FFF30]!
Item was changed: ----- Method: CogARMCompiler>>instructionIsBX: (in category 'testing') ----- instructionIsBX: instr "is this a BX <targetReg> instruction?" + ^(self conditionIsNotNever: instr) and: [(instr bitAnd: 16r0FFFFFF0) = 16r12FFF10]! - ^instr >> 28 < 16rF "test for allowed condcode - 0xF is extension" and: [(instr bitAnd: 16r0FFFFFF0) = 16r12FFF10]!
Item was changed: ----- Method: CogARMCompiler>>instructionIsCMP: (in category 'testing') ----- instructionIsCMP: instr + "is this a CMP instruction?" + ^(self conditionIsNotNever: instr) and: [(instr >> 21 bitAnd: 16r7F) = CmpOpcode]! - "is this an CMP instruction?" - ^(instr >> 21 bitAnd: 16r7F) = CmpOpcode!
Item was changed: ----- Method: CogARMCompiler>>instructionIsLDR: (in category 'testing') ----- instructionIsLDR: instr "is this any kind of LDR instruction? c.f. memMxr:reg:base:u:b:l:imm:" + ^(self conditionIsNotNever: instr) and: [(instr >> 20 bitAnd: 16rC5) = 16r41] "ldr r1, [r2, #+/-imm] or ldr r1, [r2, r3]"! - ^instr >> 28 ~= 16rF "the NEVER condition is used to encode non-load instructions" - and: [(instr >> 20 bitAnd: 16rC5) = 16r41] "ldr r1, [r2, #+/-imm] or ldr r1, [r2, r3]"!
Item was changed: ----- Method: CogARMCompiler>>instructionIsOR: (in category 'testing') ----- instructionIsOR: instr "is this an ORR instruction?" + ^(self conditionIsNotNever: instr) and:[(instr >> 21 bitAnd: 16r7F) = (16r10 bitOr: OrOpcode)]! - ^(instr >> 21 bitAnd: 16r7F) = (16r10 bitOr: OrOpcode)!
Item was changed: ----- Method: CogARMCompiler>>instructionIsPush: (in category 'testing') ----- instructionIsPush: instr "is this a push -str r??, [sp, #-4] - instruction?" + ^(self conditionIsNotNever: instr) and: [(instr bitAnd: 16rFFF0FFF) = 16r52D0004]! - ^instr >> 28 < 16rF "test for allowed condcode - 0xF is extension" - and: [(instr bitAnd: 16rFFF0FFF) = 16r52D0004]!
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