Vm-dev December 2019

vm-dev@lists.squeakfoundation.org

31 participants
265 discussions

A fork in the road()
by Ben Coman 21 Jan '20

21 Jan '20

Sharing an interesting paper I bumped into.. > A fork() in the road > https://www.microsoft.com/en-us/research/uploads/prod/2019/04/fork-hotos19.… in particular Figure 1 - fork versus spawn performance And something I didn't realise... > a process using, DPDK with a kernel-bypass NIC [12], or OpenCL with a GPU, > cannot safely fork since the OS cannot duplicate the process state on the NIC/GPU. > This appears to have been a continuing source of bafflement > among GPU programmers for a decade at least cheers -ben

4 3

VM Maker: VMMaker.oscog-eem.2602.mcz
by commits＠source.squeak.org 10 Jan '20

10 Jan '20

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2602.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2602 Author: eem Time: 3 December 2019, 6:33:22.314018 pm UUID: d0c7f3ff-f03b-4072-a00a-9425ed2b301a Ancestors: VMMaker.oscog-eem.2601 More work for CogARMv8Compiler. Add concretizeAddCqR and concretizeAndCqRDest:. Now seven instructions into generating ceDereferenceSelectorIndex. ARMv8 has an amazingly exotic scheme for encoding bitfields as immediates in logical operations. Copy LLVM's encoder. So far this is unverified because I cannot make sense of immN:NOT(imms) in len = HighestSetBit(immN:NOT(imms)); in DecodeBitMasks on page J1-7389 of the Arm ARM. If you can make sense of this either consider fully implementing CogARMv8Compiler>>decodeBitMasksN:imms:immr: or explaining to me what is meant by "immN:NOT(imms)" (via email to OpenSMalltalk-VM ?). AdvThanksance. =============== Diff against VMMaker.oscog-eem.2601 =============== Item was changed: CogAbstractInstruction subclass: #CogARMv8Compiler instanceVariableNames: '' + classVariableNames: 'AL AddOpcode AndOpcode CC CS CmpOpcode D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 EQ FP GE GT HI LE LR LS LT MI NE OrOpcode PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 SP SXTB SXTH SXTW SXTX SubOpcode UXTB UXTH UXTW UXTX VC VS XZR XorOpcode' - classVariableNames: 'AL AddOpcode AndOpcode CC CS CmpOpcode D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 EQ FP GE GT HI LE LR LS LT MI NE OrOpcode PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 SP SXTB SXTH SXTW SXTX SubOpcode UXTB UXTH UXTW UXTX VC VS XorOpcode' poolDictionaries: 'ARMv8A64Opcodes' category: 'VMMaker-JIT'! !CogARMv8Compiler commentStamp: 'eem 12/3/2019 08:45' prior: 0! I generate ARMv8 machine code instructions from CogAbstractInstructions with CogRTLOpcodes. Here in "Arm ARM" refers to Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-ma… Some things to know about ARMv8 instructions: Whether 31 in a register field implies the zero register or the SP register(s) depends on the specific instruction. C3.2.1 Load/Store register If a Load instruction specifies writeback and the register being loaded is also the base register, then behavior is CONSTRAINED UNPREDICTABLE and one of the following behaviors must occur: - The instruction is treated as UNDEFINED. - The instruction is treated as a NOP. - The instruction performs the load using the specified addressing mode and the base register becomes UNKNOWN. In addition, if an exception occurs during the execution of such an instruction, the base address might be corrupted so that the instruction cannot be repeated. If a Store instruction performs a writeback and the register that is stored is also the base register, then behavior is CONSTRAINED UNPREDICTABLE and one of the following behaviors must occur: - The instruction is treated as UNDEFINED. - The instruction is treated as a NOP. - The instruction performs the store to the designated register using the specified addressing mode, but the value stored is UNKNOWN.! Item was changed: ----- Method: CogARMv8Compiler class>>initialize (in category 'class initialization') ----- initialize "Initialize various ARM64 instruction-related constants." "self initialize" "main registers; a minor complication in reading the doc. ARM refer to the 64bit registers as X0...30 and use R0...30 to refer to the 32bit lower halves.They also use a whole suite of names for the floating point/SIMD registers. See ARMARM DDI0487 B1.2.1 etc for the gory details. Note that R30 (yes, yes, X30) is used as the link register and as such is not really a general purpose register. Also note that R31 (named XZR in ARM doc) is a pseudo-register that always reads as 0 and writes to /dev/null. And note that unlike the ARM32, there is no general purpose register for either the PC or SP; a big difference. See ARMARM DDI0487 C1.2.5. wrt to both issues. We will stick with R0...30 to refer to the 64 bit general regs and D0...31 (note the extra reg here!!) for the FP/SIMD regs" #( (D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31) (R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31)) do: [:classVarNames| classVarNames doWithIndex: [:k :v| CogARMv8Compiler classPool at: k put: v - 1]]. + + SP := XZR := R31. + LR := R30. + FP := R29. + - "Condition Codes. Note that cc=16rF is mapped back to AL in AARCH64. Generally it shouldn't be used" "Perhaps have these in the ARMv8A64Opcodes pool?" EQ := 0. NE := 1. CS := 2. CC := 3. MI := 4. PL := 5. VS := 6. VC := 7. HI := 8. LS := 9. GE := 10. LT := 11. GT := 12. LE := 13. AL := 14. "Extension Methods " UXTB := 2r000. UXTH := 2r001. UXTW := 2r010. UXTX := 2r011. "a.k.a. LSL" SXTB := 2r100. SXTH := 2r101. SXTW := 2r110. SXTX := 2r111! Item was changed: ----- Method: CogARMv8Compiler class>>initializeAbstractRegisters (in category 'class initialization') ----- initializeAbstractRegisters "Assign the abstract registers with the identities/indices of the relevant concrete registers." super initializeAbstractRegisters. "See Table 3-1 Register Usage in AArch64 SMC32, HVC32, SMC64, and HVC64 calls in SMC CALLING CONVENTION System Software on ARM® Platforms Document number: ARM DEN 0028B http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_… " CallerSavedRegisterMask := (self registerMaskFor: 0 and: 1 and: 2 and: 3 and: 4 and: 5 and: 6 and: 7 and: 8 and: 9) + (self registerMaskFor: 10 and: 11 and: 12 and: 13 and: 14 and: 15 and: 16 and: 17). TempReg := R0. ClassReg := R4. ReceiverResultReg := R5. SendNumArgsReg := R6. Arg0Reg := R7. Arg1Reg := R8. "X18/R18 is the Platform register; leave it be" Extra0Reg := R19. "R18 through R28 are callee saved" Extra1Reg := R20. Extra2Reg := R21. Extra3Reg := R22. Extra4Reg := R23. Extra5Reg := R24. Extra6Reg := R25. Extra7Reg := R26. VarBaseReg := R27. RISCTempReg := R28. + FPReg := FP "a.k.a. R29". + LinkReg := LR "a.k.a. R30". + SPReg := SP "a.k.a. R31". - FPReg := FP := R29. - LinkReg := LR := R30. - SPReg := SP := R31. NumRegisters := 32. DPFPReg0 := D0. DPFPReg1 := D1. DPFPReg2 := D2. DPFPReg3 := D3. DPFPReg4 := D4. DPFPReg5 := D5. DPFPReg6 := D6. DPFPReg7 := D7. DPFPReg8 := D8. DPFPReg9 := D9. DPFPReg10 := D10. DPFPReg11 := D11. DPFPReg12 := D12. DPFPReg13 := D13. DPFPReg14 := D14. DPFPReg15 := D15. NumFloatRegisters := 32! Item was added: + ----- Method: CogARMv8Compiler>>concretizeAddCqR (in category 'generate machine code - concretize') ----- + concretizeAddCqR + "Will get inlined into concretizeAt: switch." + <inline: true> + | constant reg offset | + constant := operands at: 0. + reg := operands at: 1. + + self deny: reg = SP. "For now; how to add an immediate to the SP?" + self isPossiblyShiftableImm12: constant + ifTrue: + [:shift| + "C6.2.8 ADDS (immediate) C6-769" + machineCode + at: 0 + put: 2r101100010 << 23 + + (shift ifTrue: [constant >> 2 + (1 << 22)] ifFalse: [constant << 10]) + + (reg << 5) + + reg. + ^machineCodeSize := 4] + ifFalse: []. + offset := self moveCw: constant intoR: RISCTempReg. + "C6.2.7 ADDS (extended register) C6-766" + machineCode + at: offset // 4 + put: 2r10101011001 + + (RISCTempReg << 16) + + (SXTX << 13) + + (reg << 5) + + reg. + ^machineCodeSize := offset + 4! Item was added: + ----- Method: CogARMv8Compiler>>concretizeAndCqRDest: (in category 'generate machine code - concretize') ----- + concretizeAndCqRDest: destReg + "C6.2.14 ANDS (immediate) C6-779 + C6.2.329 TST (immediate) C6-1346" + | srcReg constant offset | + constant := operands at: 0. + srcReg := operands at: 1. + self isImmNImmSImmREncodableBitmask: constant + ifTrue: + [:n :imms :immr| + machineCode + at: 0 + put: 2r111100100 << 23 + + (n << 22) + + (immr << 16) + + (imms << 10) + + (srcReg << 5) + + destReg. + ^machineCodeSize := 4] + ifFalse: []. + offset := self moveCw: constant intoR: RISCTempReg. + "C6.2.15 ANDS (shifted register) C6-781" + machineCode + at: offset // 4 + put: 2r11101010 << 24 + + (RISCTempReg << 16) + + (srcReg << 5) + + destReg. + ^machineCodeSize := offset + 4! Item was added: + ----- Method: CogARMv8Compiler>>countTrailingOnes: (in category 'generate machine code - support') ----- + countTrailingOnes: anInteger + | bits count | + self assert: anInteger ~= 0. + "Lazy; we could use binary chop" + bits := anInteger. + count := 0. + [(bits bitAnd: 1) = 1] whileTrue: + [bits := bits bitShift: -1. + count := count + 1]. + ^count! Item was added: + ----- Method: CogARMv8Compiler>>countTrailingZeros: (in category 'generate machine code - support') ----- + countTrailingZeros: anInteger + self assert: anInteger ~= 0. + ^self cCode: "Lazy; we could use binary chop" + [| bits count | + bits := anInteger. + count := 0. + [(bits bitAnd: 1) = 0] whileTrue: + [bits := bits bitShift: -1. + count := count + 1]. + count] + inSmalltalk: [anInteger lowBit - 1]! Item was added: + ----- Method: CogARMv8Compiler>>decodeBitMasksN:imms:immr: (in category 'generate machine code - support') ----- + decodeBitMasksN: immN imms: imms immr: immr + "See aarch64/instrs/integer/bitmasks/DecodeBitMasks J1-7389" + | tmask wmask levels | + "eem 12/3/2019 18:17 + In + + len = HighestSetBit(immN:NOT(imms)); + + I have no clue what is meant by + + immN:NOT(imms) + + Reading Arm Pseudocode Definition K13.4 Operators leaves me none the wiser." + self shouldBeImplemented! Item was changed: ----- Method: CogARMv8Compiler>>dispatchConcretize (in category 'generate machine code') ----- dispatchConcretize "Attempt to generate concrete machine code for the instruction at address. This is the inner dispatch of concretizeAt: actualAddress which exists only to get around the branch size limits in the SqueakV3 (blue book derived) bytecode set." <returnTypeC: #void> opcode caseOf: { "Noops & Pseudo Ops" [Label] -> [^self concretizeLabel]. [Literal] -> [^self concretizeLiteral]. [AlignmentNops] -> [^self concretizeAlignmentNops]. [Fill32] -> [^self concretizeFill32]. [Nop] -> [^self concretizeNop]. "Control" [Call] -> [^self concretizeCall]. "call code within code space" [CallFull] -> [^self concretizeCallFull]. "call code anywhere in address space" [JumpR] -> [^self concretizeJumpR]. [JumpFull] -> [^self concretizeJumpFull]."jump within address space" [JumpLong] -> [^self concretizeConditionalJump: AL]."jumps witihn code space" [JumpLongZero] -> [^self concretizeConditionalJump: EQ]. [JumpLongNonZero] -> [^self concretizeConditionalJump: NE]. [Jump] -> [^self concretizeConditionalJump: AL]. [JumpZero] -> [^self concretizeConditionalJump: EQ]. [JumpNonZero] -> [^self concretizeConditionalJump: NE]. [JumpNegative] -> [^self concretizeConditionalJump: MI]. [JumpNonNegative] -> [^self concretizeConditionalJump: PL]. [JumpOverflow] -> [^self concretizeConditionalJump: VS]. [JumpNoOverflow] -> [^self concretizeConditionalJump: VC]. [JumpCarry] -> [^self concretizeConditionalJump: CS]. [JumpNoCarry] -> [^self concretizeConditionalJump: CC]. [JumpLess] -> [^self concretizeConditionalJump: LT]. [JumpGreaterOrEqual] -> [^self concretizeConditionalJump: GE]. [JumpGreater] -> [^self concretizeConditionalJump: GT]. [JumpLessOrEqual] -> [^self concretizeConditionalJump: LE]. [JumpBelow] -> [^self concretizeConditionalJump: CC]. "unsigned lower" [JumpAboveOrEqual] -> [^self concretizeConditionalJump: CS]. "unsigned greater or equal" [JumpAbove] -> [^self concretizeConditionalJump: HI]. [JumpBelowOrEqual] -> [^self concretizeConditionalJump: LS]. [JumpFPEqual] -> [^self concretizeFPConditionalJump: EQ]. [JumpFPNotEqual] -> [^self concretizeFPConditionalJump: NE]. [JumpFPLess] -> [^self concretizeFPConditionalJump: LT]. [JumpFPGreaterOrEqual] -> [^self concretizeFPConditionalJump: GE]. [JumpFPGreater] -> [^self concretizeFPConditionalJump: GT]. [JumpFPLessOrEqual] -> [^self concretizeFPConditionalJump: LE]. [JumpFPOrdered] -> [^self concretizeFPConditionalJump: VC]. [JumpFPUnordered] -> [^self concretizeFPConditionalJump: VS]. [RetN] -> [^self concretizeRetN]. [Stop] -> [^self concretizeStop]. "Arithmetic" + [AddCqR] -> [^self concretizeAddCqR]. - [AddCqR] -> [^self concretizeNegateableDataOperationCqR: AddOpcode]. [AndCqR] -> [^self concretizeInvertibleDataOperationCqR: AndOpcode]. + [AndCqRR] -> [^self concretizeAndCqRDest: (operands at: 1)]. - [AndCqRR] -> [^self concretizeAndCqRR]. [CmpCqR] -> [^self concretizeCmpCqR]. [OrCqR] -> [^self concretizeDataOperationCqR: OrOpcode]. [SubCqR] -> [^self concretizeSubCqR]. + [TstCqR] -> [^self concretizeAndCqRDest: XZR]. - [TstCqR] -> [^self concretizeTstCqR]. [XorCqR] -> [^self concretizeInvertibleDataOperationCqR: XorOpcode]. [AddCwR] -> [^self concretizeDataOperationCwR: AddOpcode]. [AndCwR] -> [^self concretizeDataOperationCwR: AndOpcode]. [CmpCwR] -> [^self concretizeDataOperationCwR: CmpOpcode]. [OrCwR] -> [^self concretizeDataOperationCwR: OrOpcode]. [SubCwR] -> [^self concretizeDataOperationCwR: SubOpcode]. [XorCwR] -> [^self concretizeDataOperationCwR: XorOpcode]. [AddRR] -> [^self concretizeDataOperationRR: AddOpcode]. [AndRR] -> [^self concretizeDataOperationRR: AndOpcode]. [CmpRR] -> [^self concretizeDataOperationRR: CmpOpcode]. [OrRR] -> [^self concretizeDataOperationRR: OrOpcode]. [SubRR] -> [^self concretizeDataOperationRR: SubOpcode]. [XorRR] -> [^self concretizeDataOperationRR: XorOpcode]. [AddRdRd] -> [^self concretizeAddRdRd]. [CmpRdRd] -> [^self concretizeCmpRdRd]. [DivRdRd] -> [^self concretizeDivRdRd]. [MulRdRd] -> [^self concretizeMulRdRd]. [SubRdRd] -> [^self concretizeSubRdRd]. [SqrtRd] -> [^self concretizeSqrtRd]. [NegateR] -> [^self concretizeNegateR]. [LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR]. [ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR]. [LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR]. [LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR]. [ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR]. [LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR]. [LogicalShiftRightRR] -> [^self concretizeLogicalShiftRightRR]. [ClzRR] -> [^self concretizeClzRR]. "Data Movement" [MoveCqR] -> [^self concretizeMoveCqR]. [MoveCwR] -> [^self concretizeMoveCwR]. [MoveRR] -> [^self concretizeMoveRR]. [MoveAwR] -> [^self concretizeMoveAwR]. [MoveRAw] -> [^self concretizeMoveRAw]. [MoveAbR] -> [^self concretizeMoveAbR]. [MoveRAb] -> [^self concretizeMoveRAb]. [MoveMbrR] -> [^self concretizeMoveMbrR]. [MoveRMbr] -> [^self concretizeMoveRMbr]. [MoveRM16r] -> [^self concretizeMoveRM16r]. [MoveM16rR] -> [^self concretizeMoveM16rR]. [MoveM64rRd] -> [^self concretizeMoveM64rRd]. [MoveMwrR] -> [^self concretizeMoveMwrR]. [MoveXbrRR] -> [^self concretizeMoveXbrRR]. [MoveRXbrR] -> [^self concretizeMoveRXbrR]. [MoveXwrRR] -> [^self concretizeMoveXwrRR]. [MoveRXwrR] -> [^self concretizeMoveRXwrR]. [MoveRMwr] -> [^self concretizeMoveRMwr]. [MoveRdM64r] -> [^self concretizeMoveRdM64r]. [PopR] -> [^self concretizePopR]. [PushR] -> [^self concretizePushR]. [PushCq] -> [^self concretizePushCq]. [PushCw] -> [^self concretizePushCw]. [PrefetchAw] -> [^self concretizePrefetchAw]. "Conversion" [ConvertRRd] -> [^self concretizeConvertRRd]. [ConvertRdR] -> [^self concretizeConvertRdR]. [ConvertRRs] -> [^self concretizeConvertRRs]. [ConvertRsR] -> [^self concretizeConvertRsR]. [ConvertRsRd] -> [^self concretizeConvertRsRd]. [ConvertRdRs] -> [^self concretizeConvertRdRs]. [SignExtend8RR] -> [^self concretizeSignExtend8RR]. [SignExtend16RR] -> [^self concretizeSignExtend16RR]. [SignExtend32RR] -> [^self concretizeSignExtend32RR]. [ZeroExtend8RR] -> [^self concretizeZeroExtend8RR]. [ZeroExtend16RR] -> [^self concretizeZeroExtend16RR]. [ZeroExtend32RR] -> [^self concretizeZeroExtend32RR].}! Item was added: + ----- Method: CogARMv8Compiler>>isImmNImmSImmREncodableBitmask:ifTrue:ifFalse: (in category 'generate machine code - support') ----- + isImmNImmSImmREncodableBitmask: constant ifTrue: trinaryBlock "[:n :imms :immr|...]" ifFalse: nullaryBlock + "See DecodeBitMasks J1-7389. + See https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/ + This method is adapted from The LLVM Compiler Infrastructure, AArch64AddressingModes.h processLogicalImmediate" + + | imm size mask countLeadingOnes countTrailingOnes immr n nImms rotateCount | + (constant between: -1 and: 0) ifTrue: + [^nullaryBlock value]. + imm := constant. + + "First, determine the element size." + size := 32. + [mask := 1 << size - 1. + (imm bitAnd: mask) ~= (imm >> size) + ifTrue: [size := size * 2. false] + ifFalse: [size > 2]] + whileTrue: [size := size / 2]. + + "Second, determine the rotation to make the element be: 0^m 1^n." + mask := 1 << 64 - 1 >> (64 - size). + imm := imm bitAnd: mask. + + (self isShiftedMask: imm) + ifTrue: + [rotateCount := self countTrailingZeros: imm. + countTrailingOnes := self countTrailingOnes: imm >> rotateCount] + ifFalse: + [imm := imm bitOr: mask bitInvert64. + (self isShiftedMask: imm) ifFalse: + [^nullaryBlock value]. + countLeadingOnes := self countLeadingOnes: imm. + rotateCount := 64 - countLeadingOnes. + countTrailingOnes := countLeadingOnes + (self countTrailingOnes: imm) - (64 - size)]. + + "Encode in Immr the number of RORs it would take to get *from* 0^m 1^n + to our target value, where I is the number of RORs to go the opposite direction." + + self assert: size > rotateCount. "rotateCount should be smaller than element size" + immr := size - rotateCount bitAnd: size - 1. + + "If size has a 1 in the n'th bit, create a value that has zeroes in bits [0, n] and ones above that." + nImms := (size - 1) bitInvert64 << 1. + + "Or the CTO value into the low bits, which must be below the Nth bit mentioned above." + nImms := nImms bitOr: countTrailingOnes - 1. + + "Extract the seventh bit and toggle it to create the N field." + n := ((nImms >> 6) bitAnd: 1) bitXor: 1. + + nImms := nImms bitAnd: 16r3F. + + false ifTrue: [self assert: (self decodeBitMasksN: n imms: nImms immr: immr) = constant]. + + ^trinaryBlock + value: n + value: nImms + value: immr + ! Item was added: + ----- Method: CogARMv8Compiler>>isShiftedMask: (in category 'generate machine code - support') ----- + isShiftedMask: anInteger + | bits | + ^anInteger ~= 0 + and: [bits := anInteger - 1 bitOr: anInteger. + (bits bitAnd: bits + 1) = 0]!

3 7

[OpenSmalltalk/opensmalltalk-vm] Mac OS X: Fullscreen not as expected (#407)
by Tom Braun 07 Jan '20

07 Jan '20

Currently it is only possible to maximize Squeak by using the button in the MainDockingBar (it is not possible by using the green button on the window what is slightly unexpected but ok). The fullscreen I get is a Squeak that looks like a typical Mac fullscreen but has several drawbacks: * it is not a new desktop with only the app, but consumes the current desktop * if you change desktop you get strange behaviour with the dock appearing * if you use a second monitor and have a Squeak in fullscreen on your first you get a black background stretched over the whole second monitor The expected behaviour for fullscreen would be a native Mac OS fullscreen. (@ronsaldo someone mentioned to me that is due to the new metalshaders) -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/407

2 1

VM crash in the Squeak3D plugin
by Stéphane Rollandin 01 Jan '20

01 Jan '20

Hello all, For my first post on this list, I would like to submit the bug that prevents one of my game (this one: http://www.zogotounga.net/comp/guardians.htm) to work reliably. I spent quite some time on this, and I ended up with a nice and concise way to crash the Squeak3D plugin. The image is available at: http://www.zogotounga.net/swap/crashlab3.zip Instructions to crash the VM are detailed therein. The 3D scene is very simple, there are only three objects. The crash seems related to a race condition, because inserting a simple delay in the code prevents it - this is detailed in the image itself. I have spent days studying the Smalltalk code, and could not see anything wrong with what is sent to the plugin. It looks to my uninformed eyes as a problem of shared memory, where one rasterizing operation messes up with another happening in parallel (although no processed is being forked on the Smalltalk side). Stef

4 17

The VM to tag
by Eliot Miranda 01 Jan '20

01 Jan '20

Hi All, so it seems things are stabilizing. The CI builds. The recent commits from Nicolas re events seem like goodness to me. Are we agreed that I should tag the a4a08f98c17b23ad54b5e361ffc0280e2ea8e0c3 commit or does anyone suggest an earlier one? This commit has VM sources that are unchanged since Pablo Tesone's fix for gcc compilation of immediate floats. It includes the socket name lookup fixes Levente wanted, and it has very localized but useful fixes for events. My vote would be to choose this. _,,,^..^,,,_ best, Eliot

4 16

Passed: OpenSmalltalk/opensmalltalk-vm#1901 (Cog - f219b72)
by Travis CI 31 Dec '19

31 Dec '19

Build Update for OpenSmalltalk/opensmalltalk-vm ------------------------------------- Build: #1901 Status: Passed Duration: 1 hr, 27 mins, and 57 secs Commit: f219b72 (Cog) Author: Nicolas Cellier Message: Fix the sign of x wheel events in OSX to be inline with "natural scrolling" preference. - The VM should generate positive deltaX for Left to Right trackpad motion - The VM should generate positive deltaY for Bottom to Up trackpad motion For historical reasons, if VM does not send mouse wheel events, but fake keyboard arrow events, then: - The VM should generate a left arrow key for Left to Right trackpad motion - The VM should generate a bottom arrow key for Bottom to Up trackpad motion Not that the preferred direction preference of OSX is taken into account by the VM See https://developer.apple.com/documentation/appkit/nsevent/1525151-isdirectio… Above description is for "natural scrolling" preference (the trackpad does drag the screen contents). It will be inverted if the preference is unset (the trackpad does drag the scroll bar). Note that the `isFlipped` method of the Cocoa/Quartz view presumably ha an impact on sign of vertical motions See https://developer.apple.com/documentation/appkit/nsview/1483532-isflipped OpenSmalltalk VM does use isFlipped YES. View the changeset: https://github.com/OpenSmalltalk/opensmalltalk-vm/compare/9f4fae8b5bca...f2… View the full build log and details: https://travis-ci.org/OpenSmalltalk/opensmalltalk-vm/builds/631316227?utm_m… -- You can unsubscribe from build emails from the OpenSmalltalk/opensmalltalk-vm repository going to https://travis-ci.org/account/preferences/unsubscribe?repository=8795279&ut…. Or unsubscribe from *all* email updating your settings at https://travis-ci.org/account/preferences/unsubscribe?utm_medium=notificati…. Or configure specific recipients for build notifications in your .travis.yml file. See https://docs.travis-ci.com/user/notifications.

1 0

Re: [Vm-dev] VM crash on macOS when maximising with Moom
by Bernhard Pieber 31 Dec '19

31 Dec '19

Dear VM developers, An old crash which had been fixed before seems to be back in the latest VM. [1] [2] I am on a MacBook Pro running macOS Mojave 10.14.6 (18G2022) and use an external 30" Cinema Display with a resolution of 2560 x 1600. I can reliably reproduce the crash: 1. I downloaded the latest 64bit VM package from yesterday's build 2019-12-30. [3] 2. I copy out the image, changes and sources file from Contents/Resources. 3. I start the image by dragging it over the VM. 4. I move the window a bit by dragging the title bar. 5. I hover over the green window button and click the leftmost Moom popup menu button for maximising. [4] 6. The VM crashes. See the attached crash.dmp. Observations which might be interesting: The crash happens not always but most of the time. If I don't move the window before trying to maximise the crash does not happen. The crash does not happen on the internal Retina display with the same resolution. Is there anything I can try to get more debug information? [1] https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/263 [2] http://lists.squeakfoundation.org/pipermail/vm-dev/2016-December/023764.html [3] http://files.squeak.org/5.3beta/Squeak5.3beta-19301-64bit/Squeak5.3beta-193… [4][PastedGraphic-1.png] > Am 09.12.2016 um 16:13 schrieb Bernhard Pieber <bernhard(a)pieber.com>: > > Dear VM developers, > > I would like to help debug this. I built my own VM (macOS Sierra 10.12.1, Xcode 8.1 (8B62)). However, even when I use the debug VM (CocoaDebug.app) I don’t get more information on the command line than in the crash.dmp. > > I am a newbie when it comes to VM building and debugging. How can I help in the best way? Is there a way to debug this using Xcode? > > Bernhard > > <crash.dmp> > >> Am 03.12.2016 um 22:42 schrieb Fabio Niephaus <lists(a)fniephaus.com>: >> >> >> On Sat, Dec 3, 2016 at 6:00 PM Bernhard Pieber <bernhard(a)pieber.com> wrote: >> Hi, >> >> I just had this crash again using the latest Cog Spur VM [1] and the latest trunk image 16852 [2]. I am using macOS Sierra 10.12.1 (16B2555) on a MacBookPro11,1. >> >> Have other Mac users seen this type of crash? >> >> I use Magnet instead of Moom and that seems to be working just fine. However, my current default VM crashes every now and then randomly, but I need to upgrade to a later build to see if this has been fixed. >> >> >> [1] https://bintray.com/opensmalltalk/vm/download_file?file_path=cog_macos32x86… >> [2] http://files.squeak.org/6.0alpha/Squeak6.0alpha-16852-32bit/Squeak6.0alpha-… >> >> >> >>> Am 03.07.2016 um 21:55 schrieb John McIntosh <johnmci(a)smalltalkconsulting.com>: >>> >>> Thanks, this appears to be a problem between the window size that Squeak thinks the screen is, versus the size that open/GL thinks the size is. I had made some changes earlier this summer to handle resizing (manually). Obviously this crash gets triggered by Moom which doesn't follow the manual resize use pattern. >>> >>> On Sun, Jul 3, 2016 at 5:36 AM, Bernhard Pieber <bernhard(a)pieber.com> wrote: >>> >>> Dear VM developers, >>> >>> I can reliably crash the latest stable CogSpur.r3732.app using the Squeak5.1-15113.image when I resize it with Moom (http://manytricks.com/moom/) right after starting the image. I tried to reproduce it by resizing it manually without Moom. I *think* it happened occasionally when resizing manually, but I could not reproduce it today. >>> >>> Versions up to r3427 do not crash. The crash happens starting with version r3602. >>> >>> With the latest unstable version 201606301459 built by Travis the crash still happens. >>> >>> I attach the crash dump for version r3732. Maybe it is helpful. >>> >>> Thanks for all your work! >>> >>> Cheers, >>> Bernhard >>> >>> >>> >>> >>> >>> -- >>> =========================================================================== >>> John M. McIntosh. Corporate Smalltalk Consulting Ltd https://www.linkedin.com/in/smalltalk >>> =========================================================================== >> >

2 1

Disagreement on sign of mouse wheels
by ken.dickey＠whidbey.com 31 Dec '19

31 Dec '19

Sensible would be relative to {0,0}, X increasing right, Y increasing down. $0.02, -KenD

1 0

Canceled: OpenSmalltalk/opensmalltalk-vm#1901 (Cog - f219b72)
by Travis CI 31 Dec '19

31 Dec '19

Build Update for OpenSmalltalk/opensmalltalk-vm ------------------------------------- Build: #1901 Status: Canceled Duration: 4 mins and 6 secs Commit: f219b72 (Cog) Author: Nicolas Cellier Message: Fix the sign of x wheel events in OSX to be inline with "natural scrolling" preference. - The VM should generate positive deltaX for Left to Right trackpad motion - The VM should generate positive deltaY for Bottom to Up trackpad motion For historical reasons, if VM does not send mouse wheel events, but fake keyboard arrow events, then: - The VM should generate a left arrow key for Left to Right trackpad motion - The VM should generate a bottom arrow key for Bottom to Up trackpad motion Not that the preferred direction preference of OSX is taken into account by the VM See https://developer.apple.com/documentation/appkit/nsevent/1525151-isdirectio… Above description is for "natural scrolling" preference (the trackpad does drag the screen contents). It will be inverted if the preference is unset (the trackpad does drag the scroll bar). Note that the `isFlipped` method of the Cocoa/Quartz view presumably ha an impact on sign of vertical motions See https://developer.apple.com/documentation/appkit/nsview/1483532-isflipped OpenSmalltalk VM does use isFlipped YES. View the changeset: https://github.com/OpenSmalltalk/opensmalltalk-vm/compare/9f4fae8b5bca...f2… View the full build log and details: https://travis-ci.org/OpenSmalltalk/opensmalltalk-vm/builds/631316227?utm_m… -- You can unsubscribe from build emails from the OpenSmalltalk/opensmalltalk-vm repository going to https://travis-ci.org/account/preferences/unsubscribe?repository=8795279&ut…. Or unsubscribe from *all* email updating your settings at https://travis-ci.org/account/preferences/unsubscribe?utm_medium=notificati…. Or configure specific recipients for build notifications in your .travis.yml file. See https://docs.travis-ci.com/user/notifications.

1 0

Failed: OpenSmalltalk/opensmalltalk-vm#1901 (Cog - f219b72)
by Travis CI 31 Dec '19

31 Dec '19

Build Update for OpenSmalltalk/opensmalltalk-vm ------------------------------------- Build: #1901 Status: Failed Duration: 59 mins and 38 secs Commit: f219b72 (Cog) Author: Nicolas Cellier Message: Fix the sign of x wheel events in OSX to be inline with "natural scrolling" preference. - The VM should generate positive deltaX for Left to Right trackpad motion - The VM should generate positive deltaY for Bottom to Up trackpad motion For historical reasons, if VM does not send mouse wheel events, but fake keyboard arrow events, then: - The VM should generate a left arrow key for Left to Right trackpad motion - The VM should generate a bottom arrow key for Bottom to Up trackpad motion Not that the preferred direction preference of OSX is taken into account by the VM See https://developer.apple.com/documentation/appkit/nsevent/1525151-isdirectio… Above description is for "natural scrolling" preference (the trackpad does drag the screen contents). It will be inverted if the preference is unset (the trackpad does drag the scroll bar). Note that the `isFlipped` method of the Cocoa/Quartz view presumably ha an impact on sign of vertical motions See https://developer.apple.com/documentation/appkit/nsview/1483532-isflipped OpenSmalltalk VM does use isFlipped YES. View the changeset: https://github.com/OpenSmalltalk/opensmalltalk-vm/compare/9f4fae8b5bca...f2… View the full build log and details: https://travis-ci.org/OpenSmalltalk/opensmalltalk-vm/builds/631316227?utm_m… -- You can unsubscribe from build emails from the OpenSmalltalk/opensmalltalk-vm repository going to https://travis-ci.org/account/preferences/unsubscribe?repository=8795279&ut…. Or unsubscribe from *all* email updating your settings at https://travis-ci.org/account/preferences/unsubscribe?utm_medium=notificati…. Or configure specific recipients for build notifications in your .travis.yml file. See https://docs.travis-ci.com/user/notifications.

1 0

← Newer
1
2
3
4
5
6
7
...
27
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

Vm-dev December 2019