Vm-dev February 2018

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131 discussions

[OpenSmalltalk/opensmalltalk-vm] d77280: Revert "Upgrade to Xcode 8.3.3"
by GitHub 05 Feb '18

05 Feb '18

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: d77280d1e9d4ee6b79a8456b80ff6650d94fce19 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/d77280d1e9d4ee6b79… Author: Fabio Niephaus <code(a)fniephaus.com> Date: 2018-02-05 (Mon, 05 Feb 2018) Changed paths: M .travis.yml Log Message: ----------- Revert "Upgrade to Xcode 8.3.3" This reverts commit cc3aa3dac8379f3f5493dfc40c3b735d8bbf83fa.

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[OpenSmalltalk/opensmalltalk-vm] OpenSSL fails to build on macOS (#208)
by Fabio Niephaus 05 Feb '18

05 Feb '18

I had to clear the build cache and now Travis tries to build OpenSSL from scratch and that is failing repeatedly for some unknown reason ([example build](https://travis-ci.org/OpenSmalltalk/opensmalltalk-vm/jobs/336209100#…). /cc @estebanlm -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/208

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[OpenSmalltalk/opensmalltalk-vm] 522175: Do not grep for errors, silence make instead
by GitHub 05 Feb '18

05 Feb '18

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 522175475191ebe27317770dfc6715a9d1986c6e https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/522175475191ebe273… Author: Fabio Niephaus <code(a)fniephaus.com> Date: 2018-02-05 (Mon, 05 Feb 2018) Changed paths: M build.macos32x86/third-party/Makefile.cairo M build.macos32x86/third-party/Makefile.openssl M build.macos64x64/third-party/Makefile.cairo M build.macos64x64/third-party/Makefile.openssl Log Message: ----------- Do not grep for errors, silence make instead Fixes #208

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Compiling VM on Mac
by Guido Chari 05 Feb '18

05 Feb '18

Hello, I follow the documentation but I was not able to compile the VM. I generated the sources using: 'CogSpur32VMBuilder buildMacOSX32.' Then, I went to the pharo.cog.spur directory and ran 'mvm -A'. The output is the following: clang -x c -MT build/vm/gcc3x-cointerp.o -MMD -MP -MF deps/gcc3x-cointerp.Td -Wno-missing-field-initializers -Wno-missing-prototypes -Wno-missing-braces -Wparentheses -Wswitch -Wno-unused-function -Wno-unused-label -Wno-unused-parameter -Wunused-variable -Wunused-value -Wno-empty-body -Wno-uninitialized -Wno-unknown-pragmas -Wno-shadow -Wno-four-char-constants -Wno-conversion -Wno-constant-conversion -Wno-int-conversion -Wno-bool-conversion -Wno-enum-conversion -Wno-sign-conversion -Wno-shorten-64-to-32 -Wpointer-sign -Wno-newline-eof -Wno-trigraphs -Wdeprecated-declarations -g -Os -DPharoVM=1 -DIMMUTABILITY=1 -DDEBUGVM=0 -DNDEBUG=1 -DPharoVM=1 -DIMMUTABILITY=1 -DUSE_GLOBAL_STRUCT=0 -DNO_ISNAN=1 -DUSE_INLINE_MEMORY_ACCESSORS -D'TZ="-03"' -D'VM_LABEL(foo)=0' -DSQUEAK_BUILTIN_PLUGIN -DBUILD_FOR_OSX=1 -arch i386 -mmacosx-version-min=10.7 -msse4.2 -fvisibility=default -fwrapv -fmacro-backtrace-limit=0 -fdiagnostics-show-note-include-stack -fmessage-length=0 -fpascal-strings -fasm-blocks -fstrict-aliasing -fobjc-weak -isysroot -include ../../platforms/iOS/vm/SqueakPureObjc_Prefix.pch -I. -I../../spursrc/vm -I../../platforms/iOS/vm/Common -I../../platforms/iOS/vm/Common/Classes -I../../platforms/iOS/vm/OSX -I../../platforms/unix/vm -I../../platforms/Cross/vm -I../../platforms/Cross/plugins/FilePlugin -I../../platforms/Cross/plugins/HostWindowPlugin -I../../platforms/Cross/plugins/SoundPlugin -I../../platforms/iOS/plugins/FilePlugin -I../../platforms/iOS/plugins/HostWindowPlugin -I../../platforms/iOS/plugins/SoundPlugin -c ../../spursrc/vm/gcc3x-cointerp.c -o build/vm/gcc3x-cointerp.o clang: *error: *cannot specify -o when generating multiple output files clang: *warning: *no such sysroot directory: '-include' [-Wmissing-sysroot] make: *** [build/vm/gcc3x-cointerp.o] Error 1 I'm running Sierra 10.13.2. Any ideas? Best, Guido.

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Re: [Vm-dev] [OpenSmalltalk/opensmalltalk-vm] adds more dependencies to the CentOS list (#110)
by Fabio Niephaus 05 Feb '18

05 Feb '18

Could you update this PR please, @santana? -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/pull/110#issuecomment-363…

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[CFP] ICOOOLPS 2018
by Tim Felgentreff 05 Feb '18

05 Feb '18

Call for Papers: ICOOOLPS'18 ============================ 13th Workshop on Implementation, Compilation, Optimization of Object- Oriented Languages, Programs and Systems Co-located with ECOOP 2018 held Mon 16 - Sun 22 July in Amsterdam, Netherlands Twitter: @ICOOOLPS URL: https://conf.researchr.org/track/ecoop-issta-2018/ICOOOLPS-2018-papers The ICOOOLPS workshop series brings together researchers and practitioners working in the field of language implementation and optimization. The goal of the workshop is to discuss emerging problems and research directions as well as new solutions to classic performance challenges. The topics of interest for the workshop include techniques for the implementation and optimization of a wide range of languages including but not limited to object-oriented ones. Furthermore, meta-compilation techniques or language-agnostic approaches are welcome, too. ### Topics of Interest A non-exclusive list of topics of interest for this workshop is: - Implementation and optimization of fundamental languages features (from automatic memory management to zero-overhead metaprogramming) - Runtime systems technology (libraries, virtual machines) - Static, adaptive, and speculative optimizations and compiler techniques - Meta-compilation techniques and language-agnostic approaches for the efficient implementation of languages - Compilers (intermediate representations, offline and online optimizations,…) - Empirical studies on language usage, benchmark design, and benchmarking methodology - Resource-sensitive systems (real-time, low power, mobile, cloud) - Studies on design choices and tradeoffs (dynamic vs. static compilation, heuristics vs. programmer input,…) - Tooling support, debuggability and observability of languages as well as their implementations ### Workshop Format and Submissions This workshop welcomes the presentation and discussion of new ideas and emerging problems that give a chance for interaction and exchange. More mature work is welcome as part of a mini-conference format, too. We aim to interleave interactive brainstorming and demonstration sessions between the formal presentations to foster an active exchange of ideas. The workshop papers will be published in ACM DL or an open archive (to be confirmed). Papers are to be submitted using the sigplanconf LaTeX template (http://www.sigplan.org/Resources/LaTeXClassFile/). Please submit contributions via EasyChair: https://easychair.org/conferences/submission_show_all.cgi?a=17114062 ### Important Dates Submissions: 18 May 2018 Author Notification: 8 June 2018 ### Program Committee The program committee consists of the organizers and the following reviewers: Nada Amin, University of Cambridge Clément Béra, RMOD - INRIA Lille Nord Europe Shigeru Chiba, University of Tokyo Benoit Daloze, JKU Linz Görel Hedin, Lund University Eric Jul, University of Oslo Stefan Marr, University of Kent Eliot Miranda, Cadence Design Systems Sarah Mount, King's College London Tobias Pape, Hasso Plattner Institute Jennifer Sartor, Vrije Universiteit Brussel + University Ghent ### Workshop Organizers Tim Felgentreff, Oracle Labs Potsdam Olivier Zendra, INRIA / LORIA

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VM Maker: VMMaker.oscog-eem.2329.mcz
by commits＠source.squeak.org 04 Feb '18

04 Feb '18

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2329.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2329 Author: eem Time: 4 February 2018, 11:52:42.260503 am UUID: 74077530-8ed4-4601-a446-062057eeb3d3 Ancestors: VMMaker.oscog-eem.2328 RegisterAllocatingCogit: Revise merge code generation (& uke the now unneeded failed merge catcher). Have the merge update simStack reflecting reality as the merge proceeds. This update occurs in reconcilePoppingWith: & reconcilePushingWith:. N.B. reconcilePoppingWith: & reconcilePushingWith: are now essentially identical apart from whether they pusgh or pop. They will be merged and the push/pop moved to the client mergeCurrentSimStackWith: very soon. On backward jumps copy the simStackState to the loop head on the first pass and on the second pass have the merge at the loop head preserve as many live registers as possible, not just the live registers arriving from the back jump. Consequently generate two sets of merge code, one from regsiters live at back-jump, one from no live registers after the evebt poll. Make the merge code exchange all registers in the conflict set (in common on both sides, and a pair of current,target exists with live registers that differ). For this, add NumIntegerRegs to the back ends, along with NumFloatRegisters for symmetry. Fix temp offsets in genStorePop:TemporaryVariable: given self now at 0 in simStack. Execution on a suitably interesting boot imnage gets as far as CMMethod 395 CMClosedPIC 36 CMOpenPIC 2 CMFree 0 total 433 until assert fails stop progress. =============== Diff against VMMaker.oscog-eem.2328 =============== Item was changed: ----- Method: CogARMCompiler class>>initializeAbstractRegisters (in category 'class initialization') ----- initializeAbstractRegisters "Assign the abstract registers with the identities/indices of the relevant concrete registers." super initializeAbstractRegisters. "According to IHI0042E ARM Architecture Procedure Calling Standard, in section 5.1.1: A subroutine must preserve the contents of the registers r4-r8, r10, r11 and SP (and r9 in PCS variants that designate r9 as v6). SP = r13, so the callee-saved regs are r4-r8 & r10-r12. The caller-saved registers are those that are not callee-saved and not reserved for hardware/abi uses, i..e r0-r3, r9 & r12. We exclude registers 0 & 1 (TempReg/CArg0Reg & CArg1Reg) from the CallerSavedRegisterMask because we only use them for argument passing and so never want to save and restore them. In fact restoring TempReg/CArg0Reg would overwrite function results, so it shouldn't be included under any circumstances." CallerSavedRegisterMask := self registerMaskFor: "0 and: 1 and:" 2 and: 3 and: 9 and: 12. TempReg := R0. ClassReg := R2. ReceiverResultReg := R5. SendNumArgsReg := R6. SPReg := SP. "a.k.a. R13" self assert: SP = 13. FPReg := R11. Arg0Reg := R3. "overlaps with last C arg reg" Arg1Reg := R4. Extra0Reg := R7. Extra1Reg := R8. Extra2Reg := R9. VarBaseReg := R10. "Must be callee saved" self assert: ConcreteVarBaseReg = R10. RISCTempReg := R12. "a.k.a. IP" self assert: ConcreteIPReg = R12. LinkReg := LR. "R14" PCReg := PC. "R15" + NumRegisters := 16. + DPFPReg0 := D0. DPFPReg1 := D1. DPFPReg2 := D2. DPFPReg3 := D3. DPFPReg4 := D4. DPFPReg5 := D5. DPFPReg6 := D6. + DPFPReg7 := D7. + + NumFloatRegisters := 8! - DPFPReg7 := D7! Item was changed: ----- Method: CogAbstractRegisters class>>initialize (in category 'class initialization') ----- initialize "Define a fixed set of abstract register names used in code generation for Smalltalk code. These are given concrete values by the currently in-use back end, which is a subclass of CogAbstractInstruction; see implementors of initializeAbstractRegisters. We assume concrete registers defined by the back ends are in the range 0 to N, possibly with integer registers and floating-point registers using overlapping ranges of indices. Here we initialize all registers to #undefined, leaving it to initializeAbstractRegisters to initialize the subset of the abstract registers that a platform actually uses." "NoReg encodes no register, e.g. for parameters that supply an optional register. Being negative it is distinct from abstract and concrete registers in the 0 to N range." NoReg := -1. "The core set of abstract registers that define the Cogit's model of Smalltalk code provide for a register-based calling convention oriented towards inline cacheing and executing a core set of machine code primitives in registers. The set is composed of 8 registers, dictated by the available registers on IA32." "Smalltalk machine code executes on stack pages in the stack zone, requiring frame and stack pointers." FPReg := #undefined. "A frame pointer is used for Smalltalk frames." SPReg := #undefined. ReceiverResultReg := #undefined. "The receiver at point of send, and return value of a send" ClassReg := #undefined. "The inline send cache class tag is in this register, loaded at the send site" SendNumArgsReg := #undefined. "Sends > 2 args set the arg count in this reg" Arg0Reg := #undefined. "In the StackToRegisterMappingCogit 1 & 2 arg sends marshall into these registers." Arg1Reg := #undefined. TempReg := #undefined. "A small fixed set of abstract scratch registers for register-rich machines (ARM can use 1, x64 can use 6 or 7)." Extra0Reg := #undefined. Extra1Reg := #undefined. Extra2Reg := #undefined. Extra3Reg := #undefined. Extra4Reg := #undefined. Extra5Reg := #undefined. Extra6Reg := #undefined. Extra7Reg := #undefined. "RISC-specific registers" LinkReg := #undefined. RISCTempReg := #undefined. "Used to synthesize CISC instructions from multiple RISC instructions." PCReg := #undefined. "If the processor has an assignable pc, e.g. ARM" VarBaseReg := #undefined. "If useful, points to base of interpreter variables." + NumRegisters := #undefined. "Number of basic/integer regsiters (we don't do M68k ;-) )" + "Up to 16 floating-point registers. e.g. IA32+SSE2 can use 8, x64 can use 16." DPFPReg0 := #undefined. DPFPReg1 := #undefined. DPFPReg2 := #undefined. DPFPReg3 := #undefined. DPFPReg4 := #undefined. DPFPReg5 := #undefined. DPFPReg6 := #undefined. DPFPReg7 := #undefined. DPFPReg8 := #undefined. DPFPReg9 := #undefined. DPFPReg10 := #undefined. DPFPReg11 := #undefined. DPFPReg12 := #undefined. DPFPReg13 := #undefined. DPFPReg14 := #undefined. + DPFPReg15 := #undefined. + + NumFloatRegisters := #undefined. "Number of floating-point registers (we don;t do single-precision; we don't do xmm high (yet)."! - DPFPReg15 := #undefined! Item was changed: ----- Method: CogIA32Compiler class>>initializeAbstractRegisters (in category 'class initialization') ----- initializeAbstractRegisters "Assign the abstract registers with the identities/indices of the relevant concrete registers." super initializeAbstractRegisters. "N.B. EAX ECX & EDX are caller-save (scratch) registers. Hence we use ECX for class and EDX for receiver/result since these are written in all normal sends. EBX ESI & EDI are callee-save." CallerSavedRegisterMask := self registerMaskFor: EAX and: ECX and: EDX. TempReg := EAX. ClassReg := ECX. ReceiverResultReg := EDX. SendNumArgsReg := EBX. SPReg := ESP. FPReg := EBP. Arg0Reg := ESI. Arg1Reg := EDI. + NumRegisters := 8. + DPFPReg0 := XMM0L. DPFPReg1 := XMM1L. DPFPReg2 := XMM2L. DPFPReg3 := XMM3L. DPFPReg4 := XMM4L. DPFPReg5 := XMM5L. DPFPReg6 := XMM6L. + DPFPReg7 := XMM7L. + + NumFloatRegisters := 8! - DPFPReg7 := XMM7L! Item was changed: ----- Method: CogMIPSELCompiler class>>initializeAbstractRegisters (in category 'class initialization') ----- initializeAbstractRegisters "Assign the abstract registers with the identities/indices of the relevant concrete registers." "See MIPSConstants>>initializeRegisters for a description of the C ABI." "Note we can fit all of the abstract registers in C preserved registers, and not need to save or restore them at runtime calls." super initializeAbstractRegisters. self flag: #OABI. CallerSavedRegisterMask := self registerMaskFor: T0 and: T1 and: T2 and: T3 and: T4 and: T5 and: T6 and: T7 and: T8 and: T9. ReceiverResultReg := S0. Arg0Reg := S1. Arg1Reg := S2. ClassReg := S3. SendNumArgsReg := S4. TempReg := S5. VarBaseReg := S6. "Must be callee saved" SPReg := SP. FPReg := FP. RISCTempReg := AT. LinkReg := RA. + NumRegisters := 32 + self flag: #todo. "Extra0Reg := ??. Extra1Reg := ??. Extra2Reg := ??. Extra3Reg := ??. Extra4Reg := ??. Extra5Reg := ??. Extra6Reg := ??. Extra7Reg := ??." self flag: #todo. "DPFPReg0 := ??. DPFPReg1 := ??. DPFPReg2 := ??. DPFPReg3 := ??. DPFPReg4 := ??. DPFPReg5 := ??. DPFPReg6 := ??. DPFPReg7 := ??. DPFPReg8 := ??. DPFPReg9 := ??. DPFPReg10 := ??. DPFPReg11 := ??. DPFPReg12 := ??. DPFPReg13 := ??. DPFPReg14 := ??. DPFPReg15 := ??"! Item was added: + ----- Method: CogRASSBytecodeFixup>>simStackPrintString (in category 'debug printing') ----- + simStackPrintString + <doNotGenerate> + ^String streamContents: + [:s| + self notAFixup + ifTrue: [s nextPutAll: 'notAFixup'] + ifFalse: [cogit printSimStack: mergeSimStack toDepth: simStackPtr spillBase: -1 on: s]]! Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>ensureSpilledAt:from: (in category 'compile abstract instructions') ----- ensureSpilledAt: baseOffset from: baseRegister spilled ifTrue: [type = SSSpill ifTrue: [self assert: ((offset = baseOffset and: [register = baseRegister]) or: [cogit violatesEnsureSpilledSpillAssert]). liveRegister := NoReg. ^self]]. self assert: type ~= SSSpill. cogit traceSpill: self. + "N.B. Keep the type of SSConstant spills as SSConstant so that when joins occur + as a result of expressions with constants on the stack, the constant on stack + can be recovered. e.g. as in + self at: 1 put: (self foo ifTrue: [self bar] ifFalse: [self baz])." type = SSConstant ifTrue: [cogit genPushConstant: constant] ifFalse: [type = SSBaseOffset ifTrue: [liveRegister = NoReg ifTrue: [cogit MoveMw: offset r: register R: TempReg. cogit PushR: TempReg] ifFalse: [cogit PushR: liveRegister]] ifFalse: [self assert: type = SSRegister. cogit PushR: register]. + type := SSSpill]. - type := SSSpill. - offset := baseOffset. - register := baseRegister]. liveRegister := NoReg. + spilled := true. + offset := baseOffset. + register := baseRegister! - spilled := true! Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>isMergedWithTargetEntry: (in category 'comparing') ----- isMergedWithTargetEntry: targetEntry "The receiver is a simStackEntry at a jump to the corresponding simStackEntry at the jump's target. Answer if no merge is required for the jump." <var: 'ssEntry' type: #'CogSimStackEntry *'> spilled ~= targetEntry spilled ifTrue: "push or pop required" [^false]. (liveRegister = NoReg and: [targetEntry liveRegister ~= NoReg]) ifTrue: "register load required" [^false]. (self isSameEntryAs: targetEntry) ifTrue: [^liveRegister = targetEntry liveRegister]. (type = SSConstant and: [targetEntry type = SSRegister and: [liveRegister = targetEntry register]]) ifTrue: [^true]. "self: const =1 (16r1) (live: Extra4Reg) {172} vs reg ReceiverResultReg {127}" "self: reg ReceiverResultReg {95} vs reg Extra5Reg {85}" + "self: (bo ReceiverResultReg+296 (live: Extra5Reg) {88} vs reg ReceiverResultReg {84}" + "self: const =1 (16r1) (spilled) {167} vs spill @ FPReg-48 {122}" - "(bo ReceiverResultReg+296 (live: Extra5Reg) {88} vs reg ReceiverResultReg {84}" ((type = SSConstant and: [targetEntry type = SSRegister and: [liveRegister ~= targetEntry registerOrNone]]) or: [(type = SSRegister and: [targetEntry type = SSRegister and: [register ~= targetEntry registerOrNone]]) + or: [(type = SSBaseOffset and: [register = ReceiverResultReg and: [targetEntry type = SSRegister]]) + or: [(type = SSConstant and: [targetEntry type = SSSpill])]]]) ifFalse: - or: [type = SSBaseOffset and: [register = ReceiverResultReg and: [targetEntry type = SSRegister]]]]) ifFalse: [self halt: 'comment the incompatible pair please']. ^false! Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>reconcilePoppingWith: (in category 'compile abstract instructions') ----- reconcilePoppingWith: targetEntry "Make the state of a targetEntry, a stack entry following a non-inlined special selector send, the same as the corresponding entry (the receiver) along the inlined path." <var: #targetEntry type: #'SimStackEntry *'> | targetReg | spilled = targetEntry spilled ifTrue: [self assert: ((self isSameEntryAs: targetEntry) + or: [(targetEntry spilled not and: [targetEntry registerOrNone ~= NoReg]) + or: [spilled and: [type = SSConstant and: [offset = targetEntry offset]]]]). - or: [targetEntry spilled not and: [targetEntry registerOrNone ~= NoReg]]). (targetReg := targetEntry registerOrNone) = NoReg ifTrue: + [liveRegister := NoReg. + ^self]. - [^self]. type caseOf: { + [SSBaseOffset] -> [liveRegister ~= targetReg ifTrue: + [cogit MoveMw: offset r: register R: targetReg]. + targetEntry type caseOf: { + [SSBaseOffset] -> [liveRegister := targetReg. + (self isSameEntryAs: targetEntry) ifFalse: + [type := SSSpill]]. + [SSSpill] -> [liveRegister := targetReg. type := SSSpill]. + [SSConstant] -> [liveRegister := targetReg. type := SSSpill]. + [SSRegister] -> [register := targetReg. type := SSRegister] }]. + [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg. + liveRegister := targetReg]. + [SSConstant] -> [cogit genMoveConstant: constant R: targetReg. + type := SSRegister. register := targetReg]. + [SSRegister] -> [targetReg ~= register ifTrue: + [cogit MoveR: register R: targetReg. + register := targetReg]] }. - [SSBaseOffset] -> [cogit MoveMw: offset r: register R: targetReg]. - [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg]. - [SSConstant] -> [cogit genMoveConstant: constant R: targetReg]. - [SSRegister] -> [targetReg ~= register ifTrue: - [cogit MoveR: register R: targetReg]] }. ^self]. self assert: spilled. + (targetReg := targetEntry registerOrNone) ~= NoReg - (targetEntry type ~= SSConstant - and: [(targetReg := targetEntry registerOrNone) ~= NoReg]) ifTrue: [cogit PopR: targetReg] + ifFalse: [cogit AddCq: objectRepresentation wordSize R: SPReg]. + liveRegister ~= targetReg ifTrue: + [liveRegister := NoReg]! - ifFalse: [cogit AddCq: objectRepresentation wordSize R: SPReg]! Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>reconcilePushingWith: (in category 'compile abstract instructions') ----- reconcilePushingWith: targetEntry "Make the state of the receiver, a stack entry at the end of a basic block, the same as the corresponding simStackEntry at the target of a preceding jump to the beginning of the next basic block. Make sure targetEntry reflects the state of the merged simStack; it will be installed as the current + entry by restoreSimStackAtMergePoint: in mergeWithFixupIfRequired:." - entry by restoreSimStackAtMergePoint: in mergeWithFixupIfRequired:. - - Answer if the liveRegister for the targetEntry (if any) should be deassigned; - this is because if merging a non-temp with a temp that has a live register we - can assign to the register, but must unassign the register from the temp, - otherwise the temp will acquire the merged value without an assignment." <var: #targetEntry type: #'SimStackEntry *'> | targetReg | + spilled = targetEntry spilled ifTrue: + [self assert: ((self isSameEntryAs: targetEntry) + or: [(targetEntry spilled not and: [targetEntry registerOrNone ~= NoReg]) + or: [spilled and: [type = SSConstant and: [offset = targetEntry offset]]]]). + (targetReg := targetEntry registerOrNone) = NoReg ifTrue: + [liveRegister := NoReg. + ^self]. + type caseOf: { + [SSBaseOffset] -> [liveRegister ~= targetReg ifTrue: + [cogit MoveMw: offset r: register R: targetReg]. + targetEntry type caseOf: { + [SSBaseOffset] -> [liveRegister := targetReg. + (self isSameEntryAs: targetEntry) ifFalse: + [type := SSSpill]]. + [SSSpill] -> [liveRegister := targetReg. type := SSSpill]. + [SSConstant] -> [liveRegister := targetReg. type := SSSpill]. + [SSRegister] -> [register := targetReg. type := SSRegister] }]. + [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg. + liveRegister := targetReg]. + [SSConstant] -> [cogit genMoveConstant: constant R: targetReg. + type := SSRegister. register := targetReg]. + [SSRegister] -> [targetReg ~= register ifTrue: + [cogit MoveR: register R: targetReg. + register := targetReg]] }. + ^self]. + self assert: spilled. + (targetReg := targetEntry registerOrNone) ~= NoReg + ifTrue: [cogit PopR: targetReg] + ifFalse: [cogit AddCq: objectRepresentation wordSize R: SPReg]. + liveRegister ~= targetReg ifTrue: + [liveRegister := NoReg]! - (targetReg := targetEntry registerOrNone) = NoReg ifTrue: - [| reg | - self assert: targetEntry spilled. - (self isSameEntryAs: targetEntry) ifTrue: - [self assert: spilled. - ^false]. - (reg := self registerOrNone) = NoReg ifTrue: [reg := TempReg]. - self storeToReg: reg. - spilled - ifTrue: [cogit MoveR: reg Mw: targetEntry offset r: targetEntry register] - ifFalse: [cogit PushR: reg]. - ^false]. - liveRegister ~= NoReg ifTrue: - [liveRegister ~= targetReg ifTrue: - [cogit MoveR: liveRegister R: targetReg]. - (spilled and: [targetEntry spilled not]) ifTrue: - [cogit AddCq: objectRepresentation wordSize R: SPReg]. - ^false]. - spilled - ifTrue: - [targetEntry spilled ifFalse: - [cogit PopR: targetReg. "KISS; generate the least number of instructions..." - ^false]] - ifFalse: - [targetEntry spilled ifTrue: - [cogit SubCq: objectRepresentation wordSize R: SPReg]]. - type caseOf: { - [SSBaseOffset] -> [cogit MoveMw: offset r: register R: targetReg]. - [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg]. - [SSConstant] -> [cogit genMoveConstant: constant R: targetReg]. - [SSRegister] -> [register ~= targetReg ifTrue: - [cogit MoveR: register R: targetReg]] }. - (targetEntry type = SSConstant - and: [type ~= SSConstant or: [constant ~= targetEntry constant]]) ifTrue: - [targetEntry - register: targetReg; - type: SSRegister]. - "If merging a constant with a constant assigned to a register, then the register must be deassigned from any temps." - ^targetEntry type = SSConstant - "If merging a non-temp with a temp that has a live register we can assign - to the register, but must unassign the register from the temp, otherwise - the temp will acquire the merged value without an assignment." - or: [targetEntry isFrameTempVar and: [(self isSameEntryAs: targetEntry) not]]! Item was changed: ----- Method: CogX64Compiler class>>initializeAbstractRegisters (in category 'class initialization') ----- initializeAbstractRegisters "Assign the abstract registers with the identities/indices of the relevant concrete registers." "[1] Figure 3.4 Register Usage in System V Application Binary Interface AMD64 Architecture Processor Supplement" super initializeAbstractRegisters. "N.B. RAX RCX & RDX are caller-save (scratch) registers. Hence we use RCX for class and RDX for receiver/result since these are written in all normal sends." SysV ifTrue: [self initializeAbstractRegistersSysV] ifFalse: [self initializeAbstractRegistersWin64]. + NumRegisters := 16. + DPFPReg0 := XMM0L. DPFPReg1 := XMM1L. DPFPReg2 := XMM2L. DPFPReg3 := XMM3L. DPFPReg4 := XMM4L. DPFPReg5 := XMM5L. DPFPReg6 := XMM6L. DPFPReg7 := XMM7L. DPFPReg8 := XMM8L. DPFPReg9 := XMM9L. DPFPReg10 := XMM10L. DPFPReg11 := XMM11L. DPFPReg12 := XMM12L. DPFPReg13 := XMM13L. DPFPReg14 := XMM14L. + DPFPReg15 := XMM15L. + + NumFloatRegisters := 16! - DPFPReg15 := XMM15L! Item was changed: ----- Method: Cogit>>maybeHaltIfDebugPC (in category 'compile abstract instructions') ----- maybeHaltIfDebugPC <cmacro: '() 0'> "Simulation only; void in C" ((debugBytecodePointers includes: bytecodePC) and: [breakMethod isNil or: [methodObj = breakMethod]]) ifTrue: + [self halt: ' at bcpc ', bytecodePC printString, '/', (bytecodePC + 1) printString]! - [self halt]! Item was changed: ----- Method: RegisterAllocatingCogit>>assertCorrectSimStackPtr (in category 'compile abstract instructions') ----- assertCorrectSimStackPtr + <inline: true> "generates nothing anyway" "self simStackPrintString" - <inline: true> "generates nothing anyway" self cCode: '' inSmalltalk: [deadCode ifFalse: [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) = (self debugStackPointerFor: bytecodePC)]. + self deny: self duplicateRegisterAssignmentsInTemporaries]! - self deny: self duplicateRegisterAssignmentsInTemporaries]. - ! Item was changed: ----- Method: RegisterAllocatingCogit>>compileAbstractInstructionsFrom:through: (in category 'compile abstract instructions') ----- compileAbstractInstructionsFrom: start through: end "Loop over bytecodes, dispatching to the generator for each bytecode, handling fixups in due course. Override to provide a development-time only escape for failed merges due to partially implemented parallel move. Override to recompile after a loop requiring a merge is detected." + | result initialOpcodeIndex initialCounterIndex initialIndexOfIRC | + compilationPass := 1. + scratchBytecodePC := nil. + initialOpcodeIndex := opcodeIndex. + initialCounterIndex := self maybeCounterIndex."for SistaCogit" + literalsManager saveForRecompile. + NewspeakVM ifTrue: + [initialIndexOfIRC := indexOfIRC]. + [recompileForLoopRegisterAssignments := false. + result := super compileAbstractInstructionsFrom: start through: end. + result = 0 and: [recompileForLoopRegisterAssignments]] - ^[| result initialOpcodeIndex initialCounterIndex initialIndexOfIRC | - compilationPass := 1. - scratchBytecodePC := nil. - initialOpcodeIndex := opcodeIndex. - initialCounterIndex := self maybeCounterIndex."for SistaCogit" - literalsManager saveForRecompile. - NewspeakVM ifTrue: - [initialIndexOfIRC := indexOfIRC]. - [recompileForLoopRegisterAssignments := false. - result := super compileAbstractInstructionsFrom: start through: end. - result = 0 and: [recompileForLoopRegisterAssignments]] whileTrue: [self assert: compilationPass <= 2. self reinitializeAllButBackwardFixupsFrom: start through: end. self resetSimStack: start. self reinitializeOpcodesFrom: initialOpcodeIndex to: opcodeIndex - 1. compilationPass := compilationPass + 1. nextFixup := 0. opcodeIndex := initialOpcodeIndex. self maybeSetCounterIndex: initialCounterIndex. "For SistaCogit" literalsManager resetForRecompile. NewspeakVM ifTrue: [indexOfIRC := initialIndexOfIRC]]. + ^result! - result] - on: Notification - do: [:ex| - ex tag == #failedMerge ifTrue: - [coInterpreter transcript - ensureCr; nextPutAll: 'FAILED MERGE IN '; - nextPutAll: (coInterpreter nameOfClass: (coInterpreter methodClassOf: methodObj)); - nextPutAll: '>>#'; nextPutAll: (coInterpreter stringOf: (coInterpreter maybeSelectorOfMethod: methodObj)); - flush. - ^ShouldNotJIT]. - ex pass]! Item was changed: ----- Method: RegisterAllocatingCogit>>conflictsResolvedBetweenSimStackAnd: (in category 'bytecode generator support') ----- conflictsResolvedBetweenSimStackAnd: mergeSimStack "There are no register conflicts between simStack and mergeSimStack if traversing both stacks from hot end (simStackPtr) to cold end (0) no register exists in simStack that has previously existed in mergeSimStack. This is because the resolution assigns values from simStack to registers in mergeSimStack and so must not assign to a register yet to be read." | regsWrittenToMask | regsWrittenToMask := 0. simStackPtr to: 0 by: -1 do: [:i| | mergeMask currentMask | mergeMask := (self simStack: mergeSimStack at: i) registerMaskOrNone. currentMask := (self simStack: simStack at: i) registerMaskOrNone. + "Ignore targets with no registers. Current's register can be deassigned and so there's no conflict." + (mergeMask ~= 0 and: [mergeMask ~= currentMask]) ifTrue: - mergeMask ~= currentMask ifTrue: [(currentMask anyMask: regsWrittenToMask) ifTrue: [^false]]. regsWrittenToMask := regsWrittenToMask bitOr: mergeMask]. ^true! Item was added: + ----- Method: RegisterAllocatingCogit>>copySimStackToFixup: (in category 'bytecode generator support') ----- + copySimStackToFixup: fixup + <var: #fixup type: #'BytecodeFixup *'> + <inline: true> + self cCode: [self mem: fixup mergeSimStack cp: simStack y: simStackPtr + 1 * (self sizeof: CogSimStackEntry)] + inSmalltalk: [0 to: simStackPtr do: + [:i| + fixup mergeSimStack at: i put: (simStack at: i) copy]]! Item was changed: ----- Method: RegisterAllocatingCogit>>ensureRegisterAssignmentsAreAtHeadOfLoop: (in category 'bytecode generator support') ----- ensureRegisterAssignmentsAreAtHeadOfLoop: target "Compiling a loop body will compute a set of live registers. The backward branch must merge with the head of the loop. So it is preferrable to make the register assignments at the end of the loop available at the head. To do this, simply copy the register assignments to the loop head's fixup in the first compilation pass and schedule a second compilation pass. On the second pass the merge will occur when encountering the fixup for the loop head, using exactly the same code as for a merge at the end of an if." | conflictingRegsMask | compilationPass > 1 ifTrue: + [self assert: (target mergeSimStack notNil). - ["self deny: (self mergeRequiredToTarget: target mergeSimStack)." - self assert: (target mergeSimStack isNil or: [self simStack: simStack isIdenticalTo: target mergeSimStack]). ^self]. (self mergeRequiredToTarget: target mergeSimStack) ifFalse: [^self]. "Schedule a recompile and merge the end-of-loop assignments into the head of the loop, replacing any and all register assignments with the state as of the back jump. Because typically the back jump will be taken much more often than the loop entered, favouring the assignments here is more efficient than trying to merge." recompileForLoopRegisterAssignments := true. conflictingRegsMask := self conflictingRegistersBetweenSimStackAnd: target mergeSimStack. self deny: (self register: FPReg isInMask: conflictingRegsMask). 0 to: simStackPtr do: [:i| | currentEntry targetEntry | currentEntry := self simStack: simStack at: i. targetEntry := self simStack: target mergeSimStack at: i. targetEntry liveRegister: currentEntry liveRegister]! Item was changed: ----- Method: RegisterAllocatingCogit>>genJumpBackTo: (in category 'bytecode generator support') ----- genJumpBackTo: targetPC | target | "On first pass install register allocations (if any) as of the end of the loop and back up to recompile. One the second pass generate (any merge other than self elided because register assignments copied to loop head in first pass) cmp stackLimit maybe reload self jumpAboveOrEqual target flush checkForInterrupts merge from flushed (N.B. If stack was flushed before loop we could conceivably jump to the pre-loop merge code) jmp target self printSimStack; printSimStack: target mergeSimStack" self assert: targetPC < bytecodePC. target := self fixupAt: targetPC. self ensureRegisterAssignmentsAreAtHeadOfLoop: target. + self copySimStackToScratch: simSpillBase. + self mergeCurrentSimStackWith: target. self MoveAw: coInterpreter stackLimitAddress R: TempReg. self CmpR: TempReg R: SPReg. "N.B. FLAGS := SPReg - TempReg" self JumpAboveOrEqual: target. self ssFlushTo: simStackPtr. self CallRT: ceCheckForInterruptTrampoline. self annotateBytecode: self Label. + self restoreSimStackFromScratch. self flushLiveRegistersForSuspensionPoint. + self mergeCurrentSimStackWith: target. - self mergeCurrentSimStackWith: target forwards: false. self Jump: target. deadCode := true. "can't fall through" ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>genStorePop:TemporaryVariable: (in category 'bytecode generator support') ----- genStorePop: popBoolean TemporaryVariable: tempIndex <inline: false> | top srcRegOrNone destReg | self deny: self duplicateRegisterAssignmentsInTemporaries. self ssFlushUpThroughTemporaryVariable: tempIndex. "To avoid a stall writing through destReg, remember srcReg before the potential ssPop: 1 in ssStorePop:toReg:" top := self ssTop. srcRegOrNone := top registerOrNone. "ssStorePop:toPreferredReg: will allocate a register, and indeed may allocate ReceiverResultReg if, for example, the ssEntry to be popped is already in ReceiverResultReg (as the result of a send). ReceiverResultReg is not a good choice for a temporary variable; it has other uses. So if the ssEntry at top of stack has ReceiverResultReg as its live variable, try and allocate an alternative." + destReg := (self simStackAt: tempIndex + 1) liveRegister. - destReg := (self simStackAt: tempIndex) liveRegister. destReg ~= NoReg ifTrue: [self ssStorePop: popBoolean toReg: destReg] ifFalse: [((top type = SSConstant or: [srcRegOrNone = NoReg or: [self register: srcRegOrNone isInMask: self registerMaskUndesirableForTempVars]]) and: [(destReg := self availableRegOrNoneNotConflictingWith: (self registerMaskUndesirableForTempVars bitOr: self liveRegisters)) ~= NoReg]) ifTrue: [self ssStorePop: popBoolean toReg: destReg] ifFalse: [destReg := self ssStorePop: popBoolean toPreferredReg: TempReg]. "The ssStorePop: may end up assigning a register to ssTop, and if it is also a temp then a new register must be found for the destination temp, sicne two temp vars can't share a register." (top isFrameTempVar and: [top liveRegister = destReg]) ifTrue: [srcRegOrNone := destReg. destReg := self availableRegOrNoneNotConflictingWith: (self registerMaskUndesirableForTempVars bitOr: self liveRegisters). destReg ~= NoReg ifTrue: [self MoveR: srcRegOrNone R: destReg]]. (destReg ~= NoReg and: [destReg ~= TempReg]) ifTrue: + [(self simStackAt: tempIndex + 1) liveRegister: destReg. + self copyLiveRegisterToCopiesOf: (self simStackAt: tempIndex + 1)]]. - [(self simStackAt: tempIndex) liveRegister: destReg. - self copyLiveRegisterToCopiesOf: (self simStackAt: tempIndex)]]. self MoveR: (srcRegOrNone ~= NoReg ifTrue: [srcRegOrNone] ifFalse: [destReg]) Mw: (self frameOffsetOfTemporary: tempIndex) r: FPReg. + (self simStackAt: tempIndex + 1) bcptr: bytecodePC. "for debugging" - (self simStackAt: tempIndex) bcptr: bytecodePC. "for debugging" self deny: self duplicateRegisterAssignmentsInTemporaries. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>liveRegistersExceptingTopNItems:in: (in category 'simulation stack') ----- liveRegistersExceptingTopNItems: n in: aSimStack <var: 'aSimStack' type: #'SimStackEntry *'> + ^self liveRegistersFrom: 0 to: simStackPtr - n in: aSimStack! - | regsSet | - regsSet := 0. - 0 to: simStackPtr - n do: - [:i| - regsSet := regsSet bitOr: (self simStack: aSimStack at: i) registerMask]. - LowcodeVM ifTrue: - [self shouldBeImplemented. - (simNativeSpillBase max: 0) to: simNativeStackPtr - n do: - [:i| - regsSet := regsSet bitOr: (self simNativeStackAt: i) nativeRegisterMask]]. - ^regsSet! Item was added: + ----- Method: RegisterAllocatingCogit>>liveRegistersFrom:to:in: (in category 'simulation stack') ----- + liveRegistersFrom: low to: high in: aSimStack + <var: 'aSimStack' type: #'SimStackEntry *'> + <inline: true> + | regsSet | + regsSet := 0. + low to: high do: + [:i| + regsSet := regsSet bitOr: (self simStack: aSimStack at: i) registerMask]. + ^regsSet! Item was added: + ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith: (in category 'bytecode generator support') ----- + mergeCurrentSimStackWith: fixup + "At a merge point the cogit expects the stack to be in the same state as fixup's mergeSimStack. + mergeSimStack is the state as of some jump forward or backward to this point. So make + simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values + may have to be assigned to registers. Registers may have to be swapped. + Generate code to merge the current simStack with that of the target fixup, the goal being to + keep as many registers live as possible." + "self printSimStack; printSimStack: fixup mergeSimStack" + "self simStackPrintString-> fixup simStackPrintString" + "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" + <var: #fixup type: #'BytecodeFixup *'> + | currentRegisters targetRegisters mergeSimStack current target | + (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. + self assert: simStackPtr = fixup simStackPtr. + currentRegisters := self liveRegistersFrom: 0 to: simStackPtr in: simStack. + targetRegisters := self liveRegistersFrom: 0 to: simStackPtr in: mergeSimStack. + self resolveConflicts: (currentRegisters bitAnd: targetRegisters) with: fixup mergeSimStack to: fixup simStackPtr. + self assert: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack). + "if we simply compare spill bases it is trivial here to decide whether to push or pop. + Otherwise we have to determine the spill base in fixup's mergeSimStack." + (self pushForMergeWith: mergeSimStack) + ifTrue: + [0 to: simStackPtr do: + [:i| + current := self simStack: simStack at: i. + target := self simStack: mergeSimStack at: i. + current reconcilePushingWith: target]] + ifFalse: + [simStackPtr to: 0 by: -1 do: + [:i| + current := self simStack: simStack at: i. + target := self simStack: mergeSimStack at: i. + current reconcilePoppingWith: target]]. + self assertCorrectSimStackPtr! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeWithFixupIfRequired: (in category 'simulation stack') ----- mergeWithFixupIfRequired: fixup "If this bytecode has a fixup, some kind of merge needs to be done. There are 4 cases: 1) the bytecode has no fixup (fixup isNotAFixup) do nothing 2) the bytecode has a non merge fixup the fixup has needsNonMergeFixup. The code generating non merge fixup (currently only special selector code) is responsible for the merge so no need to do it. We set deadCode to false as the instruction can be reached from jumps. 3) the bytecode has a merge fixup, but execution flow *cannot* fall through to the merge point. the fixup has needsMergeFixup and deadCode = true. ignores the current simStack as it does not mean anything restores the simStack to the state the jumps to the merge point expects it to be. 4) the bytecode has a merge fixup and execution flow *can* fall through to the merge point. the fixup has needsMergeFixup and deadCode = false. Merge the state into the fixup's state via mergeCurrentSimStackWith:forwards:. In addition, if this is a backjump merge point, we patch the fixup to hold the current simStackPtr for later assertions. self printSimStack: fixup mergeSimStack" <var: #fixup type: #'BytecodeFixup *'> + deadCode ifFalse: + [self assertCorrectSimStackPtr]. - self deny: self duplicateRegisterAssignmentsInTemporaries. "case 1" + fixup notAFixup ifTrue: + [^0]. - fixup notAFixup ifTrue: [^0]. "case 2" fixup isNonMergeFixup ifTrue: [deadCode ifTrue: [self deny: fixup simStackPtr isNil. simStackPtr := fixup simStackPtr. self restoreSimStackAtMergePoint: fixup. + deadCode := false. + self assertCorrectSimStackPtr] - deadCode := false] ifFalse: [self flushRegistersOnlyLiveOnFallThrough: fixup]. ^0]. "cases 3 and 4" self assert: fixup isMergeFixup. self traceMerge: fixup. deadCode + ifTrue: "case 3" + [simStackPtr := fixup simStackPtr. + self restoreSimStackAtMergePoint: fixup. + deadCode := false.] + ifFalse: "case 4" + [(fixup isBackwardBranchFixup and: [compilationPass > 1]) + ifTrue: + [fixup simStackPtr: simStackPtr. + self mergeCurrentSimStackWith: fixup. + self copySimStackToFixup: fixup] + ifFalse: + [self mergeCurrentSimStackWith: fixup]]. - ifTrue: [simStackPtr := fixup simStackPtr] "case 3" - ifFalse: [(fixup isBackwardBranchFixup and: [compilationPass > 1]) ifTrue: - [fixup simStackPtr: simStackPtr]. - self mergeCurrentSimStackWith: fixup forwards: true]. "case 4" "cases 3 and 4" - deadCode := false. fixup isBackwardBranchFixup ifTrue: + [fixup mergeSimStack ifNil: + [self assert: compilationPass = 1. + self setMergeSimStackOf: fixup]]. - [self assert: fixup mergeSimStack isNil == (compilationPass = 1). - fixup mergeSimStack ifNil: - [self setMergeSimStackOf: fixup]]. fixup targetInstruction: self Label. + self assertCorrectSimStackPtr. + self assert: (self simStackMergeCompatibleWith: fixup). + "self simStackPrintString""fixup simStackPrintString" - self assert: simStackPtr = fixup simStackPtr. - self cCode: '' inSmalltalk: - [self assert: fixup simStackPtr = (self debugStackPointerFor: bytecodePC)]. - self restoreSimStackAtMergePoint: fixup. - ^0! Item was added: + ----- Method: RegisterAllocatingCogit>>resolveConflicts:with:to: (in category 'bytecode generator support') ----- + resolveConflicts: registersInCommon with: mergeSimStack to: simStackPtr + "registersInCommon is the register mask of registers in use in both the current + simStack and the target mergeSimStack. Swap any and all conflicting register uses + in registersInCommon, until register uses in simStack agree with mergeSimStack." + | registerLocations visited | + "registerLocations records where a register has moved to + during an exchange. This allows a single pass of the stack + to rename registers, instead of 1/2 N^2; max stack ~ 56" + <var: 'registerLocations' declareC: 'int registerLocations[NumRegisters]'> + registersInCommon = (self registerMaskFor: FPReg) ifTrue: + [^self]. + self cCode: '' inSmalltalk: + [registerLocations := CArrayAccessor on: (Array new: NumRegisters)]. + 0 to: NumRegisters - 1 do: + [:i| registerLocations at: i put: i]. + visited := 0. + 0 to: simStackPtr do: + [:i| | currentReg targetReg | + currentReg := (self simStackAt: i) registerOrNone. + targetReg := (self simStack: mergeSimStack at: i) registerOrNone. + (currentReg ~= NoReg + and: [targetReg ~= NoReg]) ifTrue: + [currentReg := registerLocations at: currentReg. + (currentReg ~= targetReg + and: [(self register: currentReg isInMask: registersInCommon) + and: [(self register: currentReg isNotInMask: visited)]]) ifTrue: + [visited := visited + (self registerMaskFor: currentReg). + self SwapR: targetReg R: currentReg Scratch: RISCTempReg. + registerLocations + at: currentReg put: targetReg; + at: targetReg put: currentReg]]]. + visited = 0 ifTrue: + [^self]. + 0 to: simStackPtr do: + [:i| | ssEntry reg | + ssEntry := self simStackAt: i. + reg := ssEntry registerOrNone. + (reg ~= NoReg + and: [(self register: reg isInMask: registersInCommon) + and: [reg ~= (self simStack: mergeSimStack at: i) registerOrNone]]) ifTrue: + [ssEntry type = SSRegister + ifTrue: [ssEntry register: (registerLocations at: reg)] + ifFalse: [ssEntry liveRegister: (registerLocations at: reg)]]]! Item was changed: ----- Method: RegisterAllocatingCogit>>restoreSimStackAtMergePoint: (in category 'simulation stack') ----- restoreSimStackAtMergePoint: fixup <inline: true> "All the execution paths reaching a merge point expect everything to be spilled on stack and the optStatus is unknown. If the merge point follows a return, it isn't a merge, but a skip past a return. If it is a real merge point then throw + away all simStack optimization state." - away all simStack and optStatus optimization state." fixup mergeSimStack ifNotNil: [simSpillBase := methodOrBlockNumTemps + 1. 0 to: simStackPtr do: [:i| self cCode: [simStack at: i put: (fixup mergeSimStack at: i)] inSmalltalk: [(simStack at: i) copyFrom: (fixup mergeSimStack at: i)]]]. ^0! Item was added: + ----- Method: RegisterAllocatingCogit>>simStackMergeCompatibleWith: (in category 'bytecode generator support') ----- + simStackMergeCompatibleWith: fixup + simStackPtr = fixup simStackPtr ifFalse: + [^false]. + simStackPtr to: 0 by: -1 do: + [:i| | target current | + target := self simStack: fixup mergeSimStack at: i. + current := self simStack: simStack at: i. + (target isSameEntryAs: current) ifFalse: + [^current type caseOf: { + [SSBaseOffset] -> [target type caseOf: { + [SSBaseOffset] -> [false]. + [SSSpill] -> [false]. + [SSConstant] -> [false]. + [SSRegister] -> [false] }]. + [SSSpill] -> [target type caseOf: { + [SSBaseOffset] -> [true]. + [SSSpill] -> [true]. + [SSConstant] -> [true]. + [SSRegister] -> [true] }]. + [SSConstant] -> [target type caseOf: { + [SSBaseOffset] -> [false]. + [SSSpill] -> [false]. + [SSConstant] -> [current constant = target constant]. + [SSRegister] -> [false] }]. + [SSRegister] -> [target type caseOf: { + [SSBaseOffset] -> [current register = target liveRegister]. + [SSSpill] -> [current register = target liveRegister]. + [SSConstant] -> [current register = target liveRegister]. + [SSRegister] -> [current register = target register] }] }]]. + ^true! Item was added: + ----- Method: RegisterAllocatingCogit>>simStackSameAs: (in category 'bytecode generator support') ----- + simStackSameAs: fixup + "There are no register conflicts between simStack and mergeSimStack if + traversing both stacks from hot end (simStackPtr) to cold end (0) no register + exists in simStack that has previously existed in mergeSimStack. This is because + the resolution assigns values from simStack to registers in mergeSimStack and so + must not assign to a register yet to be read." + | | + simStackPtr = fixup simStackPtr ifFalse: + [^false]. + simStackPtr to: 0 by: -1 do: + [:i| | target | + target := self simStack: fixup mergeSimStack at: i. + (target isSameEntryAs: (self simStack: simStack at: i)) ifFalse: + [^false]]. + ^true! Item was added: + ----- Method: SimpleStackBasedCogit>>register:isNotInMask: (in category 'simulation stack') ----- + register: reg isNotInMask: mask + <inline: true> + ^ mask noMask: (self registerMaskFor: reg)!

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Re: [Vm-dev] [Pharo-dev] Change Pharo window icon
by Eliot Miranda 02 Feb '18

02 Feb '18

Hi Stef, On Fri, Feb 2, 2018 at 11:32 AM, Stephane Ducasse <stepharo.self(a)gmail.com> wrote: > Would it be possible to change the icon without having to compile a new VM? > Through an AppleScript: e.g. https://www.sethvargo.com/replace-icons-osx/ > To me the current setup looks so monolithic and dated. > I would expect that somebody can deploy a application with its own > logo by just providing some new resources. > And that's indeed possible. Take the .app bundle and change the .icns file as described above. > > Stef > > On Wed, Jan 31, 2018 at 11:17 PM, Eliot Miranda <eliot.miranda(a)gmail.com> > wrote: > > Hi Vincent, > > > > On Wed, Jan 31, 2018 at 12:07 PM, <Vincent.Blondeau(a)lamresearch.com> > wrote: > >> > >> Hi, > >> > >> I would like to know how to change the main Pharo window icon. I saw > that > >> there is a primitive for the title: > >> DisplayScreen class >> primitiveWindowTitle:string: ; primitive: > >> 'primitiveHostWindowTitle' module:'HostWindowPlugin' > >> but I cannot find one for the icon. > >> Should another primitive need to be implemented? > > > > > > The icon is baked into the VM executable. So to change it one has to > build > > a VM with a different icon. > > > > On Windows it is in > > {build.win32x86,build.win64x64}/pharo.cog.spur/Pharo.ico > > and the file that specifies to use Pharo.ico is > > {build.win32x86,build.win64x64}/pharo.cog.spur/Pharo.rc > > > > On Mac OS X it is in > > platforms/iOS/vm/OSX/Pharo.icns > > (alongside three others such as PharoImage.icns) > > and the file that specifies to use Pharo.icns is > > {build.macos32x86,build.macos64x64}/pharo.cog.spur/Makefile > > in setting the VM variable. The file that associates the other icons > with > > specific file types is > > platforms/iOS//vm/OSX/Pharo-Info.plist > > > > If you're changing the Pharo icon let me suggest you update the icon > files > > themselves in the opensmalltalk-vm source tree. > > > > If you're creating a new variant of the VM for some new purpose (say a > > special Lam VM) then let me suggest you add the icons to the > > opensmalltalk-vm source tree, creating special build directories for > these > > VMs, such as {build.macos32x86,build.macos64x64}/lam.pharo.cog.spur/ > > > > If you want to do this privately, then take either of the approaches > above > > and simply don't publish the edits. You can write a script that takes an > > updated checked-out opensmalltalk-vm source tree and edits it with files > > from a specific repository. I have such scripts and can help you with > them. > > Hint, pax is a very convenient directory hierarchy copying tool > available at > > least on Mac OS X. pax -rwlk will copy the trees under a sequence of > > directories into their corresponding places in a target tree. > > > >> > >> Thanks! > >> > >> Vincent > >> > >> > > > > > > > > -- > > _,,,^..^,,,_ > > best, Eliot > > -- _,,,^..^,,,_ best, Eliot

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VM Maker: VMMaker.oscog-eem.2328.mcz
by commits＠source.squeak.org 02 Feb '18

02 Feb '18

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2328.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2328 Author: eem Time: 2 February 2018, 12:58:43.151351 pm UUID: 38b7b2c3-c420-4a1b-b83a-44f6fbbfea0d Ancestors: VMMaker.oscog-eem.2327 StackToRegisterMappingCogit: Replace the UnknownSimStackPtrFlag hack in a fixup's simStackPtr and replace it by a proper flag. Consequently make a fixup's simStackPtr unsigned char, giving us a maximim of 255 stack slots (0 being for the receiver). Fix typos and remove unnecessary doNotGenerate's from initialize methods (CCodeGenerator filters inityialize methods out anyway). =============== Diff against VMMaker.oscog-eem.2327 =============== Item was changed: ----- Method: CCodeGenerator>>addMethodFor:selector: (in category 'utilities') ----- addMethodFor: aClass selector: selector "Add the given method to the code base and answer its translation or nil if it shouldn't be translated." | method tmethod | method := aClass compiledMethodAt: selector. (method pragmaAt: #doNotGenerate) ifNotNil: ["only remove a previous method if this one overrides it, i.e. this is a subclass method. If the existing method is in a different hierarchy this method must be merely a redeirect." (methods at: selector ifAbsent: []) ifNotNil: [:tm| (aClass includesBehavior: tm definingClass) ifTrue: [self removeMethodForSelector: selector]]. ^nil]. method isSubclassResponsibility ifTrue: [^nil]. (self shouldIncludeMethodFor: aClass selector: selector) ifFalse: [^nil]. tmethod := self compileToTMethodSelector: selector in: aClass. + "Even though we exclude initialize methods, we must consider their - "Even thoug we exclude initialize methods, we must consider their global variable usage, otherwise globals may be incorrectly localized." selector == #initialize ifTrue: [self checkForGlobalUsage: (tmethod allReferencedVariablesUsing: self) in: tmethod. ^nil]. self addMethod: tmethod. "If the method has a macro then add the macro. But keep the method for analysis purposes (e.g. its variable accesses)." (method pragmaAt: #cmacro:) ifNotNil: [:pragma| self addMacro: (pragma argumentAt: 1) for: selector. (inlineList includes: selector) ifTrue: [inlineList := inlineList copyWithout: selector]]. (method pragmaAt: #cmacro) ifNotNil: [:pragma| | literal | "Method should be just foo ^const" self assert: (method numArgs = 0 and: [method numLiterals = 3 or: [method isQuick]]). literal := method isQuick ifTrue: [method decompile block statements last expr key] ifFalse: [method literalAt: 1]. self addMacro: '() ', (method isReturnField ifTrue: [literal] ifFalse: [self cLiteralFor: literal value name: method selector]) for: selector. (inlineList includes: selector) ifTrue: [inlineList := inlineList copyWithout: selector]]. ^tmethod! Item was changed: ----- Method: CoInterpreterMT>>initialize (in category 'initialization') ----- initialize - <doNotGenerate> super initialize. relinquishing := checkThreadActivation := deferThreadSwitch := false. foreignCallbackPriority := maxWaitingPriority := disownCount := willNotThreadWarnCount := 0! Item was changed: SharedPool subclass: #CogAbstractRegisters instanceVariableNames: '' + classVariableNames: 'Arg0Reg Arg1Reg CallerSavedRegisterMask ClassReg DPFPReg0 DPFPReg1 DPFPReg10 DPFPReg11 DPFPReg12 DPFPReg13 DPFPReg14 DPFPReg15 DPFPReg2 DPFPReg3 DPFPReg4 DPFPReg5 DPFPReg6 DPFPReg7 DPFPReg8 DPFPReg9 Extra0Reg Extra1Reg Extra2Reg Extra3Reg Extra4Reg Extra5Reg Extra6Reg Extra7Reg FPReg LinkReg NoReg NumFloatRegisters NumRegisters PCReg RISCTempReg ReceiverResultReg SPReg SendNumArgsReg TempReg VarBaseReg' - classVariableNames: 'Arg0Reg Arg1Reg CallerSavedRegisterMask ClassReg DPFPReg0 DPFPReg1 DPFPReg10 DPFPReg11 DPFPReg12 DPFPReg13 DPFPReg14 DPFPReg15 DPFPReg2 DPFPReg3 DPFPReg4 DPFPReg5 DPFPReg6 DPFPReg7 DPFPReg8 DPFPReg9 Extra0Reg Extra1Reg Extra2Reg Extra3Reg Extra4Reg Extra5Reg Extra6Reg Extra7Reg FPReg LinkReg NoReg PCReg RISCTempReg ReceiverResultReg SPReg SendNumArgsReg TempReg VarBaseReg' poolDictionaries: '' category: 'VMMaker-JIT'! !CogAbstractRegisters commentStamp: 'eem 12/26/2015 14:06' prior: 0! I am a pool for the abstract register set that the Cogit uses to define its model of Smalltalk compiled to machine code.! Item was changed: ----- Method: CogBytecodeFixup class>>instVarNamesAndTypesForTranslationDo: (in category 'translation') ----- instVarNamesAndTypesForTranslationDo: aBinaryBlock "Enumerate aBinaryBlock with the names and C type strings for the inst vars to include in a BytecodeFixup struct." "self withAllSubclasses collect: [:ea| ea typedef]" self filteredInstVarNames do: [:ivn| aBinaryBlock value: ivn value: (ivn first ~= $# ifTrue: [ivn caseOf: { + ['targetInstruction'] -> [#'AbstractInstruction *']. + ['mergeSimStack'] -> [#'SimStackEntry *']. + ['instructionIndex'] -> [#'unsigned short']. + ['simStackPtr'] -> [#'unsigned char']. + ['simNativeStackPtr'] -> [#'short']. + ['simNativeStackSize'] -> [#'unsigned short']. + ['isTargetOfBackwardBranch'] -> [#char] }])]! - ['targetInstruction'] -> [#'AbstractInstruction *']. - ['mergeSimStack'] -> [#'SimStackEntry *']. - ['instructionIndex'] -> [#'unsigned short']. - ['simStackPtr'] -> [#'signed char']. - ['simNativeStackPtr'] -> [#'short']. - ['simNativeStackSize'] -> [#'unsigned short']. - ['isReceiverResultRegSelf'] -> [#char] }])]! Item was changed: + ----- Method: CogBytecodeFixup>>initialize (in category 'instance initialization') ----- - ----- Method: CogBytecodeFixup>>initialize (in category 'initialize-release') ----- initialize - <doNotGenerate> targetInstruction := 0! Item was changed: ----- Method: CogRASSBytecodeFixup class>>filteredInstVarNames (in category 'translation') ----- filteredInstVarNames "Override to group char and short vars together for compactness. self typedef" | vars | vars := super filteredInstVarNames asOrderedCollection. vars remove: 'mergeSimStack'; + add: 'mergeSimStack' afterIndex: (vars indexOf: 'targetInstruction'). - add: 'mergeSimStack' afterIndex: (vars indexOf: 'targetInstruction'); - remove: 'isReceiverResultRegSelf'; - add: 'isReceiverResultRegSelf' afterIndex: (vars indexOf: 'simStackPtr'). ^vars! Item was changed: CogBytecodeFixup subclass: #CogSSBytecodeFixup + instanceVariableNames: 'simStackPtr isTargetOfBackwardBranch simNativeStackPtr simNativeStackSize' + classVariableNames: 'NeedsMergeFixupFlag NeedsNonMergeFixupFlag' - instanceVariableNames: 'simStackPtr simNativeStackPtr simNativeStackSize' - classVariableNames: 'NeedsMergeFixupFlag NeedsNonMergeFixupFlag UnknownSimStackPtrFlag' poolDictionaries: '' category: 'VMMaker-JIT'! + !CogSSBytecodeFixup commentStamp: 'eem 2/2/2018 10:51' prior: 0! - !CogSSBytecodeFixup commentStamp: 'eem 11/22/2016 08:39' prior: 0! A CogSSBytecodeFixup extends CogBytecodeFixup with state to merge the stack at control-flow joins. At a join the code generator must ensure that the stack is spilled to the same point along both branches and that the simStackPtr is correct. Instance Variables + simStackPtr: <Integer> + isTargetOfBackwardBranch: <Boolean> - simStackPtr: <Integer> simStackPtr + - the simStackPtr at the jump to this fixup. It should either agree with the incoming fixup if control continues, or replace the simStackPtr if control doesn't continue (the incoming control flow ended with a return) + + isTargetOfBackwardBranch: + - if true the fixup is the target of some backward branch! - - the simStackPtr at the jump to this fixup. It should either agree with the incoming fixup if control continues, or replace the simStackPtr if control doesn't continue (the incomming control flow ended with a return)! Item was changed: ----- Method: CogSSBytecodeFixup class>>filteredInstVarNames (in category 'translation') ----- filteredInstVarNames "Override to add ifdef LowcodeVM around the native stack info, and to put char vars before short vars. self typedef" | vars | vars := super filteredInstVarNames asOrderedCollection. vars remove: 'instructionIndex'; + add: 'instructionIndex' afterIndex: (vars indexOf: 'simStackPtr'); + remove: 'isTargetOfBackwardBranch'; + add: 'isTargetOfBackwardBranch' afterIndex: (vars indexOf: 'simStackPtr'); - add: 'instructionIndex' afterIndex: (vars indexOf: 'simStackPtr'); add: '#if LowcodeVM' beforeIndex: (vars indexOf: 'simNativeStackPtr'); add: '#endif' afterIndex: (vars indexOf: 'simNativeStackSize'). ^vars! Item was changed: ----- Method: CogSSBytecodeFixup class>>initialize (in category 'class initialization') ----- initialize "Initialize the fixup flags. In this class we have two states. A fixup is a bytecode being targeted by a branch, and a jump can target the fixup before the byetcode is generated. A non-merge fixup is that for a bytecode that follows a return instruction. There is no control flow merge from the preceding instruction for this kind of fixup. A merge fixup is that for a bytecode where control flow arrives from both the preceding instruction and a branch. When compileAbstractInstructionsFrom:to: finds a merge fixup, it must both set the targetInstruction and merge the stack/register state of the control flow from the preceding instruction with the stack/register state from the branch. Later still, when code is generated jumps follow fixups to eliminate the fixup and target the right instruction." NeedsNonMergeFixupFlag := 1. NeedsMergeFixupFlag := 2. + self assert: NeedsNonMergeFixupFlag < NeedsMergeFixupFlag! - self assert: NeedsNonMergeFixupFlag < NeedsMergeFixupFlag. - - UnknownSimStackPtrFlag := -2! Item was added: + ----- Method: CogSSBytecodeFixup>>initialize (in category 'instance initialization') ----- + initialize + targetInstruction := 0. + isTargetOfBackwardBranch := false! Item was changed: ----- Method: CogSSBytecodeFixup>>isBackwardBranchFixup (in category 'testing') ----- isBackwardBranchFixup + ^isTargetOfBackwardBranch! - <inline: true> - ^ simStackPtr = UnknownSimStackPtrFlag! Item was changed: ----- Method: CogSSBytecodeFixup>>setIsBackwardBranchFixup (in category 'accessing') ----- setIsBackwardBranchFixup <inline: true> + isTargetOfBackwardBranch := true! - simStackPtr := UnknownSimStackPtrFlag. - LowcodeVM ifTrue: [ - simNativeStackPtr := UnknownSimStackPtrFlag. - simNativeStackSize := 0. - ] - ! Item was changed: ----- Method: NewObjectMemory>>initialize (in category 'initialization') ----- initialize - <doNotGenerate> "Initialize NewObjectMemory when simulating the VM inside Smalltalk." super initialize. checkForLeaks := fullGCLock := 0. needGCFlag := false. heapMap := CogCheck32BitHeapMap new! Item was changed: ----- Method: ObjectMemory>>initialize (in category 'initialization') ----- initialize - <doNotGenerate> "Initialize ObjectMemory when simulating the VM inside Smalltalk." super initialize. headerTypeBytes := CArrayAccessor on: HeaderTypeExtraBytes. rootTable := Array new: RootTableSize. weakRoots := Array new: WeakRootTableSize. remapBuffer := Array new: RemapBufferSize! Item was changed: ----- Method: StackToRegisterMappingCogit>>mergeWithFixupIfRequired: (in category 'simulation stack') ----- mergeWithFixupIfRequired: fixup "If this bytecode has a fixup, some kind of merge needs to be done. There are 4 cases: 1) the bytecode has no fixup (fixup isNotAFixup) do nothing 2) the bytecode has a non merge fixup the fixup has needsNonMergeFixup. The code generating non merge fixup (currently only special selector code) is responsible for the merge so no need to do it. We set deadCode to false as the instruction can be reached from jumps. 3) the bytecode has a merge fixup, but execution flow *cannot* fall through to the merge point. the fixup has needsMergeFixup and deadCode = true. ignores the current simStack as it does not mean anything restores the simStack to the state the jumps to the merge point expects it to be. 4) the bytecode has a merge fixup and execution flow *can* fall through to the merge point. the fixup has needsMergeFixup and deadCode = false. flushes the stack to the stack pointer so the fall through execution path simStack is in the state the merge point expects it to be. restores the simStack to the state the jumps to the merge point expects it to be. In addition, if this is a backjump merge point, we patch the fixup to hold the current simStackPtr for later assertions." <var: #fixup type: #'BytecodeFixup *'> self assertCorrectSimStackPtr. "case 1" fixup notAFixup ifTrue: [^0]. "case 2" fixup isNonMergeFixup ifTrue: [deadCode := false. ^0]. "cases 3 and 4" self assert: fixup isMergeFixup. self traceMerge: fixup. deadCode ifTrue: "case 3" + ["Would like to assert fixup simStackPtr >= methodOrBlockNumTemps + but can't because of the initialNils hack." - ["Would like to assert fixup simStackPtr >= methodOrBlockNumTemps but can't because - a) the initialNils hack, b) deadCode removal allows arriving at an isBackwardBranchFixup." self assert: (fixup simStackPtr >= methodOrBlockNumTemps + or: [inBlock = InVanillaBlock]). + simStackPtr := fixup simStackPtr. - or: [inBlock = InVanillaBlock - or: [fixup isBackwardBranchFixup]]). - fixup isBackwardBranchFixup ifFalse: - [simStackPtr := fixup simStackPtr]. LowcodeVM ifTrue: [simNativeStackPtr := fixup simNativeStackPtr. simNativeStackSize := fixup simNativeStackSize]] ifFalse: "case 4" [self ssFlushTo: simStackPtr]. "cases 3 and 4" deadCode := false. fixup isBackwardBranchFixup ifTrue: [fixup simStackPtr: simStackPtr. LowcodeVM ifTrue: [fixup simNativeStackPtr: simNativeStackPtr. fixup simNativeStackSize: simNativeStackSize]]. fixup targetInstruction: self Label. self assert: simStackPtr = fixup simStackPtr. LowcodeVM ifTrue: [self assert: simNativeStackPtr = fixup simNativeStackPtr. self assert: simNativeStackSize = fixup simNativeStackSize]. self cCode: '' inSmalltalk: [self assert: fixup simStackPtr = (self debugStackPointerFor: bytecodePC)]. self restoreSimStackAtMergePoint: fixup. ^0! Item was added: + ----- Method: StackToRegisterMappingCogit>>printRegisterMask: (in category 'debug printing') ----- + printRegisterMask: registerMask + <doNotGenerate> + ^String streamContents: [:s| self printRegisterMask: registerMask on: s]! Item was changed: ----- Method: StackToRegisterMappingCogit>>printSimStack: (in category 'simulation only') ----- + printSimStack: aSimStackOrFixup - printSimStack: aSimStack <doNotGenerate> + (aSimStackOrFixup isKindOf: CogRASSBytecodeFixup) + ifTrue: + [self printSimStack: aSimStackOrFixup mergeSimStack toDepth: aSimStackOrFixup simStackPtr spillBase: -1 on: coInterpreter transcript] + ifFalse: + [self printSimStack: aSimStackOrFixup toDepth: simStackPtr spillBase: simSpillBase on: coInterpreter transcript]! - self printSimStack: aSimStack toDepth: simStackPtr spillBase: simSpillBase on: coInterpreter transcript! Item was changed: ----- Method: StackToRegisterMappingCogit>>restoreSimStackAtMergePoint: (in category 'simulation stack') ----- restoreSimStackAtMergePoint: fixup <inline: true> + "All the execution paths reaching a merge point expect everything + to be spilled on stack. Throw away all simStack optimization state." - "All the execution paths reaching a merge point expect everything to be - spilled on stack and the optStatus is unknown. Throw away all simStack and - optStatus optimization state." self voidReceiverOptStatus. methodOrBlockNumTemps + 1 to: simStackPtr do: [:i| (self simStackAt: i) type: SSSpill; offset: FoxMFReceiver - (i - methodOrBlockNumArgs * objectMemory bytesPerOop); register: FPReg; spilled: true]. simSpillBase := simStackPtr + 1. LowcodeVM ifTrue: [0 to: simNativeStackPtr do: [ :i | (self simNativeStackAt: i) ensureIsMarkedAsSpilled]. simNativeSpillBase := simNativeStackPtr + 1]. ^ 0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushUpThroughTemporaryVariable: (in category 'simulation stack') ----- ssFlushUpThroughTemporaryVariable: tempIndex "Any occurrences on the stack of the value being stored (which is the top of stack) must be flushed, and hence any values colder than them stack." <var: #desc type: #'CogSimStackEntry *'> + | offset | LowcodeVM ifTrue: [ self ssNativeFlushTo: simNativeStackPtr ]. + offset := (self simStackAt: tempIndex + 1) offset. + self assert: offset = (self frameOffsetOfTemporary: tempIndex). self ssFlushUpThrough: [ :desc | desc type = SSBaseOffset and: [desc register = FPReg + and: [desc offset = offset ] ] ]! - and: [desc offset = (self frameOffsetOfTemporary: tempIndex) ] ] ]! Item was changed: ----- Method: StackToRegisterMappingCogit>>traceMerge: (in category 'simulation only') ----- traceMerge: fixup <cmacro: '(ign) 0'> + | index | - | index original | (compilationTrace anyMask: 16) ifTrue: [index := (fixups object identityIndexOf: fixup) - 1. + coInterpreter transcript + ensureCr; + print: index; nextPut: $/; print: index + initialPC; + nextPut: $:; space. + fixup printStateOn: coInterpreter transcript. + coInterpreter transcript cr; flush]! - (fixup isBackwardBranchFixup and: [compilationPass notNil and: [compilationPass > 1 and: [(original := fixup simStackPtr) < 0]]]) ifTrue: - [fixup simStackPtr: simStackPtr]. - - [coInterpreter transcript - ensureCr; - print: index; nextPut: $/; print: index + initialPC; - nextPut: $:; space. - fixup printStateOn: coInterpreter transcript. - coInterpreter transcript cr; flush] - ensure: [original ifNotNil: [fixup simStackPtr: original]]]!

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[OpenSmalltalk/opensmalltalk-vm] 383040: Allow for Xcode9 in 32bit
by GitHub 02 Feb '18

02 Feb '18

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 383040ff57f5b7ad233d9a0d7b7abe3ac2326178 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/383040ff57f5b7ad23… Author: Tobias Pape <tobias(a)netshed.de> Date: 2018-02-02 (Fri, 02 Feb 2018) Changed paths: M build.macos32x86/common/Makefile.flags Log Message: ----------- Allow for Xcode9 in 32bit

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Vm-dev February 2018