Vm-dev January 2018

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255 discussions

[OpenSmalltalk/opensmalltalk-vm] Mac 32-bit 201801252341 VMs report file system errors on launch (#197)
by Ryan Macnak 27 Jan '18

27 Jan '18

``` /BuildRoot/Library/Caches/com.apple.xbs/Sources/AppleFSCompression/AppleFSCompression-96.30.2/Common/ChunkCompression.cpp:50: Error: unsupported compressor 8 /BuildRoot/Library/Caches/com.apple.xbs/Sources/AppleFSCompression/AppleFSCompression-96.30.2/Libraries/CompressData/CompressData.c:353: Error: Unknown compression scheme encountered for file '/System/Library/CoreServices/CoreTypes.bundle/Contents/Resources/Exceptions.plist' /BuildRoot/Library/Caches/com.apple.xbs/Sources/AppleFSCompression/AppleFSCompression-96.30.2/Common/ChunkCompression.cpp:50: Error: unsupported compressor 8 /BuildRoot/Library/Caches/com.apple.xbs/Sources/AppleFSCompression/AppleFSCompression-96.30.2/Libraries/CompressData/CompressData.c:353: Error: Unknown compression scheme encountered for file '/System/Library/CoreServices/CoreTypes.bundle/Contents/Library/AppExceptions.bundle/Exceptions.plist' ``` These errors are apparently non-fatal and the image does run. -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/197

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[OpenSmalltalk/opensmalltalk-vm] Mismatch between image and VM word size fails silently (#198)
by Ryan Macnak 27 Jan '18

27 Jan '18

When opening a 32-bit image from a 64-bit VM or vice versa via the UI, the process ends without any dialog explaining the mismatch. (When launching from the command line, a message about mismatch image formats is reported to stdout.) -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/198

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64-bit on OS X
by Casey Ransberger 27 Jan '18

27 Jan '18

Hi all, Forgive the clueless question: I've been out of the scene for a while. I just found out that Apple is killing 32-bit support in the next version of OS X. Do we run cleanly with a 64-bit VM under OS X? I want to think I knew that we did. Memory is foggy though, and if I need to figure out how to install Linux on the lappy I should get started soon. Thanks in advance. --C

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Re: [Vm-dev] [Pharo-dev] Random corrupted data when copying from very large byte array
by Alistair Grant 26 Jan '18

26 Jan '18

Hi Eliot, On 19 January 2018 at 23:04, Eliot Miranda <eliot.miranda(a)gmail.com> wrote: > Hi Alistair, Hi Clément, > > On Fri, Jan 19, 2018 at 12:53 PM, Alistair Grant <akgrant0710(a)gmail.com> > wrote: >> >> Hi Clément, >> >> On 19 January 2018 at 17:21, Alistair Grant <akgrant0710(a)gmail.com> wrote: >> > Hi Clément, >> > >> > On 19 January 2018 at 17:04, Clément Bera <bera.clement(a)gmail.com> >> > wrote: >> >> Does not seem to be related to prim 105. >> >> > > > I suspect that the problem is the same compactor bug I've been trying to > reproduce all week, and have just fixed. Could you try and reproduce with a > VM built from the latest commit? Happy to, but I'm out all day today, so it will be tomorrow or Monday. Cheers, Alistair (on the run...) > Some details: > The SpurPlanningCompactor works by using the fact that all Spur objects have > room for a forwarding pointer. The compactor make three passes: > > - the first pass through memory works out where objects will go, replacig > their first fields with where they will go, and saving their first fields in > a buffer (savedFirstFieldsSpace). > - the second pass scans all pointer objects, replacing their fields with > where the objects referenced will go (following the forwarding pointers), > and also relocates any pointer fields in savedFirstFieldsSpace > - the final pass slides objects down, restoring their relocated first fields > > The buffer used for savedFirstFieldsSpace determines how many passes are > used. The system will either use eden (which is empty when compaction > occurs) or a large free chunk or allocate a new segment, depending on > whatever yields the largest space. So in the right circumstances eden will > be used and more than one pass required. > > The bug was that when multiple passes are used the compactor forgot to > unmark the corpse left behind when the object was moved. Instead of the > corpse being changed into free space it was retained, but its first field > would be that of the forwarding pointer to its new location, not the actual > first field. So on 32-bits a ByteArray that should have been collected > would have its first 4 bytes appear to be invalid, and on 64-bits its first > 8 bytes. Because the heap on 64-bits can grow larger it could be that the > bug shows itself much less frequently than on 32-bits. When compaction can > be completed in a single pass all corpses are correctly collected, so most > of the time the bug is hidden. > > This is the commit: > commit 0fe1e1ea108e53501a0e728736048062c83a66ce > Author: Eliot Miranda <eliot.miranda(a)gmail.com> > Date: Fri Jan 19 13:17:57 2018 -0800 > > CogVM source as per VMMaker.oscog-eem.2320 > > Spur: > Fix a bad bug in SpurPlnningCompactor. > unmarkObjectsFromFirstFreeObject, > used when the compactor requires more than one pass due to insufficient > savedFirstFieldsSpace, expects the corpse of a moved object to be > unmarked, > but copyAndUnmarkObject:to:bytes:firstField: only unmarked the target. > Unmarking the corpse before the copy unmarks both. This fixes a crash > with > ReleaseBuilder class>>saveAsNewRelease when non-use of cacheDuring: > creates > lots of files, enough to push the system into the multi-pass regime. > >> >> >> HTH, >> Alistair >> >> >> >> > Cheers, >> > Alistair >> > >> > >> > >> >> On Thu, Jan 18, 2018 at 7:12 PM, Clément Bera <bera.clement(a)gmail.com> >> >> wrote: >> >>> >> >>> I would suspect a bug in primitive 105 on byte objects (it was changed >> >>> recently in the VM), called by copyFrom: 1 to: readCount. The bug >> >>> would >> >>> likely by due to specific alignment in readCount or something like >> >>> that. >> >>> (Assuming you're in 32 bits since the 4 bytes are corrupted). >> >>> >> >>> When I get better I can have a look (I am currently quite sick). >> >>> >> >>> On Thu, Jan 18, 2018 at 4:51 PM, Thierry Goubier >> >>> <thierry.goubier(a)gmail.com> wrote: >> >>>> >> >>>> Hi Cyril, >> >>>> >> >>>> try with the last vms available at: >> >>>> >> >>>> https://bintray.com/opensmalltalk/vm/cog/ >> >>>> >> >>>> For example, the last Ubuntu 64bits vm is at: >> >>>> >> >>>> https://bintray.com/opensmalltalk/vm/cog/201801170946#files >> >>>> >> >>>> Regards, >> >>>> >> >>>> Thierry >> >>>> >> >>>> 2018-01-18 16:42 GMT+01:00 Cyrille Delaunay <cy.delaunay(a)gmail.com>: >> >>>>> >> >>>>> Hi everyone, >> >>>>> >> >>>>> I just added a new bug entry for an issue we are experimenting since >> >>>>> some times: >> >>>>> >> >>>>> >> >>>>> >> >>>>> https://pharo.fogbugz.com/f/cases/20982/Random-corrupted-data-when-copying-… >> >>>>> >> >>>>> Here is the description: >> >>>>> >> >>>>> >> >>>>> History: >> >>>>> >> >>>>> This issue has been spotted after experimenting strange behavior >> >>>>> with >> >>>>> seaside upload. >> >>>>> After uploading a big file from a web browser, the modeled file >> >>>>> generated within pharo image begins with 4 unexpected bytes. >> >>>>> This issue occurs randomly: sometimes the first 4 bytes are right. >> >>>>> Sometimes the first 4 bytes are wrong. >> >>>>> This issue only occurs with Pharo 6. >> >>>>> This issue occurs for all platforms (Mac, Ubuntu, Windows) >> >>>>> >> >>>>> Steps to reproduce: >> >>>>> >> >>>>> I have been able to set up a small scenario that highlight the >> >>>>> issue. >> >>>>> >> >>>>> Download Pharo 6.1 on my Mac (Sierra 10.12.6): >> >>>>> https://pharo.org/web/download >> >>>>> Then, iterate over this process till spotting the issue: >> >>>>> >> >>>>> => start the pharo image >> >>>>> => execute this piece of code in a playground >> >>>>> >> >>>>> 1: >> >>>>> 2: >> >>>>> 3: >> >>>>> 4: >> >>>>> 5: >> >>>>> 6: >> >>>>> >> >>>>> ZnServer startDefaultOn: 1701. >> >>>>> ZnServer default maximumEntitySize: 80* 1024 * 1024. >> >>>>> '/Users/cdelaunay/myzip.zip' asFileReference writeStreamDo: [ :out | >> >>>>> out binary; nextPutAll: #[80 75 3 4 10 0 0 0 0 0 125 83 67 73 0 0 0 >> >>>>> 0 0 >> >>>>> 0]. >> >>>>> 18202065 timesRepeat: [ out nextPut: 0 ] >> >>>>> ]. >> >>>>> >> >>>>> => Open a web browser page on: http://localhost:1701/form-test-3 >> >>>>> => Upload the file zip file previously generated ('myzip.zip'). >> >>>>> => If the web page displays: "contents=000000000a00..." (or anything >> >>>>> unexpected), THIS IS THE ISSUE ! >> >>>>> => If the web page displays: "contents=504b03040a00..", the upload >> >>>>> worked fine. You can close the image (without saving) >> >>>>> >> >>>>> >> >>>>> >> >>>>> Debugging: >> >>>>> >> >>>>> >> >>>>> >> >>>>> Bob Arning has been able to reproduce the issue with my scenario. >> >>>>> He dived into the code involved during this process, till reaching >> >>>>> some >> >>>>> "basic" methods where he saw the issue occuring. >> >>>>> >> >>>>> Here are the conclusion till there: >> >>>>> => A corruption occurs while reading an input stream with method >> >>>>> ZnUtils >> >>>>> class>>readUpToEnd:limit: >> >>>>> The first 4 bytes may be altered randomely. >> >>>>> => The first 4 bytes are initially correctly written to an >> >>>>> outputStream. >> >>>>> But, the first 4 bytes of this outputStream gets altered >> >>>>> (corrupted), >> >>>>> sometimes when the inner byte array grows OR when performing the >> >>>>> final >> >>>>> "outputStream contents" >> >>>>> => Here is a piece of code that reproduce the issue (still >> >>>>> randomely. >> >>>>> stopping an restarting the image may change the behavior) >> >>>>> >> >>>>> 1: >> >>>>> 2: >> >>>>> 3: >> >>>>> 4: >> >>>>> 5: >> >>>>> 6: >> >>>>> 7: >> >>>>> 8: >> >>>>> 9: >> >>>>> 10: >> >>>>> 11: >> >>>>> 12: >> >>>>> 13: >> >>>>> 14: >> >>>>> 15: >> >>>>> 16: >> >>>>> 17: >> >>>>> 18: >> >>>>> 19: >> >>>>> 20: >> >>>>> >> >>>>> test4"self test4" | species bufferSize buffer totalRead >> >>>>> outputStream >> >>>>> answer inputStream ba byte1 | ba := ByteArray new: >> >>>>> 18202085. >> >>>>> ba atAllPut: 99. 1 to: 20 do: [ :i | ba at: i put: (#[80 75 >> >>>>> 3 4 10 7 >> >>>>> 7 7 7 7 125 83 67 73 7 7 7 7 7 7] at: i) ]. inputStream := ba >> >>>>> readStream. >> >>>>> bufferSize := 16384. species := ByteArray. >> >>>>> buffer := species new: bufferSize. >> >>>>> totalRead := 0. >> >>>>> outputStream := nil. >> >>>>> [ inputStream atEnd ] whileFalse: [ | readCount | >> >>>>> readCount := inputStream readInto: buffer startingAt: 1 >> >>>>> count: >> >>>>> bufferSize. >> >>>>> totalRead = 0 ifTrue: [ >> >>>>> byte1 := buffer first. >> >>>>> ]. >> >>>>> totalRead := totalRead + readCount. >> >>>>> >> >>>>> outputStream ifNil: [ >> >>>>> inputStream atEnd >> >>>>> ifTrue: [ ^ buffer copyFrom: 1 to: readCount ] >> >>>>> ifFalse: [ outputStream := (species new: bufferSize) >> >>>>> writeStream ] ]. >> >>>>> outputStream next: readCount putAll: buffer startingAt: 1. >> >>>>> byte1 = outputStream contents first ifFalse: [ self halt ]. >> >>>>> ]. >> >>>>> answer := outputStream ifNil: [ species new ] ifNotNil: [ >> >>>>> outputStream contents ]. >> >>>>> byte1 = answer first ifFalse: [ self halt ]. ^answer >> >>>>> >> >>>>> >> >>>>> >> >>>>> suspicions >> >>>>> >> >>>>> This issue appeared with Pharo 6. >> >>>>> >> >>>>> Some people suggested that it could be a vm issue, and to try my >> >>>>> little >> >>>>> scenario with the last available vm. >> >>>>> >> >>>>> I am not sure where to find the last available vm. >> >>>>> >> >>>>> I did the test using these elements: >> >>>>> >> >>>>> https://files.pharo.org/image/60/latest.zip >> >>>>> >> >>>>> https://files.pharo.org/get-files/70/pharo-mac-latest.zip/ >> >>>>> >> >>>>> >> >>>>> >> >>>>> The issue is still present >> >>>>> >> >>>>> >> >>>>> >> >>>>> >> >>>>> -- >> >>>>> Cyrille Delaunay >> >>>> >> >>>> >> >>> >> >>> >> >>> >> >>> -- >> >>> Clément Béra >> >>> Pharo consortium engineer >> >>> https://clementbera.wordpress.com/ >> >>> Bâtiment B 40, avenue Halley 59650 Villeneuve d'Ascq >> >> >> >> >> >> >> >> >> >> -- >> >> Clément Béra >> >> Pharo consortium engineer >> >> https://clementbera.wordpress.com/ >> >> Bâtiment B 40, avenue Halley 59650 Villeneuve d'Ascq >> > > > > -- > _,,,^..^,,,_ > best, Eliot

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VM Maker: VMMaker.oscog-eem.2327.mcz
by commits＠source.squeak.org 26 Jan '18

26 Jan '18

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2327.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2327 Author: eem Time: 26 January 2018, 11:57:52.384622 am UUID: 9b4049be-1cd2-4832-ac13-e744492f1007 Ancestors: VMMaker.oscog-eem.2326 StackToRegisterMappingCogit: Get much stricter with simSpillBase for the benefit of RegisterAllocatingCogit (and eventually SistaCogit). updateSimSpillBase is now called after the new descriptor is pushed and either counts up or counts down as required to guarantee it points one beyoind the last spilled entry. The assertCorrectSimStackPtr asserts now insist on this. With this change we can start to replace all the simSpillBase max: 0 prharses with simply simSpillBase. Deal with the assett failures due to frameless methods with unused temporaries by simply refusing to JIT them; see the new methodFoundInvalidPostScan hook. =============== Diff against VMMaker.oscog-eem.2326 =============== Item was changed: ----- Method: CoInterpreter>>frameCallerContext:put: (in category 'frame access') ----- frameCallerContext: theFP put: aValue "In the StackInterpreter the saved ip field of a base frame holds the base frame's caller context. But in the Cog VM the first word on the stack holds the base frame's caller context, which is immediately above the stacked receiver." <var: #theFP type: #'char *'> + <inline: true> + self assert: (aValue = objectMemory nilObject or: [objectMemory isContext: aValue]). self assert: (self isBaseFrame: theFP). self assert: theFP + (self frameStackedReceiverOffset: theFP) + (2 * objectMemory wordSize) = (stackPages stackPageFor: theFP) baseAddress. self assert: (stackPages longAt: theFP + (self frameStackedReceiverOffset: theFP) + objectMemory wordSize) = (self frameContext: theFP). ^stackPages longAt: theFP + (self frameStackedReceiverOffset: theFP) + (2 * objectMemory wordSize) put: aValue! Item was changed: ----- Method: Cogit>>compileCogMethod: (in category 'compile abstract instructions') ----- compileCogMethod: selector <returnTypeC: #'CogMethod *'> | numBytecodes numBlocks numCleanBlocks result extra | hasYoungReferent := (objectMemory isYoungObject: methodObj) or: [objectMemory isYoung: selector]. methodOrBlockNumArgs := coInterpreter argumentCountOf: methodObj. inBlock := 0. postCompileHook := nil. maxLitIndex := -1. extra := ((primitiveIndex := coInterpreter primitiveIndexOf: methodObj) > 0 and: [(coInterpreter isQuickPrimitiveIndex: primitiveIndex) not]) ifTrue: [30] ifFalse: [10]. initialPC := coInterpreter startPCOfMethod: methodObj. "initial estimate. Actual endPC is determined in scanMethod." endPC := (coInterpreter isQuickPrimitiveIndex: primitiveIndex) ifTrue: [initialPC - 1] ifFalse: [objectMemory numBytesOf: methodObj]. numBytecodes := endPC - initialPC + 1. self allocateOpcodes: (numBytecodes + extra) * self estimateOfAbstractOpcodesPerBytecodes bytecodes: numBytecodes ifFail: [^coInterpreter cCoerceSimple: MethodTooBig to: #'CogMethod *']. (numBlocks := self scanMethod) < 0 ifTrue: [^coInterpreter cCoerceSimple: numBlocks to: #'CogMethod *']. numCleanBlocks := self scanForCleanBlocks. + self methodFoundInvalidPostScan ifTrue: + [^coInterpreter cCoerceSimple: ShouldNotJIT to: #'CogMethod *']. self allocateBlockStarts: numBlocks + numCleanBlocks. blockCount := 0. numCleanBlocks > 0 ifTrue: [self addCleanBlockStarts]. (self maybeAllocAndInitCounters and: [self maybeAllocAndInitIRCs]) ifFalse: "Inaccurate error code, but it'll do. This will likely never fail." [^coInterpreter cCoerceSimple: InsufficientCodeSpace to: #'CogMethod *']. blockEntryLabel := nil. methodLabel dependent: nil. (result := self compileEntireMethod) < 0 ifTrue: [^coInterpreter cCoerceSimple: result to: #'CogMethod *']. ^self generateCogMethod: selector! Item was added: + ----- Method: Cogit>>methodFoundInvalidPostScan (in category 'testing') ----- + methodFoundInvalidPostScan + "This is a hook for subclasses to filter out methods they can't deal with." + ^false! Item was changed: ----- Method: RegisterAllocatingCogit>>copySimStackToScratch: (in category 'bytecode generator support') ----- copySimStackToScratch: spillBase <inline: true> + self assert: spillBase > methodOrBlockNumTemps. scratchBytecodePC = bytecodePC ifTrue: [^self]. scratchBytecodePC := bytecodePC. self cCode: [self mem: scratchSimStack cp: simStack y: self simStackSlots * (self sizeof: CogSimStackEntry)] inSmalltalk: [0 to: simStackPtr do: [:i| scratchSimStack at: i put: (simStack at: i) copy]]. scratchSpillBase := spillBase! Item was changed: ----- Method: RegisterAllocatingCogit>>ensureReceiverResultRegContainsSelf (in category 'bytecode generator support') ----- ensureReceiverResultRegContainsSelf + "First ensure that ReceiverResultReg is allocated to self, + which may cause spills, etc. Then copy the register into + any instances of simSelf on the stack." - methodOrBlockNumTemps + 1 to: simStackPtr do: - [:i| - (self simSelf isSameEntryAs: (self simStackAt: i)) - ifTrue: [(self simStackAt: i) liveRegister: ReceiverResultReg] - ifFalse: - [(self simStackAt: i) liveRegister = ReceiverResultReg ifTrue: - [(self simStackAt: i) liveRegister: NoReg]]]. super ensureReceiverResultRegContainsSelf. + "the storeToReg: in putSelfInReceiverResultReg in + ensureReceiverResultRegContainsSelf copies the register to all copies. + So simply check that the stack agrees with this." + self assert: self receiverResultRegIsAssignedToSelfAndNothingElse! - self assert: self receiverIsInReceiverResultReg! Item was changed: ----- Method: RegisterAllocatingCogit>>flushLiveRegistersForSend (in category 'bytecode generator support') ----- flushLiveRegistersForSend <inline: true> 0 to: simStackPtr do: [:i| self assert: ((self simStackAt: i) spilled and: [(self simStackAt: i) type = SSConstant or: [((self simStackAt: i) type = SSBaseOffset or: [i > methodOrBlockNumTemps and: [(self simStackAt: i) type = SSSpill]]) and: [(self simStackAt: i) register = FPReg + and: [i = 0 + or: [(self simStackAt: i) offset = (self frameOffsetOfTemporary: i - 1)]]]]]). - and: [(self simStackAt: i) offset = (self frameOffsetOfTemporary: i)]]]]). (self simStackAt: i) liveRegister: NoReg]! Item was changed: ----- Method: RegisterAllocatingCogit>>freeAnyRegNotConflictingWith: (in category 'simulation stack') ----- freeAnyRegNotConflictingWith: regMask "Spill the closest register on stack not conflicting with regMask. Override to unassign assigned temp regs if necessary." <var: #desc type: #'CogSimStackEntry *'> | index desc | self assert: needsFrame. + self assert: simSpillBase >= 0. + index := simSpillBase. - index := simSpillBase max: 0. [index < simStackPtr] whileTrue: [desc := self simStackAt: index. desc type = SSRegister ifTrue: [(regMask anyMask: (self registerMaskFor: desc register)) ifFalse: [self ssAllocateRequiredReg: desc register. ^desc register]]. index := index + 1]. 1 to: methodOrBlockNumTemps do: [:i| desc := self simStackAt: i. (desc liveRegister = NoReg or: [self register: desc liveRegister isInMask: regMask]) ifFalse: [self ssAllocateRequiredReg: desc liveRegister. ^desc liveRegister]]. (self simSelf liveRegister = NoReg or: [self register: self simSelf liveRegister isInMask: regMask]) ifFalse: [self ssAllocateRequiredReg: self simSelf liveRegister. ^self simSelf liveRegister]. ^NoReg! Item was changed: ----- Method: RegisterAllocatingCogit>>genSpecialSelectorArithmetic (in category 'bytecode generators') ----- genSpecialSelectorArithmetic | primDescriptor rcvrIsConst argIsConst rcvrIsInt argIsInt rcvrInt argInt destReg jumpNotSmallInts jumpContinue jumpOverflow index rcvrReg argReg regMask | <var: #jumpOverflow type: #'AbstractInstruction *'> <var: #jumpContinue type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> primDescriptor := self generatorAt: byte0. argIsInt := (argIsConst := self ssTop type = SSConstant) and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := ((rcvrIsConst := (self ssValue: 1) type = SSConstant) and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]) or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: self simSelf]]. (argIsInt and: [rcvrIsInt and: [rcvrIsConst]]) ifTrue: [| result | rcvrInt := objectMemory integerValueOf: rcvrInt. argInt := objectMemory integerValueOf: argInt. primDescriptor opcode caseOf: { [AddRR] -> [result := rcvrInt + argInt]. [SubRR] -> [result := rcvrInt - argInt]. [AndRR] -> [result := rcvrInt bitAnd: argInt]. [OrRR] -> [result := rcvrInt bitOr: argInt] }. (objectMemory isIntegerValue: result) ifTrue: ["Must annotate the bytecode for correct pc mapping." ^self ssPop: 2; ssPushAnnotatedConstant: (objectMemory integerObjectOf: result)]. ^self genSpecialSelectorSend]. "If there's any constant involved other than a SmallInteger don't attempt to inline." ((rcvrIsConst and: [rcvrIsInt not]) or: [argIsConst and: [argIsInt not]]) ifTrue: [^self genSpecialSelectorSend]. "If we know nothing about the types then better not to inline as the inline cache and primitive code is not terribly slow so wasting time on duplicating tag tests is pointless." (argIsInt or: [rcvrIsInt]) ifFalse: [^self genSpecialSelectorSend]. "Since one or other of the arguments is an integer we can very likely profit from inlining. But if the other type is not SmallInteger or if the operation overflows then we will need to do a send. Since we're allocating values in registers we would like to keep those registers live on the inlined path and reload registers along the non-inlined send path. See reconcileRegisterStateForJoinAfterSpecialSelectorSend below." argIsInt ifTrue: [rcvrReg := self allocateRegForStackEntryAt: 1. (self ssValue: 1) popToReg: rcvrReg. regMask := self registerMaskFor: rcvrReg] ifFalse: [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. self ssTop popToReg: argReg. (self ssValue: 1) popToReg: rcvrReg. regMask := self registerMaskFor: rcvrReg and: argReg]. "rcvrReg can be reused for the result iff the receiver is a constant or is an SSRegister that is not used elsewhere." destReg := ((rcvrIsInt and: [rcvrIsConst]) or: [(self ssValue: 1) type = SSRegister and: [(self anyReferencesToRegister: rcvrReg inAllButTopNItems: 2) not]]) ifTrue: [rcvrReg] ifFalse: [self allocateRegNotConflictingWith: regMask]. self ssPop: 2. jumpNotSmallInts := (rcvrIsInt and: [argIsInt]) ifFalse: [argIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: rcvrReg] ifFalse: [rcvrIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: argReg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: rcvrReg and: argReg scratch: TempReg]]]. rcvrReg ~= destReg ifTrue: [self MoveR: rcvrReg R: destReg]. primDescriptor opcode caseOf: { [AddRR] -> [argIsInt ifTrue: [self AddCq: argInt - ConstZero R: destReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before doing send" rcvrReg = destReg ifTrue: [self SubbCq: argInt - ConstZero R: rcvrReg]] ifFalse: [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: destReg. self AddR: argReg R: destReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before doing send" destReg = rcvrReg ifTrue: [(rcvrIsInt and: [rcvrIsConst]) ifTrue: [self MoveCq: rcvrInt R: rcvrReg] ifFalse: [self SubbR: argReg R: rcvrReg. objectRepresentation genSetSmallIntegerTagsIn: rcvrReg]]]]. [SubRR] -> [argIsInt ifTrue: [self SubCq: argInt - ConstZero R: destReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before doing send" rcvrReg = destReg ifTrue: [self AddcCq: argInt - ConstZero R: rcvrReg]] ifFalse: [(self anyReferencesToRegister: argReg inAllButTopNItems: 0) ifTrue: "argReg is live; cannot strip tags and continue on no overflow without restoring tags" [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: argReg. self SubR: argReg R: destReg. jumpOverflow := self JumpOverflow: 0. "no overflow; must undo the damage before continuing" objectRepresentation genSetSmallIntegerTagsIn: argReg. jumpContinue := self Jump: 0. jumpOverflow jmpTarget: self Label. "overflow; must undo the damage before doing send" ((rcvrIsInt and: [rcvrIsConst]) or: [destReg ~= rcvrReg]) ifFalse: [self AddcR: argReg R: destReg]. objectRepresentation genSetSmallIntegerTagsIn: argReg] ifFalse: [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: argReg. self SubR: argReg R: destReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before doing send" ((rcvrIsInt and: [rcvrIsConst]) or: [destReg ~= rcvrReg]) ifFalse: [self AddcR: argReg R: rcvrReg]. objectRepresentation genSetSmallIntegerTagsIn: argReg]]]. [AndRR] -> [argIsInt ifTrue: [self AndCq: argInt R: destReg] ifFalse: [self AndR: argReg R: destReg]. jumpContinue := jumpNotSmallInts ifNotNil: [self Jump: 0]]. [OrRR] -> [argIsInt ifTrue: [self OrCq: argInt R: destReg] ifFalse: [self OrR: argReg R: destReg]. jumpContinue := jumpNotSmallInts ifNotNil: [self Jump: 0]] }. jumpNotSmallInts ifNil: [jumpContinue ifNil: "overflow cannot happen" [self annotateInstructionForBytecode. self ssPushRegister: destReg. ^0]] ifNotNil: [jumpNotSmallInts jmpTarget: self Label]. self ssPushRegister: destReg. + self copySimStackToScratch: simSpillBase. - self copySimStackToScratch: (simSpillBase min: simStackPtr - 1). self ssPop: 1. self ssFlushTo: simStackPtr. rcvrReg = Arg0Reg ifTrue: [argReg = ReceiverResultReg ifTrue: [self SwapR: Arg0Reg R: Arg0Reg Scratch: TempReg. argReg := Arg0Reg] ifFalse: [self MoveR: rcvrReg R: ReceiverResultReg]. rcvrReg := ReceiverResultReg]. argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg] ifFalse: [argReg ~= Arg0Reg ifTrue: [self MoveR: argReg R: Arg0Reg]]. rcvrReg ~= ReceiverResultReg ifTrue: [self MoveR: rcvrReg R: ReceiverResultReg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines. self reconcileRegisterStateForJoinAfterSpecialSelectorSend. jumpContinue jmpTarget: self Label. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith:forwards: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup forwards: forwards "At a merge point the cogit expects the stack to be in the same state as mergeSimStack. mergeSimStack is the state as of some jump forward or backward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. The state of optStatus must agree. Generate code to merge the current simStack with that of the target fixup, the goal being to keep as many registers live as possible. If the merge is forwards registers can be deassigned (since registers are always written to temp vars). But if backwards, nothing can be deassigned, and the state /must/ reflect the target." "self printSimStack; printSimStack: fixup mergeSimStack" "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" <var: #fixup type: #'BytecodeFixup *'> | startIndex mergeSimStack | <var: #mergeSimStack type: #'SimStackEntry *'> <var: #targetEntry type: #'SimStackEntry *'> <var: #currentEntry type: #'SimStackEntry *'> (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. startIndex := opcodeIndex. "for debugging" "Assignments amongst the registers must be made in order to avoid overwriting. If necessary exchange registers amongst simStack's entries to resolve any conflicts." self reconcileRegistersInTempVarsInCurrentSimStackWithThoseIn: mergeSimStack. (self asserta: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack)) ifFalse: [Notification new tag: #failedMerge; signal]. (self pushForMergeWith: mergeSimStack) ifTrue: [methodOrBlockNumTemps + 1 to: simStackPtr do: [:i| self mergePushingWithEntryInTargetSimStack: mergeSimStack at: i]] ifFalse: [simStackPtr to: methodOrBlockNumTemps + 1 by: -1 do: [:i| self mergePoppingWithEntryInTargetSimStack: mergeSimStack at: i]]. "Still haven't handled simSpillBase." self assert: (simSpillBase > simStackPtr or: [simSpillBase > methodOrBlockNumTemps + and: [(self simStack: mergeSimStack at: simSpillBase - 1) spilled]])! - and: [(self simStack: mergeSimStack at: simSpillBase) spilled]])! Item was changed: ----- Method: RegisterAllocatingCogit>>moveVolatileSimStackEntriesToRegisters (in category 'bytecode generator support') ----- moveVolatileSimStackEntriesToRegisters "When jumping forward to a merge point the stack must be reconcilable with the state that falls through to the merge point. We cannot easily arrange that later we add code to the branch, e.g. to spill values. Instead, any volatile contents must be moved to registers. [In fact, that's not exactly true, consider these two code sequences: self at: (expr ifTrue: [1] ifFalse: [2]) put: a self at: 1 put: (expr ifTrue: [a] ifFalse: [b]) The first one needs 1 saving to a register to reconcile with 2. The second one has 1 on both paths, but we're not clever enough to spot this case yet. First of all, if the constant requires an annotation then it is difficult to deal with. But if the constant does not require an annotation one way would be for a SimStackEntry for an SSConstant to refer to the loading instruction and then at the merge simply change the loading instruction to a Label if the constant is the same on both branches]. Volatile contents are anything not spilled to the stack, because as yet we can only merge registers." <inline: true> | allocatedRegs | <var: #desc type: #'SimStackEntry *'> allocatedRegs := self allocatedRegisters. + self assert: simSpillBase >= 0. + simSpillBase to: simStackPtr do: - (simSpillBase max: 0) to: simStackPtr do: [:i| | desc reg | desc := self simStackAt: i. desc spilled ifTrue: [simSpillBase := i] ifFalse: [desc registerOrNone = NoReg ifTrue: [reg := self allocateRegNotConflictingWith: allocatedRegs. reg = NoReg ifTrue: [self halt] "have to spill" ifFalse: [desc storeToReg: reg. allocatedRegs := allocatedRegs bitOr: (self registerMaskFor: reg)]]]]. self deny: self duplicateRegisterAssignmentsInTemporaries! Item was changed: ----- Method: RegisterAllocatingCogit>>receiverRefOnScratchSimStack (in category 'bytecode generator support') ----- receiverRefOnScratchSimStack + + self assert: scratchSpillBase >= 0. + simStackPtr to: scratchSpillBase by: -1 do: - simStackPtr to: (0 max: scratchSpillBase) by: -1 do: [:i| ((self simStack: scratchSimStack at: i) register = ReceiverResultReg and: [(self simStack: scratchSimStack at: i) type = SSBaseOffset]) ifTrue: [^true]]. ^false! Item was added: + ----- Method: RegisterAllocatingCogit>>receiverResultRegIsAssignedToSelfAndNothingElse (in category 'testing') ----- + receiverResultRegIsAssignedToSelfAndNothingElse + | culprit | + 0 to: simStackPtr do: + [:i| + (self simSelf isSameEntryAs: (self simStackAt: i)) + ~= ((self simStackAt: i) liveRegister = ReceiverResultReg) ifTrue: + [culprit := i. + ^false]]. + ^true! Item was changed: ----- Method: RegisterAllocatingCogit>>ssFlushFrom:upThrough: (in category 'simulation stack') ----- ssFlushFrom: start upThrough: unaryBlock "Any occurrences on the stack of the value being stored (which is the top of stack) must be flushed, and hence any values colder than them stack." <inline: true> + self assert: simSpillBase >= 0. + start to: simSpillBase by: -1 do: - start to: (simSpillBase max: 0) by: -1 do: [ :index | (unaryBlock value: (self simStackAt: index)) ifTrue: [ ^ self ssFlushTo: index ] ]! Item was changed: ----- Method: RegisterAllocatingCogit>>traceSimStack (in category 'simulation only') ----- traceSimStack <cmacro: '() 0'> (compilationTrace anyMask: 4) ifTrue: + [self printSimStack]! - [self printSimSelf; printSimStack]! Item was changed: ----- Method: StackInterpreter>>frameCallerContext:put: (in category 'frame access') ----- frameCallerContext: theFP put: aValue - <inline: true> <var: #theFP type: #'char *'> + <inline: true> + self assert: (aValue = objectMemory nilObject or: [objectMemory isContext: aValue]). ^stackPages longAt: theFP + FoxCallerContext "a.k.a. FoxCallerSavedIP" put: aValue! Item was changed: ----- Method: StackToRegisterMappingCogit>>assertCorrectSimStackPtr (in category 'compile abstract instructions') ----- assertCorrectSimStackPtr <inline: true> "Would like to assert simply simSpillBase > methodOrBlockNumTemps but can't because of the initialNils hack for nested blocks in SqueakV3PlusClosures" self assert: (simSpillBase >= methodOrBlockNumTemps + or: [inBlock = InVanillaBlock and: [simSpillBase >= 0]]). + (needsFrame and: [simSpillBase > 0]) ifTrue: + [self assert: (self simStackAt: simSpillBase - 1) spilled == true. + self assert: (simSpillBase > simStackPtr or: [(self simStackAt: simSpillBase) spilled == false])]. + self cCode: '' inSmalltalk: - or: [inBlock = InVanillaBlock]). - self cCode: '' inSmalltalk: [deadCode ifFalse: [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) + = (self debugStackPointerFor: bytecodePC)]].! - = (self debugStackPointerFor: bytecodePC)]]. - ! Item was added: + ----- Method: StackToRegisterMappingCogit>>methodFoundInvalidPostScan (in category 'testing') ----- + methodFoundInvalidPostScan + "Frameless methods with local temporaries cause problems, + mostly in asserts, and yet they matter not at all for performance. + Shun them." + needsFrame ifFalse: + [^methodOrBlockNumTemps > methodOrBlockNumArgs]. + ^super methodFoundInvalidPostScan! Item was changed: ----- Method: StackToRegisterMappingCogit>>restoreSimStackAtMergePoint: (in category 'simulation stack') ----- restoreSimStackAtMergePoint: fixup <inline: true> "All the execution paths reaching a merge point expect everything to be spilled on stack and the optStatus is unknown. Throw away all simStack and optStatus optimization state." - simSpillBase := methodOrBlockNumTemps + 1. self voidReceiverOptStatus. methodOrBlockNumTemps + 1 to: simStackPtr do: [:i| (self simStackAt: i) type: SSSpill; offset: FoxMFReceiver - (i - methodOrBlockNumArgs * objectMemory bytesPerOop); register: FPReg; spilled: true]. + simSpillBase := simStackPtr + 1. LowcodeVM ifTrue: [0 to: simNativeStackPtr do: [ :i | (self simNativeStackAt: i) ensureIsMarkedAsSpilled]. simNativeSpillBase := simNativeStackPtr + 1]. ^ 0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushUpThrough: (in category 'simulation stack') ----- ssFlushUpThrough: unaryBlock "Any occurrences on the stack of the value being stored (which is the top of stack) must be flushed, and hence any values colder than them stack." <inline: true> + self assert: simSpillBase >= 0. + simStackPtr - 1 to: simSpillBase by: -1 do: - simStackPtr - 1 to: (simSpillBase max: 0) by: -1 do: [ :index | (unaryBlock value: (self simStackAt: index)) ifTrue: [ ^ self ssFlushTo: index ] ]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPop: (in category 'simulation stack') ----- ssPop: n self assert: (simStackPtr - n >= methodOrBlockNumTemps or: [(needsFrame not and: [simStackPtr - n >= 0]) or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil]]). + simStackPtr := simStackPtr - n. + self updateSimSpillBase! - simStackPtr := simStackPtr - n! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPushAnnotatedConstant: (in category 'simulation stack') ----- ssPushAnnotatedConstant: literal + self ssPushConstant: literal. - self ssPush: 1. - self updateSimSpillBase. - self ssTop - type: SSConstant; - spilled: false; - constant: literal; - bcptr: bytecodePC. self annotateInstructionForBytecode. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPushBase:offset: (in category 'simulation stack') ----- ssPushBase: reg offset: offset self ssPush: 1. - self updateSimSpillBase. self ssTop type: SSBaseOffset; spilled: false; register: reg; offset: offset; bcptr: bytecodePC. + self updateSimSpillBase. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPushConstant: (in category 'simulation stack') ----- ssPushConstant: literal self ssPush: 1. - self updateSimSpillBase. self ssTop type: SSConstant; spilled: false; constant: literal; bcptr: bytecodePC. + self updateSimSpillBase. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPushRegister: (in category 'simulation stack') ----- ssPushRegister: reg self ssPush: 1. - self updateSimSpillBase. self ssTop type: SSRegister; spilled: false; register: reg; bcptr: bytecodePC. + self updateSimSpillBase. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>updateSimSpillBase (in category 'simulation stack') ----- updateSimSpillBase + "Something volatile has been pushed on the stack; update simSpillBase accordingly." <inline: true> + self assert: ((simSpillBase > methodOrBlockNumTemps + and: [simStackPtr >= methodOrBlockNumTemps]) + or: [inBlock = InVanillaBlock and: [compilationPass = 1]]). + simSpillBase > simStackPtr + ifTrue: + [simSpillBase := simStackPtr + 1. + [simSpillBase - 1 > methodOrBlockNumTemps + and: [(self simStackAt: simSpillBase - 1) spilled not]] whileTrue: + [simSpillBase := simSpillBase - 1]] + ifFalse: + [[(self simStackAt: simSpillBase) spilled + and: [simSpillBase <= simStackPtr]] whileTrue: + [simSpillBase := simSpillBase + 1]]. + methodOrBlockNumTemps + 1 to: (simSpillBase - 1 min: simStackPtr) do: + [:i| + self assert: (self simStackAt: i) spilled == true]! - self assert: (simSpillBase > methodOrBlockNumTemps - or: [inBlock = InVanillaBlock]). - simSpillBase > simStackPtr ifTrue: - [simSpillBase := simStackPtr max: methodOrBlockNumTemps].!

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VM Maker: VMMaker.oscog-eem.2326.mcz
by commits＠source.squeak.org 26 Jan '18

26 Jan '18

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2326.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2326 Author: eem Time: 26 January 2018, 11:29:37.088038 am UUID: 242c8fcc-b332-4a77-b9f1-9cc0f69c6db3 Ancestors: VMMaker.oscog-eem.2325 StackToRegisterMappingCogit: For simplicity, especially in the RegisterAllocatingCogit subclass, eliminate simSelf and optStatus and include the receiver's simStackEntry as the 0'th element of the simStack. optStatus is therefore whether simSelf's liveRegister is ReceiverResultReg. hence loops from 0 to: methodOrBlockNumTemps - 1 become loops from 1 to: methodOrBlockNumTemps. Teh simSelf variable is replaced by self simSelf, which is short-hand for self simStackAt: 0. Consequently move te liveRegister accessors up from CogRegisterAllocatingSimStackEntry to CogSimStackEntry. =============== Diff against VMMaker.oscog-eem.2325 =============== Item was changed: CogSSBytecodeFixup subclass: #CogRASSBytecodeFixup + instanceVariableNames: 'cogit mergeSimStack' - instanceVariableNames: 'cogit mergeSimStack isReceiverResultRegSelf' classVariableNames: '' poolDictionaries: '' category: 'VMMaker-JIT'! !CogRASSBytecodeFixup commentStamp: 'eem 11/22/2016 08:44' prior: 0! A CogRASSBytecodeFixup extends CogSSBytecodeFixup with state to merge the stack at control-flow joins, preserving register contents. By holding onto the entire stack state a CogRASSBytecodeFixup allows RegisterAllocatingCogit to merge individual stack entries, instead of merely spilling to the same height. Instance Variables cogit: <RegisterAllocatingCogit> mergeSimStack: <Array of: CogRegisterAllocatingSimStackEntry> cogit - the JIT compiler mergeSimStack - the state of the stack at the jump to this fixup! Item was changed: ----- Method: CogRASSBytecodeFixup>>cogit: (in category 'initialize-release') ----- cogit: aCogit cogit := aCogit. - isReceiverResultRegSelf := false. ^self! Item was removed: - ----- Method: CogRASSBytecodeFixup>>isReceiverResultRegSelf (in category 'accessing') ----- - isReceiverResultRegSelf - - ^ isReceiverResultRegSelf! Item was removed: - ----- Method: CogRASSBytecodeFixup>>isReceiverResultRegSelf: (in category 'accessing') ----- - isReceiverResultRegSelf: anObject - - ^isReceiverResultRegSelf := anObject! Item was changed: ----- Method: CogRASSBytecodeFixup>>reinitialize (in category 'accessing') ----- reinitialize <inline: true> super reinitialize. + mergeSimStack := nil! - mergeSimStack := nil. - isReceiverResultRegSelf := false! Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>ensureSpilledAt:from: (in category 'compile abstract instructions') ----- ensureSpilledAt: baseOffset from: baseRegister spilled ifTrue: [type = SSSpill ifTrue: + [self assert: ((offset = baseOffset and: [register = baseRegister]) or: [cogit violatesEnsureSpilledSpillAssert]). - [self assert: (offset = baseOffset and: [register = baseRegister]). liveRegister := NoReg. ^self]]. self assert: type ~= SSSpill. cogit traceSpill: self. type = SSConstant ifTrue: [cogit genPushConstant: constant] ifFalse: [type = SSBaseOffset ifTrue: [liveRegister = NoReg ifTrue: [cogit MoveMw: offset r: register R: TempReg. cogit PushR: TempReg] ifFalse: [cogit PushR: liveRegister]] ifFalse: [self assert: type = SSRegister. cogit PushR: register]. type := SSSpill. offset := baseOffset. register := baseRegister]. liveRegister := NoReg. spilled := true! Item was removed: - ----- Method: CogRegisterAllocatingSimStackEntry>>liveRegister: (in category 'accessing') ----- - liveRegister: anObject - - ^liveRegister := anObject! Item was changed: ----- Method: CogSimStackEntry>>ensureSpilledAt:from: (in category 'compile abstract instructions') ----- ensureSpilledAt: baseOffset from: baseRegister | inst | <var: #inst type: #'AbstractInstruction *'> spilled ifTrue: [type = SSSpill ifTrue: + [self assert: ((offset = baseOffset and: [register = baseRegister]) or: [cogit violatesEnsureSpilledSpillAssert]). - [self assert: (offset = baseOffset and: [register = baseRegister]). ^self]]. self assert: type ~= SSSpill. cogit traceSpill: self. type = SSConstant ifTrue: [inst := cogit genPushConstant: constant] ifFalse: [type = SSBaseOffset ifTrue: [cogit MoveMw: offset r: register R: TempReg. inst := cogit PushR: TempReg] ifFalse: [self assert: type = SSRegister. inst := cogit PushR: register]. type := SSSpill. offset := baseOffset. register := baseRegister]. spilled := true.! Item was added: + ----- Method: CogSimStackEntry>>liveRegister (in category 'accessing') ----- + liveRegister + + ^ liveRegister! Item was added: + ----- Method: CogSimStackEntry>>liveRegister: (in category 'accessing') ----- + liveRegister: anObject + + ^liveRegister := anObject! Item was changed: StackToRegisterMappingCogit subclass: #RegisterAllocatingCogit + instanceVariableNames: 'numFixups mergeSimStacksBase nextFixup scratchSimStack scratchSpillBase ceSendMustBeBooleanAddTrueLongTrampoline ceSendMustBeBooleanAddFalseLongTrampoline recompileForLoopRegisterAssignments scratchBytecodePC' - instanceVariableNames: 'numFixups mergeSimStacksBase nextFixup scratchSimStack scratchSpillBase scratchSimSelf ceSendMustBeBooleanAddTrueLongTrampoline ceSendMustBeBooleanAddFalseLongTrampoline recompileForLoopRegisterAssignments scratchBytecodePC' classVariableNames: '' poolDictionaries: '' category: 'VMMaker-JIT'! !RegisterAllocatingCogit commentStamp: 'eem 2/9/2017 10:40' prior: 0! RegisterAllocatingCogit is an optimizing code generator that is specialized for register allocation. On the contrary to StackToRegisterMappingCogit, RegisterAllocatingCogit keeps at each control flow merge point the state of the simulated stack to merge into and not only an integer fixup. Each branch and jump record the current state of the simulated stack, and each fixup is responsible for merging this state into the saved simulated stack. Instance Variables ceSendMustBeBooleanAddFalseLongTrampoline: <Integer> ceSendMustBeBooleanAddTrueLongTrampoline: <Integer> mergeSimStacksBase: <Integer> nextFixup: <Integer> numFixups: <Integer> scratchOptStatus: <CogSSOptStatus> scratchSimStack: <Array of CogRegisterAllocatingSimStackEntry> scratchSpillBase: <Integer> ceSendMustBeBooleanAddFalseLongTrampoline - the must-be-boolean trampoline for long jump false bytecodes (the existing ceSendMustBeBooleanAddFalseTrampoline is used for short branches) ceSendMustBeBooleanAddTrueLongTrampoline - the must-be-boolean trampoline for long jump true bytecodes (the existing ceSendMustBeBooleanAddTrueTrampoline is used for short branches) mergeSimStacksBase - the base address of the alloca'ed memory for merge fixups nextFixup - the index into mergeSimStacksBase from which the next needed mergeSimStack will be allocated numFixups - a conservative (over) estimate of the number of merge fixups needed in a method scratchOptStatus - a scratch variable to hold the state of optStatus while merge code is generated scratchSimStack - a scratch variable to hold the state of simStack while merge code is generated scratchSpillBase - a scratch variable to hold the state of spillBase while merge code is generated! Item was changed: ----- Method: RegisterAllocatingCogit>>copySimStackToScratch: (in category 'bytecode generator support') ----- copySimStackToScratch: spillBase <inline: true> scratchBytecodePC = bytecodePC ifTrue: [^self]. scratchBytecodePC := bytecodePC. self cCode: [self mem: scratchSimStack cp: simStack y: self simStackSlots * (self sizeof: CogSimStackEntry)] inSmalltalk: [0 to: simStackPtr do: [:i| scratchSimStack at: i put: (simStack at: i) copy]]. + scratchSpillBase := spillBase! - scratchSpillBase := spillBase. - scratchSimSelf := self cCode: [simSelf] inSmalltalk: [simSelf copy]! Item was changed: ----- Method: RegisterAllocatingCogit>>deassignRegisterForTempVar:in: (in category 'bytecode generator support') ----- deassignRegisterForTempVar: targetEntry in: mergeSimStack "If merging a non-temp with a temp that has a live register we can assign to the register, but must unassign the register from the temp, otherwise the temp will acquire the merged value without an assignment. The targetEntry must also be transmogrified into an SSRegister entry, which is done in the caller." <var: #targetEntry type: #'SimStackEntry *'> <var: #duplicateEntry type: #'SimStackEntry *'> <var: #mergeSimStack type: #'SimStackEntry *'> <inline: true> | reg | self halt. "Clément and I hope this shouldn't happen as of the new merge code in reconcileRegistersInTempVarsInCurrentSimStackWithThoseIn:" reg := targetEntry liveRegister. self assert: (reg ~= NoReg and: [targetEntry type = SSConstant or: [targetEntry isFrameTempVar]]). targetEntry type = SSConstant ifTrue: + [simStackPtr to: 1 by: -1 do: - [simStackPtr to: 0 by: -1 do: [:j| | duplicateEntry | duplicateEntry := self simStack: mergeSimStack at: j. (duplicateEntry registerOrNone = reg and: [duplicateEntry type = SSBaseOffset or: [duplicateEntry type = SSSpill]]) ifTrue: [duplicateEntry liveRegister: NoReg]]] ifFalse: + [simStackPtr to: 1 by: -1 do: - [simStackPtr to: 0 by: -1 do: [:j| | duplicateEntry | duplicateEntry := self simStack: mergeSimStack at: j. (targetEntry isSameEntryAs: duplicateEntry) ifTrue: + [j <= methodOrBlockNumTemps - [j < methodOrBlockNumTemps ifTrue: [duplicateEntry liveRegister: NoReg] ifFalse: [duplicateEntry type: SSRegister; register: reg]]]]! Item was changed: ----- Method: RegisterAllocatingCogit>>duplicateRegisterAssignmentsInTemporaries (in category 'debugging') ----- duplicateRegisterAssignmentsInTemporaries | liveRegisters | liveRegisters := 0. + 0 to: methodOrBlockNumTemps do: - 0 to: methodOrBlockNumTemps - 1 do: [:i| | liveRegister | liveRegister := (self simStackAt: i) liveRegister. liveRegister ~= NoReg ifTrue: [(self register: liveRegister isInMask: liveRegisters) ifTrue: [^true]. liveRegisters := liveRegisters bitOr: 1 << liveRegister]]. ^false! Item was changed: ----- Method: RegisterAllocatingCogit>>ensureNonMergeFixupAt: (in category 'compile abstract instructions') ----- ensureNonMergeFixupAt: targetPC "Make sure there's a flagged fixup at the target pc in fixups. Initially a fixup's target is just a flag. Later on it is replaced with a proper instruction. Override to remember the simStack state at the target, if not already there." "self printSimStack; printSimStack: fixup mergeSimStack" true ifTrue: [self shouldNotImplement] ifFalse: [| fixup | fixup := super ensureNonMergeFixupAt: targetPC. fixup mergeSimStack ifNil: [self setMergeSimStackOf: fixup] + ifNotNil: + [self assert: simStackPtr = fixup simStackPtr. + self deny: (self mergeRequiredToTarget: fixup mergeSimStack)]. - ifNotNil: [self assert: simStackPtr = fixup simStackPtr. - self deny: (self mergeRequiredToTarget: fixup mergeSimStack)]. - self receiverIsInReceiverResultReg ifFalse: - [fixup isReceiverResultRegSelf: false]. ^fixup]! Item was changed: ----- Method: RegisterAllocatingCogit>>ensureReceiverResultRegContainsSelf (in category 'bytecode generator support') ----- ensureReceiverResultRegContainsSelf + methodOrBlockNumTemps + 1 to: simStackPtr do: - methodOrBlockNumTemps to: simStackPtr do: [:i| + (self simSelf isSameEntryAs: (self simStackAt: i)) - ((self addressOf: simSelf) isSameEntryAs: (self simStackAt: i)) ifTrue: [(self simStackAt: i) liveRegister: ReceiverResultReg] ifFalse: [(self simStackAt: i) liveRegister = ReceiverResultReg ifTrue: [(self simStackAt: i) liveRegister: NoReg]]]. + super ensureReceiverResultRegContainsSelf. - needsFrame - ifTrue: - [self receiverIsInReceiverResultReg ifFalse: - [self ssAllocateRequiredReg: ReceiverResultReg. - self putSelfInReceiverResultReg]] - ifFalse: - [self assert: (simSelf type = SSRegister - and: [simSelf liveRegister = ReceiverResultReg])]. self assert: self receiverIsInReceiverResultReg! Item was changed: ----- Method: RegisterAllocatingCogit>>ensureRegisterAssignmentsAreAtHeadOfLoop: (in category 'bytecode generator support') ----- ensureRegisterAssignmentsAreAtHeadOfLoop: target "Compiling a loop body will compute a set of live registers. The backward branch must merge with the head of the loop. So it is preferrable to make the register assignments at the end of the loop available at the head. To do this, simply copy the register assignments to the loop head's fixup in the first compilation pass and schedule a second compilation pass. On the second pass the merge will occur when encountering the fixup for the loop head, using exactly the same code as for a merge at the end of an if." | conflictingRegsMask | compilationPass > 1 ifTrue: ["self deny: (self mergeRequiredToTarget: target mergeSimStack)." self assert: (target mergeSimStack isNil or: [self simStack: simStack isIdenticalTo: target mergeSimStack]). ^self]. (self mergeRequiredToTarget: target mergeSimStack) ifFalse: [^self]. "Schedule a recompile and merge the end-of-loop assignments into the head of the loop, replacing any and all register assignments with the state as of the back jump. Because typically the back jump will be taken much more often than the loop entered, favouring the assignments here is more efficient than trying to merge." recompileForLoopRegisterAssignments := true. conflictingRegsMask := self conflictingRegistersBetweenSimStackAnd: target mergeSimStack. self deny: (self register: FPReg isInMask: conflictingRegsMask). 0 to: simStackPtr do: [:i| | currentEntry targetEntry | currentEntry := self simStack: simStack at: i. targetEntry := self simStack: target mergeSimStack at: i. + targetEntry liveRegister: currentEntry liveRegister]! - targetEntry liveRegister: currentEntry liveRegister]. - self receiverIsInReceiverResultReg ifTrue: - [target isReceiverResultRegSelf: true]! Item was changed: ----- Method: RegisterAllocatingCogit>>flushLiveRegistersForCRunTimeCall (in category 'bytecode generator support') ----- flushLiveRegistersForCRunTimeCall "Flush any live registers for a C call, i.e. don't flush caller-saved registers. Answer if any registers were flushed." <inline: true> | flushed reg | flushed := false. - self assert: simSelf type = SSBaseOffset. - reg := simSelf liveRegister. - (reg ~= NoReg and: [(self isCallerSavedReg: reg)]) ifTrue: - [simSelf liveRegister: NoReg. - flushed := true]. 0 to: simStackPtr do: [:i| + self assert: (self simStackAt: i) type = (i <= methodOrBlockNumTemps - self assert: (self simStackAt: i) type = (i < methodOrBlockNumTemps ifTrue: [SSBaseOffset] ifFalse: [SSSpill]). reg := (self simStackAt: i) liveRegister. (reg ~= NoReg and: [(self isCallerSavedReg: reg)]) ifTrue: [(self simStackAt: i) liveRegister: NoReg. flushed := true]]. ^flushed! Item was changed: ----- Method: RegisterAllocatingCogit>>flushLiveRegistersForSend (in category 'bytecode generator support') ----- flushLiveRegistersForSend <inline: true> - self assert: simSelf type = SSBaseOffset. - simSelf liveRegister: NoReg. 0 to: simStackPtr do: [:i| self assert: ((self simStackAt: i) spilled and: [(self simStackAt: i) type = SSConstant or: [((self simStackAt: i) type = SSBaseOffset + or: [i > methodOrBlockNumTemps - or: [i >= methodOrBlockNumTemps and: [(self simStackAt: i) type = SSSpill]]) and: [(self simStackAt: i) register = FPReg and: [(self simStackAt: i) offset = (self frameOffsetOfTemporary: i)]]]]). (self simStackAt: i) liveRegister: NoReg]! Item was changed: ----- Method: RegisterAllocatingCogit>>flushLiveRegistersForSuspensionPoint (in category 'bytecode generator support') ----- flushLiveRegistersForSuspensionPoint "Flush any live registers for a C call at a suspension/resumption point, i.e.flush all registers. Answer if any registers were flushed." <inline: true> | flushed | flushed := false. - self assert: simSelf type = SSBaseOffset. - simSelf liveRegister ~= NoReg ifTrue: - [simSelf liveRegister: NoReg. - flushed := true]. 0 to: simStackPtr do: [:i| + self assert: (i <= methodOrBlockNumTemps - self assert: (i < methodOrBlockNumTemps ifTrue: [(self simStackAt: i) type = SSBaseOffset] ifFalse: [(self simStackAt: i) spilled]). (self simStackAt: i) liveRegister ~= NoReg ifTrue: [(self simStackAt: i) liveRegister: NoReg. flushed := true]]. ^flushed! Item was changed: ----- Method: RegisterAllocatingCogit>>freeAnyRegNotConflictingWith: (in category 'simulation stack') ----- freeAnyRegNotConflictingWith: regMask "Spill the closest register on stack not conflicting with regMask. Override to unassign assigned temp regs if necessary." <var: #desc type: #'CogSimStackEntry *'> | index desc | self assert: needsFrame. index := simSpillBase max: 0. [index < simStackPtr] whileTrue: [desc := self simStackAt: index. desc type = SSRegister ifTrue: [(regMask anyMask: (self registerMaskFor: desc register)) ifFalse: [self ssAllocateRequiredReg: desc register. ^desc register]]. index := index + 1]. + 1 to: methodOrBlockNumTemps do: - 0 to: methodOrBlockNumTemps - 1 do: [:i| desc := self simStackAt: i. (desc liveRegister = NoReg + or: [self register: desc liveRegister isInMask: regMask]) ifFalse: - or: [self register: desc liveRegister isInMask: regMask]) ifFalse: [self ssAllocateRequiredReg: desc liveRegister. ^desc liveRegister]]. + (self simSelf liveRegister = NoReg + or: [self register: self simSelf liveRegister isInMask: regMask]) ifFalse: + [self ssAllocateRequiredReg: self simSelf liveRegister. + ^self simSelf liveRegister]. ^NoReg! Item was changed: ----- Method: RegisterAllocatingCogit>>genJumpBackTo: (in category 'bytecode generator support') ----- genJumpBackTo: targetPC | target | "On first pass install register allocations (if any) as of the end of the loop and back up to recompile. One the second pass generate (any merge other than self elided because register assignments copied to loop head in first pass) cmp stackLimit maybe reload self jumpAboveOrEqual target flush checkForInterrupts merge from flushed (N.B. If stack was flushed before loop we could conceivably jump to the pre-loop merge code) jmp target self printSimStack; printSimStack: target mergeSimStack" self assert: targetPC < bytecodePC. target := self fixupAt: targetPC. self ensureRegisterAssignmentsAreAtHeadOfLoop: target. self MoveAw: coInterpreter stackLimitAddress R: TempReg. - (target isReceiverResultRegSelf - and: [simSelf liveRegister = NoReg]) ifTrue: - [(self addressOf: simSelf) storeToReg: ReceiverResultReg]. self CmpR: TempReg R: SPReg. "N.B. FLAGS := SPReg - TempReg" self JumpAboveOrEqual: target. self ssFlushTo: simStackPtr. self CallRT: ceCheckForInterruptTrampoline. self annotateBytecode: self Label. self flushLiveRegistersForSuspensionPoint. self mergeCurrentSimStackWith: target forwards: false. self Jump: target. deadCode := true. "can't fall through" ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>genSpecialSelectorArithmetic (in category 'bytecode generators') ----- genSpecialSelectorArithmetic | primDescriptor rcvrIsConst argIsConst rcvrIsInt argIsInt rcvrInt argInt destReg jumpNotSmallInts jumpContinue jumpOverflow index rcvrReg argReg regMask | <var: #jumpOverflow type: #'AbstractInstruction *'> <var: #jumpContinue type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> primDescriptor := self generatorAt: byte0. argIsInt := (argIsConst := self ssTop type = SSConstant) and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := ((rcvrIsConst := (self ssValue: 1) type = SSConstant) and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]) + or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: self simSelf]]. - or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: (self addressOf: simSelf)]]. (argIsInt and: [rcvrIsInt and: [rcvrIsConst]]) ifTrue: [| result | rcvrInt := objectMemory integerValueOf: rcvrInt. argInt := objectMemory integerValueOf: argInt. primDescriptor opcode caseOf: { [AddRR] -> [result := rcvrInt + argInt]. [SubRR] -> [result := rcvrInt - argInt]. [AndRR] -> [result := rcvrInt bitAnd: argInt]. [OrRR] -> [result := rcvrInt bitOr: argInt] }. (objectMemory isIntegerValue: result) ifTrue: ["Must annotate the bytecode for correct pc mapping." ^self ssPop: 2; ssPushAnnotatedConstant: (objectMemory integerObjectOf: result)]. ^self genSpecialSelectorSend]. "If there's any constant involved other than a SmallInteger don't attempt to inline." ((rcvrIsConst and: [rcvrIsInt not]) or: [argIsConst and: [argIsInt not]]) ifTrue: [^self genSpecialSelectorSend]. "If we know nothing about the types then better not to inline as the inline cache and primitive code is not terribly slow so wasting time on duplicating tag tests is pointless." (argIsInt or: [rcvrIsInt]) ifFalse: [^self genSpecialSelectorSend]. "Since one or other of the arguments is an integer we can very likely profit from inlining. But if the other type is not SmallInteger or if the operation overflows then we will need to do a send. Since we're allocating values in registers we would like to keep those registers live on the inlined path and reload registers along the non-inlined send path. See reconcileRegisterStateForJoinAfterSpecialSelectorSend below." argIsInt ifTrue: [rcvrReg := self allocateRegForStackEntryAt: 1. (self ssValue: 1) popToReg: rcvrReg. regMask := self registerMaskFor: rcvrReg] ifFalse: [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. self ssTop popToReg: argReg. (self ssValue: 1) popToReg: rcvrReg. regMask := self registerMaskFor: rcvrReg and: argReg]. "rcvrReg can be reused for the result iff the receiver is a constant or is an SSRegister that is not used elsewhere." destReg := ((rcvrIsInt and: [rcvrIsConst]) or: [(self ssValue: 1) type = SSRegister and: [(self anyReferencesToRegister: rcvrReg inAllButTopNItems: 2) not]]) ifTrue: [rcvrReg] ifFalse: [self allocateRegNotConflictingWith: regMask]. self ssPop: 2. jumpNotSmallInts := (rcvrIsInt and: [argIsInt]) ifFalse: [argIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: rcvrReg] ifFalse: [rcvrIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: argReg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: rcvrReg and: argReg scratch: TempReg]]]. rcvrReg ~= destReg ifTrue: [self MoveR: rcvrReg R: destReg]. primDescriptor opcode caseOf: { [AddRR] -> [argIsInt ifTrue: [self AddCq: argInt - ConstZero R: destReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before doing send" rcvrReg = destReg ifTrue: [self SubbCq: argInt - ConstZero R: rcvrReg]] ifFalse: [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: destReg. self AddR: argReg R: destReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before doing send" destReg = rcvrReg ifTrue: [(rcvrIsInt and: [rcvrIsConst]) ifTrue: [self MoveCq: rcvrInt R: rcvrReg] ifFalse: [self SubbR: argReg R: rcvrReg. objectRepresentation genSetSmallIntegerTagsIn: rcvrReg]]]]. [SubRR] -> [argIsInt ifTrue: [self SubCq: argInt - ConstZero R: destReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before doing send" rcvrReg = destReg ifTrue: [self AddcCq: argInt - ConstZero R: rcvrReg]] ifFalse: [(self anyReferencesToRegister: argReg inAllButTopNItems: 0) ifTrue: "argReg is live; cannot strip tags and continue on no overflow without restoring tags" [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: argReg. self SubR: argReg R: destReg. jumpOverflow := self JumpOverflow: 0. "no overflow; must undo the damage before continuing" objectRepresentation genSetSmallIntegerTagsIn: argReg. jumpContinue := self Jump: 0. jumpOverflow jmpTarget: self Label. "overflow; must undo the damage before doing send" ((rcvrIsInt and: [rcvrIsConst]) or: [destReg ~= rcvrReg]) ifFalse: [self AddcR: argReg R: destReg]. objectRepresentation genSetSmallIntegerTagsIn: argReg] ifFalse: [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: argReg. self SubR: argReg R: destReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before doing send" ((rcvrIsInt and: [rcvrIsConst]) or: [destReg ~= rcvrReg]) ifFalse: [self AddcR: argReg R: rcvrReg]. objectRepresentation genSetSmallIntegerTagsIn: argReg]]]. [AndRR] -> [argIsInt ifTrue: [self AndCq: argInt R: destReg] ifFalse: [self AndR: argReg R: destReg]. jumpContinue := jumpNotSmallInts ifNotNil: [self Jump: 0]]. [OrRR] -> [argIsInt ifTrue: [self OrCq: argInt R: destReg] ifFalse: [self OrR: argReg R: destReg]. jumpContinue := jumpNotSmallInts ifNotNil: [self Jump: 0]] }. jumpNotSmallInts ifNil: [jumpContinue ifNil: "overflow cannot happen" [self annotateInstructionForBytecode. self ssPushRegister: destReg. ^0]] ifNotNil: [jumpNotSmallInts jmpTarget: self Label]. self ssPushRegister: destReg. self copySimStackToScratch: (simSpillBase min: simStackPtr - 1). self ssPop: 1. self ssFlushTo: simStackPtr. rcvrReg = Arg0Reg ifTrue: [argReg = ReceiverResultReg ifTrue: [self SwapR: Arg0Reg R: Arg0Reg Scratch: TempReg. argReg := Arg0Reg] ifFalse: [self MoveR: rcvrReg R: ReceiverResultReg]. rcvrReg := ReceiverResultReg]. argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg] ifFalse: [argReg ~= Arg0Reg ifTrue: [self MoveR: argReg R: Arg0Reg]]. rcvrReg ~= ReceiverResultReg ifTrue: [self MoveR: rcvrReg R: ReceiverResultReg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines. self reconcileRegisterStateForJoinAfterSpecialSelectorSend. jumpContinue jmpTarget: self Label. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison | nextPC postBranchPC targetPC primDescriptor branchDescriptor rcvrIsInt rcvrIsConst argIsIntConst argInt jumpNotSmallInts inlineCAB index rcvrReg argReg branchToTarget needMergeToContinue needMergeToTarget | <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> primDescriptor := self generatorAt: byte0. argIsIntConst := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := ((rcvrIsConst := (self ssValue: 1) type = SSConstant) and: [objectMemory isIntegerObject: (self ssValue: 1) constant]) + or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: self simSelf]]. - or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: (self addressOf: simSelf)]]. (argIsIntConst and: [rcvrIsInt and: [rcvrIsConst]]) ifTrue: [^self genStaticallyResolvedSpecialSelectorComparison]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetPC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsIntConst or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. "In-line the comparison and the jump, but if the types are not SmallInteger then we will need to do a send and fall through to the following conditional branch. Since we're allocating values in registers we would like to keep those registers live on the inlined path and reload registers along the non-inlined send path. The merge logic at the branch destinations handles this." argIsIntConst ifTrue: [rcvrReg := self allocateRegForStackEntryAt: 1. (self ssValue: 1) popToReg: rcvrReg. argReg := NoReg] ifFalse: [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. self ssTop popToReg: argReg. (self ssValue: 1) popToReg: rcvrReg]. self ssPop: 2. jumpNotSmallInts := (rcvrIsInt and: [argIsIntConst]) ifFalse: [argIsIntConst ifTrue: [objectRepresentation genJumpNotSmallInteger: rcvrReg] ifFalse: [rcvrIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: argReg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: rcvrReg and: argReg scratch: TempReg]]]. argIsIntConst ifTrue: [self CmpCq: argInt R: rcvrReg] ifFalse: [self CmpR: argReg R: rcvrReg]. "self printSimStack; printSimStack: (self fixupAt: postBranchPC) mergeSimStack; printSimStack: (self fixupAt: targetPC) mergeSimStack" "If there are merges to be performed on the forward branches we have to execute the merge code only along the path requiring that merge, and exactly once." needMergeToTarget := self mergeRequiredForJumpTo: targetPC. needMergeToContinue := self mergeRequiredForJumpTo: postBranchPC. "Cmp is weird/backwards so invert the comparison." (needMergeToTarget and: [needMergeToContinue]) ifTrue: [branchToTarget := self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: 0. self Jump: (self ensureFixupAt: postBranchPC). branchToTarget jmpTarget: self Label. self Jump: (self ensureFixupAt: targetPC)]. (needMergeToTarget and: [needMergeToContinue not]) ifTrue: [self genConditionalBranch: (branchDescriptor isBranchFalse ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureFixupAt: postBranchPC) asUnsignedInteger. self Jump: (self ensureFixupAt: targetPC)]. (needMergeToTarget not and: [needMergeToContinue]) ifTrue: [self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureFixupAt: targetPC) asUnsignedInteger. self Jump: (self ensureFixupAt: postBranchPC)]. (needMergeToTarget or: [needMergeToContinue]) ifFalse: [self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureFixupAt: targetPC) asUnsignedInteger. self Jump: (self ensureFixupAt: postBranchPC)]. jumpNotSmallInts ifNil: [self annotateInstructionForBytecode. deadCode := true. ^0]. jumpNotSmallInts jmpTarget: self Label. self ssFlushTo: simStackPtr. rcvrReg = Arg0Reg ifTrue: [argReg = ReceiverResultReg ifTrue: [self SwapR: Arg0Reg R: Arg0Reg Scratch: TempReg. argReg := Arg0Reg] ifFalse: [self MoveR: rcvrReg R: ReceiverResultReg]. rcvrReg := ReceiverResultReg]. argIsIntConst ifTrue: [self MoveCq: argInt R: Arg0Reg] ifFalse: [argReg ~= Arg0Reg ifTrue: [self MoveR: argReg R: Arg0Reg]]. rcvrReg ~= ReceiverResultReg ifTrue: [self MoveR: rcvrReg R: ReceiverResultReg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. ^self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines! Item was changed: ----- Method: RegisterAllocatingCogit>>initSimStackForFramefulMethod: (in category 'simulation stack') ----- initSimStackForFramefulMethod: startpc super initSimStackForFramefulMethod: startpc. - simSelf liveRegister: NoReg. 0 to: simStackPtr do: [:i| (self simStackAt: i) liveRegister: NoReg]! Item was changed: ----- Method: RegisterAllocatingCogit>>initSimStackForFramelessBlock: (in category 'simulation stack') ----- initSimStackForFramelessBlock: startpc super initSimStackForFramelessBlock: startpc. + self simSelf liveRegister: ReceiverResultReg. + 1 to: simStackPtr do: - simSelf liveRegister: ReceiverResultReg. - 0 to: simStackPtr do: [:i| (self simStackAt: i) liveRegister: NoReg]! Item was changed: ----- Method: RegisterAllocatingCogit>>initSimStackForFramelessMethod: (in category 'simulation stack') ----- initSimStackForFramelessMethod: startpc super initSimStackForFramelessMethod: startpc. - simSelf liveRegister: ReceiverResultReg. 0 to: simStackPtr do: [:i| | desc | desc := self simStackAt: i. desc liveRegister: (desc type = SSRegister ifTrue: [desc register] ifFalse: [NoReg])]! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith:forwards: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup forwards: forwards "At a merge point the cogit expects the stack to be in the same state as mergeSimStack. mergeSimStack is the state as of some jump forward or backward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. The state of optStatus must agree. Generate code to merge the current simStack with that of the target fixup, the goal being to keep as many registers live as possible. If the merge is forwards registers can be deassigned (since registers are always written to temp vars). But if backwards, nothing can be deassigned, and the state /must/ reflect the target." "self printSimStack; printSimStack: fixup mergeSimStack" "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" <var: #fixup type: #'BytecodeFixup *'> | startIndex mergeSimStack | <var: #mergeSimStack type: #'SimStackEntry *'> <var: #targetEntry type: #'SimStackEntry *'> <var: #currentEntry type: #'SimStackEntry *'> (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. startIndex := opcodeIndex. "for debugging" "Assignments amongst the registers must be made in order to avoid overwriting. If necessary exchange registers amongst simStack's entries to resolve any conflicts." self reconcileRegistersInTempVarsInCurrentSimStackWithThoseIn: mergeSimStack. (self asserta: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack)) ifFalse: [Notification new tag: #failedMerge; signal]. (self pushForMergeWith: mergeSimStack) ifTrue: + [methodOrBlockNumTemps + 1 to: simStackPtr do: - [methodOrBlockNumTemps to: simStackPtr do: [:i| self mergePushingWithEntryInTargetSimStack: mergeSimStack at: i]] ifFalse: + [simStackPtr to: methodOrBlockNumTemps + 1 by: -1 do: - [simStackPtr to: methodOrBlockNumTemps by: -1 do: [:i| self mergePoppingWithEntryInTargetSimStack: mergeSimStack at: i]]. "Still haven't handled simSpillBase." self assert: (simSpillBase > simStackPtr + or: [simSpillBase > methodOrBlockNumTemps + and: [(self simStack: mergeSimStack at: simSpillBase) spilled]])! - or: [simSpillBase < (methodOrBlockNumTemps max: 1) - or: [(self simStack: mergeSimStack at: simSpillBase - 1) spilled]]). - fixup isReceiverResultRegSelf ifTrue: - [self receiverIsInReceiverResultReg ifFalse: - [self putSelfInReceiverResultReg]]! Item was changed: ----- Method: RegisterAllocatingCogit>>mergePushingWithEntryInTargetSimStack:at: (in category 'bytecode generator support') ----- mergePushingWithEntryInTargetSimStack: mergeSimStack at: i "Merge an intermediate result on currentSimStack with the corresponding one in target's mergeSimStack. Depending on spilledness, the stack may need to be pushed or popped, or simply a register assignment made." | currentEntry targetEntry | <inline: true> currentEntry := self simStack: simStack at: i. targetEntry := self simStack: mergeSimStack at: i. (currentEntry reconcilePushingWith: targetEntry) ifTrue: + [self assert: i > methodOrBlockNumTemps. - [self assert: i >= methodOrBlockNumTemps. self deassignRegisterForTempVar: targetEntry in: mergeSimStack. targetEntry type: SSRegister; register: targetEntry liveRegister]. "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: spilled ifFalse: [simSpillBase := i - 1]. simStack at: i put: (self cCode: [mergeSimStack at: i] inSmalltalk: [(mergeSimStack at: i) copy])"! Item was changed: ----- Method: RegisterAllocatingCogit>>pushForMergeWith: (in category 'bytecode generator support') ----- pushForMergeWith: mergeSimStack "Answer if values must be pushed from simStack to merge with mergeSimStack, otherwise < 0 (the default)." <var: #mergeSimStack type: #'SimStackEntry *'> <inline: true> + simStackPtr to: methodOrBlockNumTemps + 1 by: -1 do: - simStackPtr to: methodOrBlockNumTemps by: -1 do: [:i| (self simStack: mergeSimStack at: i) spilled ~= (self simStack: simStack at: i) spilled ifTrue: [^(self simStack: mergeSimStack at: i) spilled]]. ^false! Item was removed: - ----- Method: RegisterAllocatingCogit>>receiverIsInReceiverResultReg (in category 'bytecode generator support') ----- - receiverIsInReceiverResultReg - "Used to mark ReceiverResultReg as dead or not containing simSelf. - Used when the simStack has already been flushed, e.g. for sends." - <inline: true> - ^simSelf liveRegister = ReceiverResultReg! Item was changed: ----- Method: RegisterAllocatingCogit>>reconcileRegisterStateForJoinAfterSpecialSelectorSend (in category 'bytecode generator support') ----- reconcileRegisterStateForJoinAfterSpecialSelectorSend "When the control flow from the inlined special selector code (e.g. add or comparison) joins the control flow from the send, taken when the inlined code fails, we should decide whether to reload any registers known to contain useful values or mark them as dead." - "If ReceiverResultReg is live along the inlined path, and is used before the next full send, - reload it on the uncommon path." - scratchSimSelf liveRegister = ReceiverResultReg ifTrue: - [(self existsInstVarRefBeforeSendOrReturn - or: [self receiverRefOnScratchSimStack]) - ifTrue: - [simSelf liveRegister: ReceiverResultReg. - self putSelfInReceiverResultReg] - ifFalse: [self voidReceiverOptStatus]]. - "Restore the simStack to that in scratchSimStack, popping any spilled state back into allocated registers." simSpillBase := scratchSpillBase. simStackPtr to: 0 by: -1 do: [:i| self assert: (i = simStackPtr ifTrue: [(self simStackAt: i) type = SSRegister] ifFalse: [(self simStackAt: i) spilled]). (self simStackAt: i) reconcilePoppingWith: (self simStack: scratchSimStack at: i). simStack at: i put: (self cCode: [scratchSimStack at: i] inSmalltalk: [(scratchSimStack at: i) copy])]! Item was changed: ----- Method: RegisterAllocatingCogit>>reconcileRegistersInTempVarsInCurrentSimStackWithThoseIn: (in category 'bytecode generator support') ----- reconcileRegistersInTempVarsInCurrentSimStackWithThoseIn: mergeSimStack <var: #mergeSimStack type: #'SimStackEntry *'> + 0 to: methodOrBlockNumTemps do: - 0 to: methodOrBlockNumTemps - 1 do: [ :i | | current target | current := self simStack: simStack at: i. target := self simStack: mergeSimStack at: i. target registerMaskOrNone ~= 0 ifTrue: [ target registerMaskOrNone ~= current registerMaskOrNone ifTrue: [ self swap: target with: current at: i]] ifFalse: [current liveRegister: NoReg]]. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>resetSimStack: (in category 'bytecode generator support') ----- resetSimStack: startPC <inline: true> + simSpillBase := methodOrBlockNumTemps + 1. + simStackPtr := methodOrBlockNumTemps. - simSpillBase := methodOrBlockNumTemps. - simStackPtr := methodOrBlockNumTemps - 1. self flushLiveRegistersForSend. self cCode: '' inSmalltalk: + [0 to: methodOrBlockNumTemps do: - [0 to: methodOrBlockNumTemps - 1 do: [:i| (self simStackAt: i) bcptr: startPC]]! Item was changed: ----- Method: RegisterAllocatingCogit>>restoreSimStackAtMergePoint: (in category 'simulation stack') ----- restoreSimStackAtMergePoint: fixup <inline: true> "All the execution paths reaching a merge point expect everything to be spilled on stack and the optStatus is unknown. If the merge point follows a return, it isn't a merge, but a skip past a return. If it is a real merge point then throw away all simStack and optStatus optimization state." + - simSelf liveRegister: (fixup isReceiverResultRegSelf - ifTrue: [ReceiverResultReg] - ifFalse: [NoReg]). fixup mergeSimStack ifNotNil: + [simSpillBase := methodOrBlockNumTemps + 1. - [simSpillBase := methodOrBlockNumTemps. 0 to: simStackPtr do: [:i| self cCode: [simStack at: i put: (fixup mergeSimStack at: i)] inSmalltalk: [(simStack at: i) copyFrom: (fixup mergeSimStack at: i)]]]. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>restoreSimStackFromScratch (in category 'bytecode generator support') ----- restoreSimStackFromScratch <inline: true> self cCode: [self mem: simStack cp: scratchSimStack y: self simStackSlots * (self sizeof: CogSimStackEntry)] inSmalltalk: [0 to: simStackPtr do: [:i| simStack at: i put: (scratchSimStack at: i)]]. + simSpillBase := scratchSpillBase! - simSpillBase := scratchSpillBase. - simSelf := scratchSimSelf! Item was removed: - ----- Method: RegisterAllocatingCogit>>setInterpreter: (in category 'initialization') ----- - setInterpreter: aCoInterpreter - "Override to elide optStatus which shoudl be unused since simSelf has a liveRegister - and hence more elegantly accomplishes the same purpose." - <doNotGenerate> - super setInterpreter: aCoInterpreter. - optStatus := nil! Item was changed: ----- Method: RegisterAllocatingCogit>>setMergeSimStackOf: (in category 'bytecode generator support') ----- setMergeSimStackOf: fixup <var: #fixup type: #'BytecodeFixup *'> self moveVolatileSimStackEntriesToRegisters. fixup mergeSimStack ifNil: [self assert: nextFixup <= numFixups. self cCode: [fixup mergeSimStack: mergeSimStacksBase + (nextFixup * self simStackSlots * (self sizeof: CogSimStackEntry))]. nextFixup := nextFixup + 1] ifNotNil: [self assert: fixup simStackPtr = simStackPtr. 0 to: simStackPtr do: [:i| self assert: ((self simStackAt: i) isSameEntryAs: (self addressOf: (fixup mergeSimStack at: i))). (self simStackAt: i) liveRegister ~= (self addressOf: (fixup mergeSimStack at: i)) liveRegister ifTrue: [(self simStackAt: i) liveRegister: NoReg]]]. + fixup simStackPtr: simStackPtr. - fixup - simStackPtr: simStackPtr; - isReceiverResultRegSelf: self receiverIsInReceiverResultReg. self cCode: [self mem: fixup mergeSimStack cp: simStack y: self simStackSlots * (self sizeof: CogSimStackEntry)] inSmalltalk: [fixup mergeSimStack: self copySimStack]! Item was changed: ----- Method: RegisterAllocatingCogit>>simSelfOnStackInReceiverResultReg (in category 'bytecode generator support') ----- simSelfOnStackInReceiverResultReg "For assert checking only." + methodOrBlockNumTemps + 1 to: simStackPtr do: - methodOrBlockNumTemps to: simStackPtr do: [:i| + ((self simSelf isSameEntryAs: (self simStackAt: i)) - (((self addressOf: simSelf) isSameEntryAs: (self simStackAt: i)) and: [(self simStackAt: i) registerOrNone = ReceiverResultReg]) ifTrue: [^true]]. ^false! Item was changed: ----- Method: RegisterAllocatingCogit>>ssAllocateRequiredRegMask:upThrough:upThroughNative: (in category 'simulation stack') ----- ssAllocateRequiredRegMask: requiredRegsMask upThrough: stackPtr upThroughNative: nativeStackPtr "Override to void any required registers in temp vars." + 0 to: methodOrBlockNumTemps do: - (requiredRegsMask anyMask: (self registerMaskFor: ReceiverResultReg)) ifTrue: - [self voidReceiverOptStatus]. - 0 to: methodOrBlockNumTemps - 1 do: [:i| ((self simStackAt: i) registerMask anyMask: requiredRegsMask) ifTrue: [(self simStackAt: i) liveRegister: NoReg]]. super ssAllocateRequiredRegMask: requiredRegsMask upThrough: stackPtr upThroughNative: nativeStackPtr! Item was changed: ----- Method: RegisterAllocatingCogit>>swap:with:at: (in category 'bytecode generator support') ----- swap: target with: current at: index "Swaps the registers between target and current. target is guaranteed to be in a register. Current is not. If current is in a register, just perform a register swap and update the simStack. If current is not in a register, free the target register and use it. Invariant: items in current's simStack up to index have been resolved with target because we are visiting the stack in order 0 to siumStackPtr. Strategy: since the target simStack is valid (it has a unique disposition of temps) we can spill to obtain registers (since once an entry is written to ther stack its register, if any, can be freed) pop to assign after fully spilling (if necessary)" | currentLiveRegisters | self assert: target registerMaskOrNone ~= 0. current registerMaskOrNone ~= 0 ifTrue: [ self SwapR: target liveRegister R: current liveRegister Scratch: RISCTempReg. + methodOrBlockNumTemps + 1 to: simStackPtr do: - methodOrBlockNumTemps to: simStackPtr do: [:i| | localCurrent | localCurrent := self simStack: simStack at: i. localCurrent liveRegister = current liveRegister ifTrue: [ localCurrent liveRegister: target liveRegister ] ifFalse: [ localCurrent liveRegister = target liveRegister ifTrue: [ localCurrent liveRegister: current liveRegister ] ] ]. current liveRegister: target liveRegister. ^ 0 ]. + 0 to: index - 1 do: [:j | self assert: (self simStack: simStack at: j) liveRegister ~= target liveRegister]. - 0 to: index -1 do: [:j | self assert: (self simStack: simStack at: j) liveRegister ~= target liveRegister]. currentLiveRegisters := self liveRegistersExceptingTopNItems: 0 in: simStack. (self register: target liveRegister isInMask: currentLiveRegisters) ifTrue: [self ssAllocateRequiredReg: target liveRegister]. "Now target liveRegister is available. we set it." current storeToReg: target liveRegister. ^0! Item was removed: - ----- Method: RegisterAllocatingCogit>>voidReceiverOptStatus (in category 'bytecode generator support') ----- - voidReceiverOptStatus - "Used to mark ReceiverResultReg as dead or not containing simSelf. - Used when the simStack has already been flushed, e.g. for sends." - <inline: true> - simSelf liveRegister: NoReg! Item was changed: ----- Method: RegisterAllocatingCogit>>voidReceiverResultRegContainsSelf (in category 'bytecode generator support') ----- voidReceiverResultRegContainsSelf "Used when ReceiverResultReg is allocated for other than simSelf, and there may be references to ReceiverResultReg which need to be spilled." self receiverIsInReceiverResultReg ifFalse: [self deny: self simSelfOnStackInReceiverResultReg. ^self]. + 1 to: methodOrBlockNumTemps do: - methodOrBlockNumTemps to: simStackPtr do: [:i| + self deny: (self simStackAt: i) liveRegister = ReceiverResultReg]. + methodOrBlockNumTemps + 1 to: simStackPtr do: + [:i| + (self simSelf isSameEntryAs: (self simStackAt: i)) ifTrue: - ((self addressOf: simSelf) isSameEntryAs: (self simStackAt: i)) ifTrue: [(self simStackAt: i) liveRegister: NoReg]]. + self simSelf liveRegister: NoReg! - simSelf liveRegister: NoReg! Item was changed: ----- Method: SistaCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison "Override to count inlined branches if followed by a conditional branch. We borrow the following conditional branch's counter and when about to inline the comparison we decrement the counter (without writing it back) and if it trips simply abort the inlining, falling back to the normal send which will then continue to the conditional branch which will trip and enter the abort." | nextPC postBranchPC targetPC primDescriptor branchDescriptor rcvrIsInt rcvrIsConst argIsIntConst argInt jumpNotSmallInts inlineCAB counterAddress countTripped counterReg index | <var: #countTripped type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> (coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ self genSpecialSelectorComparisonWithoutCounters ]. self ssFlushTo: simStackPtr - 2. primDescriptor := self generatorAt: byte0. argIsIntConst := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := ((rcvrIsConst := (self ssValue: 1) type = SSConstant) and: [objectMemory isIntegerObject:(self ssValue: 1) constant]) + or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: self simSelf]]. - or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: (self addressOf: simSelf)]]. "short-cut the jump if operands are SmallInteger constants." (argIsIntConst and: [rcvrIsInt and: [rcvrIsConst]]) ifTrue: [^ self genStaticallyResolvedSpecialSelectorComparison]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetPC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsIntConst or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. argIsIntConst ifTrue: [(self ssValue: 1) popToReg: ReceiverResultReg. self ssPop: 2] ifFalse: [self marshallSendArguments: 1]. jumpNotSmallInts := (rcvrIsInt and: [argIsIntConst]) ifFalse: [argIsIntConst ifTrue: [objectRepresentation genJumpNotSmallInteger: ReceiverResultReg] ifFalse: [rcvrIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: Arg0Reg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: ReceiverResultReg and: Arg0Reg scratch: TempReg]]]. counterReg := self allocateRegNotConflictingWith: (self registerMaskFor: ReceiverResultReg and: Arg0Reg). self genExecutionCountLogicInto: [ :cAddress :countTripBranch | counterAddress := cAddress. countTripped := countTripBranch ] counterReg: counterReg. argIsIntConst ifTrue: [self CmpCq: argInt R: ReceiverResultReg] ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureNonMergeFixupAt: targetPC) asUnsignedInteger. self genFallsThroughCountLogicCounterReg: counterReg counterAddress: counterAddress. self Jump: (self ensureNonMergeFixupAt: postBranchPC). countTripped jmpTarget: self Label. jumpNotSmallInts ifNil: [(self fixupAt: nextPC) notAFixup ifTrue: [branchReachedOnlyForCounterTrip := true]] ifNotNil: [jumpNotSmallInts jmpTarget: countTripped getJmpTarget]. argIsIntConst ifTrue: [self MoveCq: argInt R: Arg0Reg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. ^self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines! Item was changed: ----- Method: SistaRegisterAllocatingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison "Override to count inlined branches if followed by a conditional branch. We borrow the following conditional branch's counter and when about to inline the comparison we decrement the counter (without writing it back) and if it trips simply abort the inlining, falling back to the normal send which will then continue to the conditional branch which will trip and enter the abort." | nextPC postBranchPC targetPC primDescriptor branchDescriptor rcvrIsInt rcvrIsConst argIsIntConst argInt jumpNotSmallInts inlineCAB counterAddress countTripped counterReg index rcvrReg argReg branchToTarget needMergeToContinue needMergeToTarget | <var: #countTripped type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> (coInterpreter isOptimizedMethod: methodObj) ifTrue: [^self genSpecialSelectorComparisonWithoutCounters]. primDescriptor := self generatorAt: byte0. argIsIntConst := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := ((rcvrIsConst := (self ssValue: 1) type = SSConstant) and: [objectMemory isIntegerObject: (self ssValue: 1) constant]) + or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: self simSelf]]. - or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: (self addressOf: simSelf)]]. "short-cut the jump if operands are SmallInteger constants." (argIsIntConst and: [rcvrIsInt and: [rcvrIsConst]]) ifTrue: [^ self genStaticallyResolvedSpecialSelectorComparison]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetPC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsIntConst or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. "In-line the comparison and the jump, but if the types are not SmallInteger then we will need to do a send and fall through to the following conditional branch. Since we're allocating values in registers we would like to keep those registers live on the inlined path and reload registers along the non-inlined send path. The merge logic at the branch destinations handles this." argIsIntConst ifTrue: [rcvrReg := self allocateRegForStackEntryAt: 1. (self ssValue: 1) popToReg: rcvrReg. counterReg := self allocateRegNotConflictingWith: (self registerMaskFor: rcvrReg). argReg := NoReg] ifFalse: [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. self ssTop popToReg: argReg. (self ssValue: 1) popToReg: rcvrReg. counterReg := self allocateRegNotConflictingWith: (self registerMaskFor: rcvrReg and: argReg)]. self ssPop: 2. jumpNotSmallInts := (rcvrIsInt and: [argIsIntConst]) ifFalse: [argIsIntConst ifTrue: [objectRepresentation genJumpNotSmallInteger: rcvrReg] ifFalse: [rcvrIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: argReg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: rcvrReg and: argReg scratch: TempReg]]]. self genExecutionCountLogicInto: [ :cAddress :countTripBranch | counterAddress := cAddress. countTripped := countTripBranch ] counterReg: counterReg. argIsIntConst ifTrue: [self CmpCq: argInt R: rcvrReg] ifFalse: [self CmpR: argReg R: rcvrReg]. "self printSimStack; printSimStack: (self fixupAt: postBranchPC) mergeSimStack; printSimStack: (self fixupAt: targetPC) mergeSimStack" "If there are merges to be performed on the forward branches we have to execute the merge code only along the path requiring that merge, and exactly once." needMergeToTarget := self mergeRequiredForJumpTo: targetPC. needMergeToContinue := self mergeRequiredForJumpTo: postBranchPC. "Cmp is weird/backwards so invert the comparison." (needMergeToTarget and: [needMergeToContinue]) ifTrue: [branchToTarget := self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: 0. self Jump: (self ensureFixupAt: postBranchPC). branchToTarget jmpTarget: self Label. self Jump: (self ensureFixupAt: targetPC)]. (needMergeToTarget and: [needMergeToContinue not]) ifTrue: [self genConditionalBranch: (branchDescriptor isBranchFalse ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureFixupAt: postBranchPC) asUnsignedInteger. self Jump: (self ensureFixupAt: targetPC)]. (needMergeToTarget not and: [needMergeToContinue]) ifTrue: [self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureFixupAt: targetPC) asUnsignedInteger. self Jump: (self ensureFixupAt: postBranchPC)]. (needMergeToTarget or: [needMergeToContinue]) ifFalse: [self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureFixupAt: targetPC) asUnsignedInteger. self Jump: (self ensureFixupAt: postBranchPC)]. countTripped jmpTarget: self Label. jumpNotSmallInts ifNil: [self annotateInstructionForBytecode. deadCode := true. ^0]. jumpNotSmallInts jmpTarget: countTripped getJmpTarget. self ssFlushTo: simStackPtr. rcvrReg = Arg0Reg ifTrue: [argReg = ReceiverResultReg ifTrue: [self SwapR: Arg0Reg R: Arg0Reg Scratch: TempReg. argReg := Arg0Reg] ifFalse: [self MoveR: rcvrReg R: ReceiverResultReg]. rcvrReg := ReceiverResultReg]. argIsIntConst ifTrue: [self MoveCq: argInt R: Arg0Reg] ifFalse: [argReg ~= Arg0Reg ifTrue: [self MoveR: argReg R: Arg0Reg]]. rcvrReg ~= ReceiverResultReg ifTrue: [self MoveR: rcvrReg R: ReceiverResultReg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. ^self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines! Item was changed: SimpleStackBasedCogit subclass: #StackToRegisterMappingCogit + instanceVariableNames: 'prevBCDescriptor numPushNilsFunction pushNilSizeFunction methodOrBlockNumTemps regArgsHaveBeenPushed simStack simStackPtr simSpillBase ceCallCogCodePopReceiverArg0Regs ceCallCogCodePopReceiverArg1Arg0Regs methodAbortTrampolines picAbortTrampolines picMissTrampolines ceCall0ArgsPIC ceCall1ArgsPIC ceCall2ArgsPIC debugStackPointers debugFixupBreaks realCECallCogCodePopReceiverArg0Regs realCECallCogCodePopReceiverArg1Arg0Regs deadCode useTwoPaths currentCallCleanUpSize simNativeStack simNativeStackPtr simNativeSpillBase simNativeStackSize hasNativeFrame compilationPass' - instanceVariableNames: 'prevBCDescriptor numPushNilsFunction pushNilSizeFunction methodOrBlockNumTemps regArgsHaveBeenPushed simSelf simStack simStackPtr simSpillBase optStatus ceCallCogCodePopReceiverArg0Regs ceCallCogCodePopReceiverArg1Arg0Regs methodAbortTrampolines picAbortTrampolines picMissTrampolines ceCall0ArgsPIC ceCall1ArgsPIC ceCall2ArgsPIC debugStackPointers debugFixupBreaks realCECallCogCodePopReceiverArg0Regs realCECallCogCodePopReceiverArg1Arg0Regs deadCode useTwoPaths currentCallCleanUpSize simNativeStack simNativeStackPtr simNativeSpillBase simNativeStackSize hasNativeFrame compilationPass' classVariableNames: 'NeedsMergeFixupFlag NeedsNonMergeFixupFlag' poolDictionaries: 'CogCompilationConstants VMMethodCacheConstants VMObjectIndices VMStackFrameOffsets' category: 'VMMaker-JIT'! StackToRegisterMappingCogit class instanceVariableNames: 'numPushNilsFunction pushNilSizeFunction'! + !StackToRegisterMappingCogit commentStamp: 'eem 1/26/2018 11:21' prior: 0! + StackToRegisterMappingCogit is an optimizing code generator that eliminates a lot of stack operations and inlines some special selector arithmetic. It does so by a simple stack-to-register mapping scheme based on deferring the generation of code to produce operands until operand-consuming operations. The operations that consume operands are sends, stores and returns. This scheme was first conceived by L. Peter Deutch in the HPS Smalltalk VM (the VisualWorks VM). Thank you, Peter. - !StackToRegisterMappingCogit commentStamp: 'eem 3/3/2017 10:29' prior: 0! - StackToRegisterMappingCogit is an optimizing code generator that eliminates a lot of stack operations and inlines some special selector arithmetic. It does so by a simple stack-to-register mapping scheme based on deferring the generation of code to produce operands until operand-consuming operations. The operations that consume operands are sends, stores and returns. See methods in the class-side documentation protocol for more detail. Instance Variables compilationPass: <Integer> currentCallCleanUpSize: <Integer> ceCall0ArgsPIC: <Integer> ceCall1ArgsPIC: <Integer> ceCall2ArgsPIC: <Integer> ceCallCogCodePopReceiverArg0Regs: <Integer> ceCallCogCodePopReceiverArg1Arg0Regs: <Integer> deadCode <Boolean> debugBytecodePointers: <Set of Integer> debugFixupBreaks: <Set of Integer> debugStackPointers: <CArrayAccessor of (Integer|nil)> hasNativeFrame <Boolean> methodAbortTrampolines: <CArrayAccessor of Integer> methodOrBlockNumTemps: <Integer> numPushNilsFunction: <Symbol> - optStatus: <Integer> picAbortTrampolines: <CArrayAccessor of Integer> picMissTrampolines: <CArrayAccessor of Integer> pushNilSizeFunction: <Symbol> realCECallCogCodePopReceiverArg0Regs: <Integer> realCECallCogCodePopReceiverArg1Arg0Regs: <Integer> regArgsHaveBeenPushed: <Boolean> simNativeSpillBase: <Integer> simNativeStack: <CArrayAccessor of CogSimStackNativeEntry> simNativeStackPtr: <Integer> simNativeStackSize: <Integer> - simSelf: <CogSimStackEntry> simSpillBase: <Integer> simStack: <CArrayAccessor of CogSimStackEntry> simStackPtr: <Integer> traceSimStack: <Integer> useTwoPaths <Boolean> compilationPass - counter indicating whether on the first pass through bytecodes in a V3-style embedded block or not. The V3 closure implementation uses pushNil to initialize temporary variables and this makes an initial pushNil ambiguous. With the V3 bytecode set, the JIT must compile to the end of the block to discover if a pushNil is for initializing a temp or to produce an operand. currentCallCleanUpSize - the number of bytes to remove from the stack in a Lowcode call. ceCall0ArgsPIC ceCall1ArgsPIC ceCall2ArgsPIC - the trampoline for entering an N-arg PIC ceCallCogCodePopReceiverArg0Regs ceCallCogCodePopReceiverArg1Arg0Regs - the trampoline for invokinging a method with N register args debugBytecodePointers - a Set of bytecode pcs for setting breakpoints (simulation only) deadCode - set to true to indicate that the next bytecode (up to the next fixup) is not reachable. Used to avoid generating dead code. debugFixupBreaks - a Set of fixup indices for setting breakpoints (simulation only) debugStackPointers + - an Array of stack depths for each bytecode for code verification (simulation only) - - an Array of stack depths for each bytecode for code verification hasNativeFrame - set to true when Lowcode creates a native stack frame for Lowcode callouts. methodAbortTrampolines - a CArrayAccessor of abort trampolines for 0, 1, 2 and N args methodOrBlockNumTemps - the number of method or block temps (including args) in the current compilation unit (method or block) - optStatus - - the variable used to track the status of ReceiverResultReg for avoiding reloading that register with self between adjacent inst var accesses - numPushNilsFunction - the function used to determine the number of push nils at the beginning of a block. This abstracts away from the specific bytecode set(s). picAbortTrampolines - a CArrayAccessor of abort trampolines for 0, 1, 2 and N args picMissTrampolines - a CArrayAccessor of abort trampolines for 0, 1, 2 and N args pushNilSizeFunction - the function used to determine the number of bytes in the push nils bytecode(s) at the beginning of a block. This abstracts away from the specific bytecode set(s). realCECallCogCodePopReceiverArg0Regs realCECallCogCodePopReceiverArg1Arg0Regs - the real trampolines for invoking machine code with N reg args when in the Debug regime regArgsHaveBeenPushed - whether the register args have been pushed before frame build (e.g. when an interpreter primitive is called) simNativeSpillBase - the variable tracking how much of the Lowcode simulation stack has been spilled to the real stack simNativeStack - the Lowcode simulation stack itself simNativeStackPtr - the pointer to the top of the Lowcode simulation stack simNativeStackSize - the size of the Lowcode stack so far - simSelf - - the simulation stack entry representing self in the current compilation unit - simSpillBase - the variable tracking how much of the simulation stack has been spilled to the real stack simStack + - the simulation stack itself, comprising the receiver, arguments, temporaries, and volatile stack contents. The receiver is the 0'th entry, and the 1st is that of the first argument, etc. - - the simulation stack itself simStackPtr - the pointer to the top of the simulation stack useTwoPaths - a variable controlling whether to create two paths through a method based on the existence of inst var stores. With immutability this causes a frameless path to be generated if an otherwise frameless method is frameful simply because of inst var stores. In this case the test to take the first frameless path is if the receiver is not immutable. Without immutability, if a frameless method contains two or more inst var stores, the first path will be code with no store check, chosen by a single check for the receiver being in new space. ! StackToRegisterMappingCogit class instanceVariableNames: 'numPushNilsFunction pushNilSizeFunction'! Item was changed: ----- Method: StackToRegisterMappingCogit>>assertCorrectSimStackPtr (in category 'compile abstract instructions') ----- assertCorrectSimStackPtr + <inline: true> + "Would like to assert simply simSpillBase > methodOrBlockNumTemps but can't because + of the initialNils hack for nested blocks in SqueakV3PlusClosures" + self assert: (simSpillBase >= methodOrBlockNumTemps + or: [inBlock = InVanillaBlock]). + self cCode: '' inSmalltalk: - <inline: true> "generates nothing anyway" - self cCode: '' inSmalltalk: [deadCode ifFalse: [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) = (self debugStackPointerFor: bytecodePC)]]. ! Item was changed: ----- Method: StackToRegisterMappingCogit>>compileAbstractInstructionsFrom:through: (in category 'compile abstract instructions') ----- compileAbstractInstructionsFrom: start through: end "Loop over bytecodes, dispatching to the generator for each bytecode, handling fixups in due course." | nextOpcodeIndex descriptor nExts fixup result | <var: #descriptor type: #'BytecodeDescriptor *'> <var: #fixup type: #'BytecodeFixup *'> self traceSimStack. bytecodePC := start. nExts := result := 0. descriptor := nil. deadCode := false. [self maybeHaltIfDebugPC. + self mergeWithFixupIfRequired: (fixup := self fixupAt: bytecodePC). - fixup := self fixupAt: bytecodePC. - self mergeWithFixupIfRequired: fixup. - self assertCorrectSimStackPtr. descriptor := self loadBytesAndGetDescriptor. nextOpcodeIndex := opcodeIndex. result := deadCode ifTrue: [self mapDeadDescriptorIfNeeded: descriptor] ifFalse: [self perform: descriptor generator]. result = 0 ifTrue: [self assertExtsAreConsumed: descriptor]. self traceDescriptor: descriptor; traceSimStack. self patchFixupTargetIfNeeded: fixup nextOpcodeIndex: nextOpcodeIndex. self maybeDumpLiterals: descriptor. bytecodePC := self nextBytecodePCFor: descriptor exts: nExts. result = 0 and: [bytecodePC <= end]] whileTrue: [nExts := descriptor isExtension ifTrue: [nExts + 1] ifFalse: [0]]. self checkEnoughOpcodes. ^result! Item was changed: ----- Method: StackToRegisterMappingCogit>>debugStackPointerFor: (in category 'simulation only') ----- debugStackPointerFor: bcpc <doNotGenerate> + ^(debugStackPointers at: bcpc) + (needsFrame ifTrue: [0] ifFalse: [1])! - ^(debugStackPointers at: bcpc) - (needsFrame ifTrue: [1] ifFalse: [0])! Item was changed: ----- Method: StackToRegisterMappingCogit>>ensureReceiverResultRegContainsSelf (in category 'bytecode generator support') ----- ensureReceiverResultRegContainsSelf needsFrame ifTrue: [self receiverIsInReceiverResultReg ifFalse: [self ssAllocateRequiredReg: ReceiverResultReg. + self putSelfInReceiverResultReg. + self simSelf liveRegister: ReceiverResultReg]] - self putSelfInReceiverResultReg ]. - optStatus isReceiverResultRegLive: true] ifFalse: + [self assert: (self simSelf type = SSRegister + and: [self simSelf register = ReceiverResultReg + and: [self receiverIsInReceiverResultReg]])]! - [self assert: (simSelf type = SSRegister - and: [simSelf register = ReceiverResultReg]). - self assert: (optStatus isReceiverResultRegLive - and: [optStatus ssEntry = (self addressOf: simSelf)])]! Item was changed: ----- Method: StackToRegisterMappingCogit>>genExtPushFullClosureBytecode (in category 'bytecode generators') ----- genExtPushFullClosureBytecode "Full Block creation compilation. The block's actual code will be compiled separatedly." "* 255 11111111 xxxxxxxx siyyyyyy push Closure Compiled block literal index xxxxxxxx (+ Extend A * 256) numCopied yyyyyy receiverOnStack: s = 1 ignoreOuterContext: i = 1" | numCopied ignoreContext receiverIsOnStack compiledBlock reg | self assert: needsFrame. compiledBlock := self getLiteral: byte1 + (extA << 8). extA := 0. numCopied := byte2 bitAnd: 1<< 6 - 1. receiverIsOnStack := byte2 anyMask: 1 << 7. ignoreContext := byte2 anyMask: 1 << 6. self voidReceiverResultRegContainsSelf. self ssAllocateCallReg: ReceiverResultReg and: SendNumArgsReg and: ClassReg. objectRepresentation genCreateFullClosure: compiledBlock numArgs: (coInterpreter argumentCountOf: compiledBlock) numCopied: numCopied ignoreContext: ignoreContext contextNumArgs: methodOrBlockNumArgs large: (coInterpreter methodNeedsLargeContext: methodObj) inBlock: inBlock. "Closure in ReceiverResultReg" 1 to: numCopied do: [:i| reg := self ssStorePop: true toPreferredReg: TempReg. objectRepresentation genStoreSourceReg: reg slotIndex: FullClosureFirstCopiedValueIndex + numCopied - i intoNewObjectInDestReg: ReceiverResultReg]. receiverIsOnStack ifTrue: [reg := self ssStorePop: true toPreferredReg: TempReg] + ifFalse: [self simSelf storeToReg: (reg := TempReg)]. - ifFalse: [(self addressOf: simSelf) storeToReg: (reg := TempReg)]. objectRepresentation genStoreSourceReg: reg slotIndex: FullClosureReceiverIndex intoNewObjectInDestReg: ReceiverResultReg. self ssPushRegister: ReceiverResultReg. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genPushReceiverBytecode (in category 'bytecode generators') ----- genPushReceiverBytecode self receiverIsInReceiverResultReg ifTrue: [^self ssPushRegister: ReceiverResultReg]. + ^self ssPushDesc: self simSelf! - self assert: simSelf registerOrNone = NoReg. - ^self ssPushDesc: simSelf! Item was changed: ----- Method: StackToRegisterMappingCogit>>genPushTemporaryVariable: (in category 'bytecode generator support') ----- genPushTemporaryVariable: index "If a frameless method (not a block), only argument temps can be accessed. This is assured by the use of needsFrameIfMod16GENumArgs: in pushTemp." self assert: (inBlock > 0 or: [needsFrame or: [index < methodOrBlockNumArgs]]). + ^self ssPushDesc: (simStack at: index + 1)! - ^self ssPushDesc: (simStack at: index)! Item was changed: ----- Method: StackToRegisterMappingCogit>>genSpecialSelectorArithmetic (in category 'bytecode generators') ----- genSpecialSelectorArithmetic | primDescriptor rcvrIsConst argIsConst rcvrIsInt argIsInt rcvrInt argInt result jumpNotSmallInts jumpContinue index | <var: #jumpContinue type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> primDescriptor := self generatorAt: byte0. argIsInt := (argIsConst := self ssTop type = SSConstant) and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := ((rcvrIsConst := (self ssValue: 1) type = SSConstant) and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]) + or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: self simSelf]]. - or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: (self addressOf: simSelf)]]. (argIsInt and: [rcvrIsInt and: [rcvrIsConst]]) ifTrue: [rcvrInt := objectMemory integerValueOf: rcvrInt. argInt := objectMemory integerValueOf: argInt. primDescriptor opcode caseOf: { [AddRR] -> [result := rcvrInt + argInt]. [SubRR] -> [result := rcvrInt - argInt]. [AndRR] -> [result := rcvrInt bitAnd: argInt]. [OrRR] -> [result := rcvrInt bitOr: argInt] }. (objectMemory isIntegerValue: result) ifTrue: ["Must annotate the bytecode for correct pc mapping." ^self ssPop: 2; ssPushAnnotatedConstant: (objectMemory integerObjectOf: result)]. ^self genSpecialSelectorSend]. "If there's any constant involved other than a SmallInteger don't attempt to inline." ((rcvrIsConst and: [rcvrIsInt not]) or: [argIsConst and: [argIsInt not]]) ifTrue: [^self genSpecialSelectorSend]. "If we know nothing about the types then better not to inline as the inline cache and primitive code is not terribly slow so wasting time on duplicating tag tests is pointless." (argIsInt or: [rcvrIsInt]) ifFalse: [^self genSpecialSelectorSend]. argIsInt ifTrue: [self ssFlushTo: simStackPtr - 2. (self ssValue: 1) popToReg: ReceiverResultReg. self ssPop: 2] ifFalse: [self marshallSendArguments: 1]. jumpNotSmallInts := (rcvrIsInt and: [argIsInt]) ifFalse: [argIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: ReceiverResultReg] ifFalse: [rcvrIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: Arg0Reg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: ReceiverResultReg and: Arg0Reg scratch: TempReg]]]. primDescriptor opcode caseOf: { [AddRR] -> [argIsInt ifTrue: [self AddCq: argInt - ConstZero R: ReceiverResultReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before continuing" self SubCq: argInt - ConstZero R: ReceiverResultReg] ifFalse: [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: ReceiverResultReg. self AddR: Arg0Reg R: ReceiverResultReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before continuing" (rcvrIsInt and: [rcvrIsConst]) ifTrue: [self MoveCq: rcvrInt R: ReceiverResultReg] ifFalse: [self SubR: Arg0Reg R: ReceiverResultReg. objectRepresentation genSetSmallIntegerTagsIn: ReceiverResultReg]]]. [SubRR] -> [argIsInt ifTrue: [self SubCq: argInt - ConstZero R: ReceiverResultReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before continuing" self AddCq: argInt - ConstZero R: ReceiverResultReg] ifFalse: [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: Arg0Reg. self SubR: Arg0Reg R: ReceiverResultReg. jumpContinue := self JumpNoOverflow: 0. "overflow; must undo the damage before continuing" self AddR: Arg0Reg R: ReceiverResultReg. objectRepresentation genSetSmallIntegerTagsIn: Arg0Reg]]. [AndRR] -> [argIsInt ifTrue: [self AndCq: argInt R: ReceiverResultReg] ifFalse: [self AndR: Arg0Reg R: ReceiverResultReg]. jumpContinue := jumpNotSmallInts ifNotNil: [self Jump: 0]]. [OrRR] -> [argIsInt ifTrue: [self OrCq: argInt R: ReceiverResultReg] ifFalse: [self OrR: Arg0Reg R: ReceiverResultReg]. jumpContinue := jumpNotSmallInts ifNotNil: [self Jump: 0]] }. jumpNotSmallInts ifNil: [jumpContinue ifNil: "overflow cannot happen" [self annotateInstructionForBytecode. self ssPushRegister: ReceiverResultReg. ^0]] ifNotNil: [jumpNotSmallInts jmpTarget: self Label]. argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines. jumpContinue jmpTarget: self Label. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison | nextPC postBranchPC targetPC primDescriptor branchDescriptor rcvrIsInt rcvrIsConst argIsIntConst argInt jumpNotSmallInts inlineCAB index | <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> self ssFlushTo: simStackPtr - 2. primDescriptor := self generatorAt: byte0. argIsIntConst := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := ((rcvrIsConst := (self ssValue: 1) type = SSConstant) and: [objectMemory isIntegerObject: (self ssValue: 1) constant]) + or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: self simSelf]]. - or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: (self addressOf: simSelf)]]. (argIsIntConst and: [rcvrIsInt and: [rcvrIsConst]]) ifTrue: [^ self genStaticallyResolvedSpecialSelectorComparison]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetPC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsIntConst or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. argIsIntConst ifTrue: [(self ssValue: 1) popToReg: ReceiverResultReg. self ssPop: 2] ifFalse: [self marshallSendArguments: 1]. jumpNotSmallInts := (rcvrIsInt and: [argIsIntConst]) ifFalse: [argIsIntConst ifTrue: [objectRepresentation genJumpNotSmallInteger: ReceiverResultReg] ifFalse: [rcvrIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: Arg0Reg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: ReceiverResultReg and: Arg0Reg scratch: TempReg]]]. argIsIntConst ifTrue: [self CmpCq: argInt R: ReceiverResultReg] ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureNonMergeFixupAt: targetPC) asUnsignedInteger. self Jump: (self ensureNonMergeFixupAt: postBranchPC). jumpNotSmallInts ifNil: [self annotateInstructionForBytecode. self ensureFixupAt: postBranchPC. self ensureFixupAt: targetPC. deadCode := true. ^0]. jumpNotSmallInts jmpTarget: self Label. argIsIntConst ifTrue: [self MoveCq: argInt R: Arg0Reg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. ^self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines! Item was changed: ----- Method: StackToRegisterMappingCogit>>genStorePop:TemporaryVariable: (in category 'bytecode generator stores') ----- genStorePop: popBoolean TemporaryVariable: tempIndex <inline: false> | reg | self ssFlushUpThroughTemporaryVariable: tempIndex. reg := self ssStorePop: popBoolean toPreferredReg: TempReg. self MoveR: reg Mw: (self frameOffsetOfTemporary: tempIndex) r: FPReg. + (self simStackAt: tempIndex + 1) bcptr: bytecodePC. "for debugging" - (self simStackAt: tempIndex) bcptr: bytecodePC. "for debugging" ^0! Item was removed: - ----- Method: StackToRegisterMappingCogit>>initOptStatus: (in category 'simulation stack') ----- - initOptStatus: receiverResultRegLive - <inline: true> - optStatus - isReceiverResultRegLive: receiverResultRegLive; - ssEntry: (self addressOf: simSelf)! Item was changed: ----- Method: StackToRegisterMappingCogit>>initSimStackForFramefulMethod: (in category 'simulation stack') ----- initSimStackForFramefulMethod: startpc <var: #desc type: #'CogSimStackEntry *'> + simStackPtr := methodOrBlockNumTemps. "N.B. Includes num args" + simSpillBase := methodOrBlockNumTemps + 1. + LowcodeVM ifTrue: + [simNativeSpillBase := simNativeStackPtr := -1. + simNativeStackSize := 0]. + self simSelf - simSelf type: SSBaseOffset; spilled: true; register: FPReg; + offset: FoxMFReceiver; + liveRegister: NoReg. - offset: FoxMFReceiver. - self initOptStatus: false. - simSpillBase := methodOrBlockNumTemps. "N.B. Includes num args" - simStackPtr := simSpillBase - 1. - LowcodeVM ifTrue: [ - simNativeSpillBase := simNativeStackPtr := -1. - simNativeStackSize := 0. - ]. "args" + 1 to: methodOrBlockNumArgs do: - 0 to: methodOrBlockNumArgs - 1 do: [:i| | desc | desc := self simStackAt: i. desc type: SSBaseOffset; spilled: true; register: FPReg; + offset: FoxCallerSavedIP + ((methodOrBlockNumArgs - i + 1) * objectMemory wordSize); - offset: FoxCallerSavedIP + ((methodOrBlockNumArgs - i) * objectMemory wordSize); bcptr: startpc]. "temps" + methodOrBlockNumArgs + 1 to: simStackPtr do: - methodOrBlockNumArgs to: simStackPtr do: [:i| | desc | desc := self simStackAt: i. desc type: SSBaseOffset; spilled: true; register: FPReg; + offset: FoxMFReceiver - (i - methodOrBlockNumArgs * objectMemory wordSize); - offset: FoxMFReceiver - (i - methodOrBlockNumArgs + 1 * objectMemory wordSize); bcptr: startpc]! Item was changed: ----- Method: StackToRegisterMappingCogit>>initSimStackForFramelessBlock: (in category 'simulation stack') ----- initSimStackForFramelessBlock: startpc "The register receiver (the closure itself) and args are pushed by the closure value primitive(s) and hence a frameless block has all arguments and copied values pushed to the stack. However, + the method receiver (self) is put in the ReceiverResultReg by the block entry." - the method receiver (self) is put in the ReceiverResultRegister by the block entry." - | desc | <var: #desc type: #'CogSimStackEntry *'> + self simSelf - simSelf type: SSRegister; spilled: false; + register: ReceiverResultReg; + liveRegister: ReceiverResultReg. - register: ReceiverResultReg. - self initOptStatus: true. self assert: methodOrBlockNumTemps >= methodOrBlockNumArgs. + 1 to: methodOrBlockNumTemps do: + [:i| | desc | - 0 to: methodOrBlockNumTemps - 1 do: - [:i| desc := self simStackAt: i. desc type: SSBaseOffset; spilled: true; register: SPReg; offset: ((backEnd hasLinkRegister + ifTrue: [methodOrBlockNumArgs - i] + ifFalse: [methodOrBlockNumArgs + 1 - i]) * objectMemory wordSize); - ifTrue: [methodOrBlockNumArgs - 1- i] - ifFalse: [methodOrBlockNumArgs - i]) * objectMemory wordSize); bcptr: startpc]. + simStackPtr := methodOrBlockNumTemps. "N.B. Includes num args" + simSpillBase := methodOrBlockNumTemps + 1. + LowcodeVM ifTrue: + [simNativeSpillBase := simNativeStackPtr := -1. + simNativeStackSize := 0]! - simSpillBase := simStackPtr := methodOrBlockNumTemps - 1. - LowcodeVM ifTrue: [ - simNativeSpillBase := simNativeStackPtr := -1. - simNativeStackSize := 0. - ].! Item was changed: ----- Method: StackToRegisterMappingCogit>>initSimStackForFramelessMethod: (in category 'simulation stack') ----- initSimStackForFramelessMethod: startpc | desc | <var: #desc type: #'CogSimStackEntry *'> + self simSelf - simSelf type: SSRegister; spilled: false; + register: ReceiverResultReg; + liveRegister: ReceiverResultReg. - register: ReceiverResultReg. - self initOptStatus: true. self assert: methodOrBlockNumTemps = methodOrBlockNumArgs. self assert: self numRegArgs <= 2. (methodOrBlockNumArgs between: 1 and: self numRegArgs) ifTrue: + [desc := self simStackAt: 1. - [desc := self simStackAt: 0. desc type: SSRegister; spilled: false; register: Arg0Reg; bcptr: startpc. methodOrBlockNumArgs > 1 ifTrue: + [desc := self simStackAt: 2. - [desc := self simStackAt: 1. desc type: SSRegister; spilled: false; register: Arg1Reg; bcptr: startpc]] ifFalse: + [1 to: methodOrBlockNumArgs do: - [0 to: methodOrBlockNumArgs - 1 do: [:i| desc := self simStackAt: i. desc type: SSBaseOffset; register: SPReg; spilled: true; offset: ((backEnd hasLinkRegister + ifTrue: [methodOrBlockNumArgs - i] + ifFalse: [methodOrBlockNumArgs + 1 - i]) * objectMemory wordSize); - ifTrue: [methodOrBlockNumArgs - 1- i] - ifFalse: [methodOrBlockNumArgs - i]) * objectMemory wordSize); bcptr: startpc]]. + simStackPtr := methodOrBlockNumArgs. + simSpillBase := methodOrBlockNumArgs + 1. + LowcodeVM ifTrue: + [simNativeSpillBase := simNativeStackPtr := -1. + simNativeStackSize := 0]! - simSpillBase := simStackPtr := methodOrBlockNumArgs - 1. - LowcodeVM ifTrue: [ - simNativeSpillBase := simNativeStackPtr := -1. - simNativeStackSize := 0. - ].! Item was changed: ----- Method: StackToRegisterMappingCogit>>mergeWithFixupIfRequired: (in category 'simulation stack') ----- mergeWithFixupIfRequired: fixup "If this bytecode has a fixup, some kind of merge needs to be done. There are 4 cases: 1) the bytecode has no fixup (fixup isNotAFixup) do nothing 2) the bytecode has a non merge fixup the fixup has needsNonMergeFixup. The code generating non merge fixup (currently only special selector code) is responsible for the merge so no need to do it. We set deadCode to false as the instruction can be reached from jumps. 3) the bytecode has a merge fixup, but execution flow *cannot* fall through to the merge point. the fixup has needsMergeFixup and deadCode = true. ignores the current simStack as it does not mean anything restores the simStack to the state the jumps to the merge point expects it to be. 4) the bytecode has a merge fixup and execution flow *can* fall through to the merge point. the fixup has needsMergeFixup and deadCode = false. flushes the stack to the stack pointer so the fall through execution path simStack is in the state the merge point expects it to be. restores the simStack to the state the jumps to the merge point expects it to be. In addition, if this is a backjump merge point, we patch the fixup to hold the current simStackPtr for later assertions." - <var: #fixup type: #'BytecodeFixup *'> + + self assertCorrectSimStackPtr. + "case 1" fixup notAFixup ifTrue: [^0]. "case 2" fixup isNonMergeFixup ifTrue: [deadCode := false. ^0]. "cases 3 and 4" self assert: fixup isMergeFixup. self traceMerge: fixup. deadCode ifTrue: "case 3" + ["Would like to assert fixup simStackPtr >= methodOrBlockNumTemps but can't because - ["Would like to assert fixup simStackPtr >= (methodOrBlockNumTemps - 1) but can't because a) the initialNils hack, b) deadCode removal allows arriving at an isBackwardBranchFixup." + self assert: (fixup simStackPtr >= methodOrBlockNumTemps + or: [inBlock = InVanillaBlock + or: [fixup isBackwardBranchFixup]]). - self assert: (fixup simStackPtr >= (methodOrBlockNumTemps - 1) or: [inBlock = InVanillaBlock or: [fixup isBackwardBranchFixup]]). fixup isBackwardBranchFixup ifFalse: [simStackPtr := fixup simStackPtr]. LowcodeVM ifTrue: [simNativeStackPtr := fixup simNativeStackPtr. simNativeStackSize := fixup simNativeStackSize]] ifFalse: "case 4" [self ssFlushTo: simStackPtr]. "cases 3 and 4" deadCode := false. fixup isBackwardBranchFixup ifTrue: [fixup simStackPtr: simStackPtr. LowcodeVM ifTrue: [fixup simNativeStackPtr: simNativeStackPtr. fixup simNativeStackSize: simNativeStackSize]]. fixup targetInstruction: self Label. self assert: simStackPtr = fixup simStackPtr. LowcodeVM ifTrue: [self assert: simNativeStackPtr = fixup simNativeStackPtr. self assert: simNativeStackSize = fixup simNativeStackSize]. self cCode: '' inSmalltalk: [self assert: fixup simStackPtr = (self debugStackPointerFor: bytecodePC)]. self restoreSimStackAtMergePoint: fixup. ^0! Item was removed: - ----- Method: StackToRegisterMappingCogit>>printOptStatus (in category 'simulation only') ----- - printOptStatus - <doNotGenerate> - coInterpreter transcript ensureCr; nextPutAll: 'opt: '. - (optStatus isReceiverResultRegLive ~~ true - and: [optStatus ssEntry isNil]) ifTrue: - [coInterpreter transcript nextPutAll: 'none']. - optStatus printStateOn: coInterpreter transcript. - coInterpreter transcript cr; flush! Item was removed: - ----- Method: StackToRegisterMappingCogit>>printSimSelf (in category 'simulation only') ----- - printSimSelf - <doNotGenerate> - coInterpreter transcript ensureCr; nextPutAll: 'self: '. - simSelf printStateOn: coInterpreter transcript. - coInterpreter transcript cr; flush! Item was changed: ----- Method: StackToRegisterMappingCogit>>printSimStack:toDepth:spillBase:on: (in category 'simulation only') ----- printSimStack: aSimStack toDepth: limit spillBase: spillBase on: aStream <doNotGenerate> | tempNames width tabWidth | aStream ensureCr. limit < 0 ifTrue: [^aStream nextPutAll: 'simStackEmpty'; cr; flush]. aSimStack ifNil: [^aStream nextPutAll: 'nil simStack'; cr; flush]. (self class initializationOptions at: #tempNames ifAbsent: nil) ifNotNil: [:tempNamesDictOrNil | | tab longest | tempNames := tempNamesDictOrNil at: (self class initializationOptions at: #startpc ifAbsent: [initialPC]) + 1. longest := tempNames inject: '' into: [:m :t| m size >= t size ifTrue: [m] ifFalse: [t]]. tabWidth := self widthInDefaultFontOf: (tab := String with: Character tab). width := self widthInDefaultFontOf: longest, tab. width <= ((self widthInDefaultFontOf: longest, (String with: Character space)) + 4) ifTrue: [width := width + tabWidth]]. 0 to: limit do: [:i| width ifNotNil: + [self put: (tempNames at: i ifAbsent: [i = 0 ifTrue: ['self'] ifFalse: ['']]) paddedTo: width tabWidth: tabWidth on: aStream]. - [self put: (tempNames at: i + 1 ifAbsent: ['']) paddedTo: width tabWidth: tabWidth on: aStream]. aStream print: i. i = simStackPtr ifTrue: [aStream nextPutAll: '<-' ]. i = spillBase ifTrue: [aStream nextPutAll: '(sb)']. aStream tab: (i = spillBase ifTrue: [1] ifFalse: [2]). (aSimStack at: i) printStateOn: aStream. + aStream cr; flush]. + simSpillBase > limit ifTrue: + [aStream nextPutAll: '(sb: '; print: simSpillBase; nextPut: $); cr; flush]! - aStream cr; flush]! Item was changed: ----- Method: StackToRegisterMappingCogit>>putSelfInReceiverResultReg (in category 'bytecode generator support') ----- putSelfInReceiverResultReg <inline: true> + self simSelf storeToReg: ReceiverResultReg! - (self addressOf: simSelf) storeToReg: ReceiverResultReg - ! Item was changed: ----- Method: StackToRegisterMappingCogit>>receiverIsInReceiverResultReg (in category 'bytecode generator support') ----- receiverIsInReceiverResultReg "Used to mark ReceiverResultReg as dead or not containing simSelf. Used when the simStack has already been flushed, e.g. for sends." <inline: true> + ^self simSelf liveRegister = ReceiverResultReg! - ^optStatus isReceiverResultRegLive! Item was changed: ----- Method: StackToRegisterMappingCogit>>restoreSimStackAtMergePoint: (in category 'simulation stack') ----- restoreSimStackAtMergePoint: fixup <inline: true> "All the execution paths reaching a merge point expect everything to be + spilled on stack and the optStatus is unknown. Throw away all simStack and + optStatus optimization state." + simSpillBase := methodOrBlockNumTemps + 1. - spilled on stack and the optStatus is unknown. Throw away all simStack and - optStatus optimization state." - simSpillBase := methodOrBlockNumTemps. self voidReceiverOptStatus. + methodOrBlockNumTemps + 1 to: simStackPtr do: - methodOrBlockNumTemps to: simStackPtr do: [:i| (self simStackAt: i) type: SSSpill; + offset: FoxMFReceiver - (i - methodOrBlockNumArgs * objectMemory bytesPerOop); - offset: FoxMFReceiver - (i - methodOrBlockNumArgs + 1 * objectMemory bytesPerOop); register: FPReg; spilled: true]. LowcodeVM ifTrue: [0 to: simNativeStackPtr do: [ :i | (self simNativeStackAt: i) ensureIsMarkedAsSpilled]. simNativeSpillBase := simNativeStackPtr + 1]. ^ 0! Item was changed: ----- Method: StackToRegisterMappingCogit>>setInterpreter: (in category 'initialization') ----- setInterpreter: aCoInterpreter "Initialization of the code generator in the simulator. These objects already exist in the generated C VM or are used only in the simulation." <doNotGenerate> super setInterpreter: aCoInterpreter. methodAbortTrampolines := CArrayAccessor on: (Array new: self numRegArgs + 2). picAbortTrampolines := CArrayAccessor on: (Array new: self numRegArgs + 2). picMissTrampolines := CArrayAccessor on: (Array new: self numRegArgs + 2). simStack := CArrayAccessor on: ((1 to: self class simStackSlots) collect: [:i| self simStackEntryClass new cogit: self]). simNativeStack := CArrayAccessor on: ((1 to: self class simNativeStackSlots) collect: [:i| self simStackNativeEntryClass new cogit: self]). - simSelf := self simStackEntryClass new cogit: self. - optStatus := CogSSOptStatus new. debugFixupBreaks := self class initializationOptions at: #debugFixupBreaks ifAbsent: [Set new]. numPushNilsFunction := self class numPushNilsFunction. pushNilSizeFunction := self class pushNilSizeFunction! Item was changed: ----- Method: StackToRegisterMappingCogit>>simSelf (in category 'accessing') ----- simSelf + <cmacro: ' simStack'> + <returnTypeC: #'CogSimStackEntry *'> + ^self simStackAt: 0! - ^simSelf! Item was changed: ----- Method: StackToRegisterMappingCogit>>simStackPrintString (in category 'simulation only') ----- simStackPrintString <doNotGenerate> + ^String streamContents: [:s| self printSimStack: simStack toDepth: simStackPtr spillBase: simSpillBase on: s]! - ^String streamContents: - [:s| - optStatus printStateOn: s. - self printSimStack: simStack toDepth: simStackPtr spillBase: simSpillBase on: s]! Item was changed: ----- Method: StackToRegisterMappingCogit>>simStackSlots (in category 'simulation stack') ----- simStackSlots + "Answer the number of slots to include in a simulated stack. + This needs to be big enough to include all stack slots in a context + plus a slot for the receiver and some overflow for safety." - "Answer the number of slots toinclude in a simulated stack. - This needs to be big enough to include all slots in a context - plus some overflow for safety." <inline: true> + ^((LargeContextSlots - CtxtTempFrameStart + 1 max: 64) * 11 // 10)! - ^((LargeContextSlots - CtxtTempFrameStart max: 64) * 11 // 10)! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssAllocateRequiredFloatRegMask:upThrough:upThroughNative: (in category 'simulation stack') ----- ssAllocateRequiredFloatRegMask: requiredRegsMask upThrough: stackPtr upThroughNative: nativeStackPtr | lastRequired lastRequiredNative liveRegs | lastRequired := -1. lastRequiredNative := -1. "compute live regs while noting the last occurrence of required regs. If these are not free we must spill from simSpillBase to last occurrence. Note we are conservative here; we could allocate FPReg in frameless methods." liveRegs := NoReg. (simSpillBase max: 0) to: stackPtr do: [:i| liveRegs := liveRegs bitOr: (self simStackAt: i) registerMask. ((self simStackAt: i) floatRegisterMask bitAnd: requiredRegsMask) ~= 0 ifTrue: [lastRequired := i]]. + self assert: lastRequiredNative = simNativeStackPtr. + (simNativeSpillBase max: 0) to: nativeStackPtr do: + [:i| + liveRegs := liveRegs bitOr: (self simNativeStackAt: i) nativeRegisterMask. + ((self simNativeStackAt: i) floatRegisterMask bitAnd: requiredRegsMask) ~= 0 ifTrue: + [lastRequiredNative := i]]. - LowcodeVM ifTrue: [ - (simNativeSpillBase max: 0) to: nativeStackPtr do: - [:i| - liveRegs := liveRegs bitOr: (self simNativeStackAt: i) nativeRegisterMask. - ((self simNativeStackAt: i) floatRegisterMask bitAnd: requiredRegsMask) ~= 0 ifTrue: - [lastRequiredNative := i]]. - ]. "If any of requiredRegsMask are live we must spill." (liveRegs bitAnd: requiredRegsMask) = 0 ifFalse: ["Some live, must spill" + self ssFlushTo: lastRequired. - self ssFlushTo: lastRequired nativeFlushTo: lastRequiredNative. self assert: (self liveFloatRegisters bitAnd: requiredRegsMask) = 0]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssAllocateRequiredRegMask:upThrough:upThroughNative: (in category 'simulation stack') ----- ssAllocateRequiredRegMask: requiredRegsMask upThrough: stackPtr upThroughNative: nativeStackPtr | lastRequired lastRequiredNative liveRegs | lastRequired := -1. lastRequiredNative := -1. "compute live regs while noting the last occurrence of required regs. If these are not free we must spill from simSpillBase to last occurrence. Note we are conservative here; we could allocate FPReg in frameless methods." liveRegs := self registerMaskFor: FPReg and: SPReg. (simSpillBase max: 0) to: stackPtr do: [:i| liveRegs := liveRegs bitOr: (self simStackAt: i) registerMask. ((self simStackAt: i) registerMask bitAnd: requiredRegsMask) ~= 0 ifTrue: [lastRequired := i]]. LowcodeVM ifTrue: + [self assert: nativeStackPtr = simNativeStackPtr. + (simNativeSpillBase max: 0) to: nativeStackPtr do: - [(simNativeSpillBase max: 0) to: nativeStackPtr do: [:i| liveRegs := liveRegs bitOr: (self simNativeStackAt: i) nativeRegisterMask. ((self simNativeStackAt: i) nativeRegisterMask anyMask: requiredRegsMask) ifTrue: [lastRequiredNative := i]]]. "If any of requiredRegsMask are live we must spill." (liveRegs anyMask: requiredRegsMask) ifTrue: + [self ssFlushTo: lastRequired. - [self ssFlushTo: lastRequired nativeFlushTo: lastRequiredNative. self deny: (self liveRegisters anyMask: requiredRegsMask)]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushAll (in category 'simulation stack') ----- ssFlushAll <inline: true> + self ssFlushTo: simStackPtr. - self ssFlushTo: simStackPtr nativeFlushTo: simNativeStackPtr. self voidReceiverResultRegContainsSelf.! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushTo: (in category 'simulation stack') ----- ssFlushTo: index <inline: true> + self assert: self tempsValidAndVolatileEntriesSpilled. + LowcodeVM ifTrue: + [self ssNativeFlushTo: simNativeStackPtr]. + simSpillBase <= index ifTrue: + [(simSpillBase max: methodOrBlockNumTemps + 1) to: index do: + [:i| + self assert: needsFrame. + (self simStackAt: i) + ensureSpilledAt: (self frameOffsetOfTemporary: i - 1) "frameOffsetOfTemporary: is 0-relative" + from: FPReg]. + simSpillBase := index + 1]! - self ssFlushTo: index nativeFlushTo: simNativeStackPtr.! Item was removed: - ----- Method: StackToRegisterMappingCogit>>ssFlushTo:nativeFlushTo: (in category 'simulation stack') ----- - ssFlushTo: index nativeFlushTo: nativeIndex - LowcodeVM ifTrue: - [self ssNativeFlushTo: nativeIndex]. - 0 to: methodOrBlockNumTemps - 1 do: - [:i| self assert: ((self simStackAt: i) type = SSBaseOffset - or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil])]. - methodOrBlockNumTemps to: simSpillBase - 1 do: "simSpillBase and simStackPtr are 0-relative" - [:i| self assert: (self simStackAt: i) spilled]. - simSpillBase <= index ifTrue: - [(simSpillBase max: methodOrBlockNumTemps) to: index do: - [:i| - self assert: needsFrame. - (self simStackAt: i) - ensureSpilledAt: (self frameOffsetOfTemporary: i) - from: FPReg]. - simSpillBase := index + 1]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPop: (in category 'simulation stack') ----- ssPop: n + self assert: (simStackPtr - n >= methodOrBlockNumTemps + or: [(needsFrame not and: [simStackPtr - n >= 0]) - self assert: (simStackPtr - n >= (methodOrBlockNumTemps - 1) - or: [(needsFrame not and: [simStackPtr - n >= -1]) or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil]]). simStackPtr := simStackPtr - n! Item was added: + ----- Method: StackToRegisterMappingCogit>>tempsValidAndVolatileEntriesSpilled (in category 'debugging') ----- + tempsValidAndVolatileEntriesSpilled + "Answer if the stack is valid up to, but not including, simSpillBase." + | culprit | + 1 to: methodOrBlockNumTemps do: + [:i| + ((self simStackAt: i) type = SSBaseOffset + or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil]) ifFalse: + [culprit ifNil: [culprit := i]. + ^false]]. + methodOrBlockNumTemps + 1 to: simSpillBase - 1 do: + [:i| + (self simStackAt: i) spilled ifFalse: + [culprit ifNil: [culprit := i]. + ^false]]. + ^true! Item was changed: ----- Method: StackToRegisterMappingCogit>>traceSimStack (in category 'simulation only') ----- traceSimStack <cmacro: '() 0'> (compilationTrace anyMask: 4) ifTrue: + [self printSimStack]! - [self printOptStatus; printSimSelf; printSimStack]! Item was changed: ----- Method: StackToRegisterMappingCogit>>updateSimSpillBase (in category 'simulation stack') ----- updateSimSpillBase <inline: true> + self assert: (simSpillBase > methodOrBlockNumTemps + or: [inBlock = InVanillaBlock]). simSpillBase > simStackPtr ifTrue: + [simSpillBase := simStackPtr max: methodOrBlockNumTemps].! - [simSpillBase := simStackPtr max: 0].! Item was added: + ----- Method: StackToRegisterMappingCogit>>violatesEnsureSpilledSpillAssert (in category 'testing') ----- + violatesEnsureSpilledSpillAssert + ^true! Item was changed: ----- Method: StackToRegisterMappingCogit>>voidReceiverOptStatus (in category 'bytecode generator support') ----- voidReceiverOptStatus "Used to mark ReceiverResultReg as dead or not containing simSelf. Used when the simStack has already been flushed, e.g. for sends." <inline: true> + self simSelf liveRegister: NoReg! - optStatus isReceiverResultRegLive: false! Item was changed: ----- Method: StackToRegisterMappingCogit>>voidReceiverResultRegContainsSelf (in category 'bytecode generator support') ----- voidReceiverResultRegContainsSelf "Used when ReceiverResultReg is allocated for other than simSelf, and there may be references to ReceiverResultReg which need to be spilled." | spillIndex | self voidReceiverOptStatus. + spillIndex := 0. + (methodOrBlockNumTemps + 1 max: simSpillBase) to: simStackPtr do: - spillIndex := -1. - (methodOrBlockNumTemps max: simSpillBase) to: simStackPtr do: [:i| (self simStackAt: i) registerOrNone = ReceiverResultReg ifTrue: [spillIndex := i]]. spillIndex > 0 ifTrue: [self ssFlushTo: spillIndex]!

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[OpenSmalltalk/opensmalltalk-vm] e668d7: Add DOI Badge
by GitHub 26 Jan '18

26 Jan '18

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: e668d7d2384fbc1524d9ee56d9073908b743dfa2 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/e668d7d2384fbc1524… Author: Tobias Pape <krono(a)users.noreply.github.com> Date: 2018-01-26 (Fri, 26 Jan 2018) Changed paths: M README.md Log Message: ----------- Add DOI Badge Works because of #84

1 0

[OpenSmalltalk/opensmalltalk-vm] 201801252341
by Fabio Niephaus 26 Jan '18

26 Jan '18

-- You are receiving this because you are subscribed to this thread. View it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/releases/tag/201801252341

1 0

[OpenSmalltalk/opensmalltalk-vm]
by GitHub 26 Jan '18

26 Jan '18

Branch: refs/tags/201801252341 Home: https://github.com/OpenSmalltalk/opensmalltalk-vm

1 0

[OpenSmalltalk/opensmalltalk-vm] c90589: Update bintray.json
by GitHub 26 Jan '18

26 Jan '18

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: c9058963d62b8f1aa623d71445a636f30d4eceeb https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/c9058963d62b8f1aa6… Author: Fabio Niephaus <code(a)fniephaus.com> Date: 2018-01-26 (Fri, 26 Jan 2018) Changed paths: M deploy/bintray.json Log Message: ----------- Update bintray.json

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Vm-dev January 2018