Vm-dev April 2017

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44 participants
105 discussions

VM Maker: VMMaker.oscog-eem.2192.mcz
by commits＠source.squeak.org 12 Apr '17

12 Apr '17

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2192.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2192 Author: eem Time: 12 April 2017, 11:55:28.37044 am UUID: 5c76ddfa-fe83-4088-95e0-780dad08ab10 Ancestors: VMMaker.oscog-eem.2191 SiatCogit: Fix mapping errors for genExtStorePopRemoteTemp & genSistaExtStoreAndPopReceiverVariableBytecode. Add some simulatiuon support for ensureAllocatableSlots:, and a shortcut for symbolicMethod:. =============== Diff against VMMaker.oscog-eem.2191 =============== Item was changed: ----- Method: CogVMSimulator>>utilitiesMenu: (in category 'UI') ----- utilitiesMenu: aMenuMorph aMenuMorph add: 'toggle transcript' action: #toggleTranscript; add: 'clone VM' action: #cloneSimulationWindow; addLine; add: 'print ext head frame' action: #printExternalHeadFrame; add: 'print int head frame' action: #printHeadFrame; add: 'print mc/cog head frame' action: [self printFrame: cogit processor fp WithSP: cogit processor sp]; add: 'short print ext head frame & callers' action: [self shortPrintFrameAndCallers: framePointer]; add: 'short print int head frame & callers' action: [self shortPrintFrameAndCallers: localFP]; add: 'short print mc/cog head frame & callers' action: [self shortPrintFrameAndCallers: cogit processor fp]; add: 'long print ext head frame & callers' action: [self printFrameAndCallers: framePointer SP: stackPointer]; add: 'long print int head frame & callers' action: [self printFrameAndCallers: localFP SP: localSP]; add: 'long print mc/cog head frame & callers' action: [self printFrameAndCallers: cogit processor fp SP: cogit processor sp]; add: 'print frame...' action: [(self promptHex: 'print frame') ifNotNil: [:fp| self printFrame: fp]]; add: 'print call stack' action: #printCallStack; add: 'print stack call stack' action: #printStackCallStack; add: 'print stack call stack of...' action: [(self promptHex: 'frame') ifNotNil: [:fp| self printStackCallStackOf: fp]]; add: 'print call stack of...' action: [(self promptHex: 'context or process oop') ifNotNil: [:obj| self printCallStackOf: obj]]; add: 'print call stack of frame...' action: [(self promptHex: 'frame') ifNotNil: [:fp| self printCallStackFP: fp]]; add: 'print all stacks' action: #printAllStacks; add: 'write back local ptrs' action: [stackPointer := localSP. framePointer := localFP. instructionPointer := localIP. self writeBackHeadFramePointers]; add: 'write back mc ptrs' action: [stackPointer := cogit processor sp. framePointer := cogit processor fp. instructionPointer := cogit processor pc. self externalWriteBackHeadFramePointers]; addLine; add: 'print rump C stack' action: [objectMemory printMemoryFrom: cogit processor sp to: cogit getCStackPointer]; add: 'print registers' action: [cogit processor printRegistersOn: transcript]; add: 'print register map' action: [cogit printRegisterMapOn: transcript]; add: 'disassemble method/trampoline...' action: [(self promptHex: 'pc') ifNotNil: [:pc| cogit disassembleCodeAt: pc]]; add: 'disassemble method/trampoline at pc' action: [cogit disassembleCodeAt: (((cogit codeEntryFor: cogit processor pc) isNil and: [(cogit methodZone methodFor: cogit processor pc) = 0]) ifTrue: [instructionPointer] ifFalse: [cogit processor pc])]; add: 'disassemble ext head frame method' action: [cogit disassembleMethod: (self frameMethod: framePointer)]; add: 'print oop...' action: [(self promptHex: 'print oop') ifNotNil: [:oop| self printOop: oop]]; add: 'long print oop...' action: [(self promptHex: 'print oop') ifNotNil: [:oop| self longPrintOop: oop]]; add: 'print context...' action: [(self promptHex: 'print context') ifNotNil: [:oop| self printContext: oop]]; + add: 'symbolic method...' action: [(self promptHex: 'method bytecodes') ifNotNil: [:oop| self symbolicMethod: oop]]; addLine; add: 'inspect object memory' target: objectMemory action: #inspect; add: 'run leak checker' action: [Cursor execute showWhile: [self runLeakChecker]]; add: 'inspect cointerpreter' action: #inspect; add: 'inspect cogit' target: cogit action: #inspect; add: 'inspect method zone' target: cogit methodZone action: #inspect. self isThreadedVM ifTrue: [aMenuMorph add: 'inspect thread manager' target: self threadManager action: #inspect]. aMenuMorph addLine; add: 'print cog methods' target: cogMethodZone action: #printCogMethods; add: 'print cog methods with prim...' action: [(self promptNum: 'prim index') ifNotNil: [:pix| cogMethodZone printCogMethodsWithPrimitive: pix]]; add: 'print cog methods with selector...' action: [|s| s := UIManager default request: 'selector'. s notEmpty ifTrue: [s = 'nil' ifTrue: [s := nil]. cogMethodZone methodsDo: [:m| (s ifNil: [m selector = objectMemory nilObject] ifNotNil: [(objectMemory numBytesOf: m selector) = s size and: [(self str: s n: (m selector + objectMemory baseHeaderSize) cmp: (objectMemory numBytesOf: m selector)) = 0]]) ifTrue: [cogit printCogMethod: m]]]]; add: 'print cog methods with method...' action: [(self promptHex: 'method') ifNotNil: [:methodOop| cogMethodZone methodsDo: [:m| m methodObject = methodOop ifTrue: [cogit printCogMethod: m]]]]; add: 'print cog method for...' action: [(self promptHex: 'pc') ifNotNil: [:pc| cogit printCogMethodFor: pc]]; add: 'print cog method header for...' action: [(self promptHex: 'pc') ifNotNil: [:pc| cogit printCogMethodHeaderFor: pc]]; add: 'print trampoline table' target: cogit action: #printTrampolineTable; add: 'print prim trace log' action: #dumpPrimTraceLog; add: 'report recent instructions' target: cogit action: #reportLastNInstructions; add: (cogit printRegisters ifTrue: ['no print registers each instruction'] ifFalse: ['print registers each instruction']) action: [cogit printRegisters: cogit printRegisters not]; add: (cogit printInstructions ifTrue: ['no print instructions each instruction'] ifFalse: ['print instructions each instruction']) action: [cogit printInstructions: cogit printInstructions not]; addLine; add: (cogit singleStep ifTrue: ['no single step'] ifFalse: ['single step']) action: [cogit singleStep: cogit singleStep not]; add: 'click step' action: [cogit setClickStepBreakBlock]; add: 'set break pc', cogit breakPC menuPrompt, '...-ve to disable or remove' action: [cogit promptForBreakPC]; add: 'set break count...' action: [|s| s := UIManager default request: 'break count (dec)'. s notEmpty ifTrue: [breakCount := Integer readFrom: s readStream]]; add: 'set break selector...' action: [|s| s := UIManager default request: 'break selector'. s notEmpty ifTrue: [self setBreakSelector: s]]; add: 'set break block...' action: [|s| s := UIManager default request: 'break block' initialAnswer: '[:theCogit| false]'. s notEmpty ifTrue: [self setBreakBlockFromString: s]]; add: 'set cogit break method...' action: [(self promptHex: 'cogit breakMethod') ifNotNil: [:bm| cogit setBreakMethod: bm]]; add: (printBytecodeAtEachStep ifTrue: ['no print bytecode each bytecode'] ifFalse: ['print bytecode each bytecode']) action: [self ensureDebugAtEachStepBlock. printBytecodeAtEachStep := printBytecodeAtEachStep not]; add: (printFrameAtEachStep ifTrue: ['no print frame each bytecode'] ifFalse: ['print frame each bytecode']) action: [self ensureDebugAtEachStepBlock. printFrameAtEachStep := printFrameAtEachStep not]. ^aMenuMorph! Item was added: + ----- Method: Spur32BitMMLECoSimulator>>needGCFlag: (in category 'accessing') ----- + needGCFlag: anInteger + needGCFlag := anInteger ~= 0! Item was added: + ----- Method: Spur64BitMMLECoSimulator>>needGCFlag: (in category 'accessing') ----- + needGCFlag: anInteger + needGCFlag := anInteger ~= 0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genExtStorePopRemoteTempOrInstVarLongBytecodePopBoolean: (in category 'bytecode generators') ----- genExtStorePopRemoteTempOrInstVarLongBytecodePopBoolean: boolean | index maybeContext needsStoreCheck needsImmCheck | needsStoreCheck := self sistaNeedsStoreCheck. maybeContext := self extBSpecifiesMaybeContext. needsImmCheck := self extBSpecifiesImmCheck. extB := 0. numExtB := 0. (byte2 noMask: coInterpreter remoteIsInstVarAccess) ifTrue: [ self genStorePop: boolean RemoteTemp: byte1 At: byte2 needsStoreCheck: needsStoreCheck. self cppIf: IMMUTABILITY ifTrue: [ self annotateBytecode: self Label ] ] ifFalse: [index := byte1 + (extA << 8). extA := 0. ((coInterpreter isWriteMediatedContextInstVarIndex: index) and: [ maybeContext ]) ifTrue: [self genStorePop: boolean MaybeContextRemoteInstVar: index ofObjectAt: byte2 - coInterpreter remoteIsInstVarAccess needsStoreCheck: needsStoreCheck needsImmutabilityCheck: needsImmCheck ] ifFalse: [self genStorePop: boolean RemoteInstVar: index ofObjectAt: byte2 - coInterpreter remoteIsInstVarAccess needsStoreCheck: needsStoreCheck + needsImmutabilityCheck: needsImmCheck ]. + self cppIf: IMMUTABILITY ifTrue: [ needsImmCheck ifFalse: [self annotateBytecode: self Label ] ] ]. - needsImmutabilityCheck: needsImmCheck ] ]. ^ 0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genSistaExtStoreAndPopReceiverVariableBytecodePopBoolean: (in category 'bytecode generators') ----- genSistaExtStoreAndPopReceiverVariableBytecodePopBoolean: popBoolean <inline: true> + | index needsStoreCheck needsImmCheck maybeContext result | - | index needsStoreCheck needsImmCheck maybeContext | needsStoreCheck := self sistaNeedsStoreCheck. needsImmCheck := self extBSpecifiesImmCheck. "Long form and short form exist for popInto. Only the long form exists for store. Store have an explicit flag to mark context accessing, while popInto context accessing are done through the long form, hence generate the context form if the flag is set or if this is a popInto." maybeContext := popBoolean or: [self extBSpecifiesMaybeContext]. extB := 0. numExtB := 0. index := byte1 + (extA << 8). extA := 0. + result := ((coInterpreter isWriteMediatedContextInstVarIndex: index) and: [maybeContext]) - ^((coInterpreter isWriteMediatedContextInstVarIndex: index) and: [maybeContext]) ifTrue: [self genStorePop: popBoolean MaybeContextReceiverVariable: index needsStoreCheck: needsStoreCheck needsImmutabilityCheck: needsImmCheck] ifFalse: [self genStorePop: popBoolean ReceiverVariable: index needsStoreCheck: needsStoreCheck + needsImmutabilityCheck: needsImmCheck]. + self cppIf: IMMUTABILITY ifTrue: [ needsImmCheck ifFalse: [self annotateBytecode: self Label ] ]. + ^result! - needsImmutabilityCheck: needsImmCheck]!

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[VM-dev] How serialize/materialize SmallFloat64?
by Denis Kudriashov 12 Apr '17

12 Apr '17

I tested my serialization library on 64bits image and tests for floats are failed. For boxed floats I use #basicNew. And SmallFloat signal error 'SmallFloat64s can only be created by performing arithmetic' So question how implement smallfloat serialization/materialization ? Do we have something similar to ByteArray>>asInteger and SmallInteger>>asByteArray? Best regards, Denis

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VM Maker: VMMaker.oscog-eem.2191.mcz
by commits＠source.squeak.org 12 Apr '17

12 Apr '17

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2191.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2191 Author: eem Time: 12 April 2017, 9:44:27.279512 am UUID: d1e0c31d-4650-4976-b685-7746035e025e Ancestors: VMMaker.oscog-eem.2190 SistaVI Cogit: Fix a slip in genExtEnsureAllocatableSlots; get the branch sense right. Implement glue to access cogCodeZoneThreshold & needGCFlagAddress. Fix receiver for integerObjectOf: in primitiveVMParameter. =============== Diff against VMMaker.oscog-eem.2190 =============== Item was added: + ----- Method: CoInterpreter>>needGCFlagAddress (in category 'accessing') ----- + needGCFlagAddress + <doNotGenerate> + ^objectMemory needGCFlagAddress! Item was changed: ----- Method: SimpleStackBasedCogit>>genExtEnsureAllocatableSlots (in category 'bytecode generators') ----- genExtEnsureAllocatableSlots "SistaV1 * 236 11101100 iiiiiiii Ensure Allocatable Slots (+ Extend A * 256)" | slots skip | slots := (extA bitShift: 8) + byte1. extA := 0. self MoveAw: objectMemory freeStartAddress R: TempReg; CmpCq: objectMemory getScavengeThreshold - (objectMemory bytesPerOop * slots) R: TempReg. + skip := self JumpBelow: 0. - skip := self JumpAboveOrEqual: 0. objectRepresentation genSetGCNeeded. self CallRT: ceCheckForInterruptTrampoline. skip jmpTarget: self Label. self annotateBytecode: skip getJmpTarget. ^0! Item was added: + ----- Method: SistaCogit>>getCogCodeZoneThreshold (in category 'accessing') ----- + getCogCodeZoneThreshold + <doNotGenerate> + ^methodZone getCogCodeZoneThreshold! Item was changed: ----- Method: StackInterpreterPrimitives>>primitiveVMParameter (in category 'system control primitives') ----- (excessive size, no diff calculated)

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[OpenSmalltalk/opensmalltalk-vm] 855dd0: revert to ugly define because exeName is not prese...
by GitHub 12 Apr '17

12 Apr '17

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 855dd0f37d308f6d19bf50a5c3732a239c550a35 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/855dd0f37d308f6d19… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2017-04-12 (Wed, 12 Apr 2017) Changed paths: M platforms/unix/vm/sqUnixHeartbeat.c Log Message: ----------- revert to ugly define because exeName is not present in all platforms Commit: 1be1bf987fee75f9a5739c2b3b94452c5e2cf8a4 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/1be1bf987fee75f9a5… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2017-04-12 (Wed, 12 Apr 2017) Changed paths: M platforms/unix/vm/sqUnixHeartbeat.c Log Message: ----------- Merge pull request #133 from estebanlm/CogLatestTree revert to ugly define because exeName is not present in all platforms Compare: https://github.com/OpenSmalltalk/opensmalltalk-vm/compare/0e1fc3adf468...1b…

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vm executable name
by K K Subbu 12 Apr '17

12 Apr '17

Hi, The current practice of building all VMs (squeak, stack, cog, spur, ...) with the same executable name ("squeak") is complicating the task of building mimetypes, desktop launchers and binfmt auto loaders for different image files. This overuse is leading to layers of wrapper scripts to disambiguate and match VMs to image files. An image is an executable file and it shouldn't be this hard to start it. I propose that the executable 'squeak' be reserved for the classic VM only and use names like stack, cog, spur etc. for the newer VMs that use a different image format. If later, cog evolves to handle older image formats, then we can always copy (or link) it to 'squeak' name and have cog check for 'squeak' in its argv[0] to turn on backward compatibility mode. If a newer VM cannot execute a magic file, then it should not share the same name as the older VM which does execute it. Regards .. Subbu

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Idle time and sleep/wake notification
by Eliot Miranda 12 Apr '17

12 Apr '17

Hi All, I've just added tallying of idle time in the VM so that the system report can give more meaningful overheads to the GC information it reports. Currently the VM tallies idle time in the innards of relinquishProcessorForMicroseconds:. But it also needs to tally idle time across SLEEP/WAKE events. May I ask experts in the Mac OS, X11 and Windows worlds to have a loop at event processing and either implement tallying idle time here or reporting back on what work is required or (as I fear in the case of X11/Unix) whether it is unsupported. Here's an example of the nonsense one gets back after waking one's laptop: Virtual Machine Statistics -------------------------- uptime 14h 59m 26s (runtime 11h 53m 33s, idletime 3h 5m 53s) memory 338,690,048 bytes old 333,689,744 bytes (98.5%) young 4,111,360 bytes (1.2%) used 314,964,392 bytes (93%) free 21,991,672 bytes (6.5%) GCs 3,430 (15733.6 ms between GCs 12482 ms runtime between GCs) full 8 totalling 1,331 ms (0% runtime), avg 166.4 ms marking 536 ms (40.3%) avg 67 ms, compacting 795 ms (59.7%) avg 99.4 ms scavenges 3,422 totalling 2,511 ms (0.01% runtime), avg 0.7 ms tenures 818,889 (avg 239 tenures per scavenge) Since last view 2,463 (21394 ms between GCs, 17285 ms runtime between GCs) uptime 52695.2 s, runtime 42574 s, idletime 10121.2 s full 2 totalling 322 ms (0% runtime), avg 161 ms scavenge 2,461 totalling 2,029 ms (0% runtime), avg 0.8 ms tenures 16,733 (avg 6 tenures per scavenge) whereas while the machine stays awake we get good information: Virtual Machine Statistics -------------------------- uptime 1m 58s (runtime 0m 21s, idletime 1m 37s) memory 281,018,368 bytes old 276,018,064 bytes (98.2%) young 4,111,360 bytes (1.5%) used 251,951,208 bytes (89.7%) free 26,712,592 bytes (9.5%) GCs 37 (3203.5 ms between GCs 569.7 ms runtime between GCs) full 0 totalling 0 ms (0% runtime), avg 0 ms scavenges 37 totalling 13 ms (0.06% runtime), avg 0.4 ms tenures 648 (avg 17 tenures per scavenge) Since last view 30 (3498 ms between GCs, 590 ms runtime between GCs) uptime 104.9 s, runtime 17.7 s, idletime 87.2 s full 0 scavenge 30 totalling 11 ms (0.1% runtime), avg 0.4 ms tenures 0 _,,,^..^,,,_ best, Eliot

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Unix heartbeat thread vs itimer
by Guillermo Polito 12 Apr '17

12 Apr '17

Hi, I was checking the code in sqUnixHeartbeat.c to see how the heartbeat thread/itimer worked. It somehow bothers me that there are different compiled artifacts, one per option. What do you think about having a VM that manages that as an argument provided when we launch the VM? This would add some flexibility that we don't have right now because we make the decision at compile time. The code in sqUnixHeartbeat.c is not a lot nor very complex, it should not be difficult to do... Also, what would be the drawbacks besides an increase on the vm size? Guille

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VM Maker: VMMaker.oscog-eem.2190.mcz
by commits＠source.squeak.org 12 Apr '17

12 Apr '17

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2190.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2190 Author: eem Time: 11 April 2017, 5:52:10.631026 pm UUID: 7752b22c-922c-4063-88f7-d8ee8a016cb6 Ancestors: VMMaker.oscog-eem.2189 Sista Cogit: Implement ensureAllocatableSlots: support. RegisterAllocatingCogit: liveRegisters must work in frameless methods. Fix yet another methodOrBlockNumArgs/Temps mixup (this time in an assert). Add assertCorrectSimStackPtr and revert StackToRegisterMappingCogit's one; duplicateRegisterAssignmentsInTemporaries is a RegisterAllocatingCogit thang.. Misc: Eliminate some breaks left in various methods by mistake. =============== Diff against VMMaker.oscog-eem.2189 =============== Item was changed: ----- Method: CogObjectRepresentationForSpur>>genGetInstanceOf:into:initializingIf: (in category 'bytecode generator support') ----- genGetInstanceOf: classObj into: destReg initializingIf: initializeInstance "Create an instance of classObj and assign it to destReg, initializing the instance if initializeInstance is true with nil or 0 as appropriate This is for inline primitives. Assume there is sufficient space in new space to complete the operation. Answer zero on success." | classIndex classFormat header slots | ((objectMemory isNonImmediate: classObj) and: [(coInterpreter objCouldBeClassObj: classObj) and: [(classIndex := objectMemory rawHashBitsOf: classObj) ~= 0 and: [(objectMemory isFixedSizePointerFormat: (objectMemory instSpecOfClassFormat: (classFormat := objectMemory formatOfClass: classObj))) and: [(slots := objectMemory fixedFieldsOfClassFormat: classFormat) < objectMemory numSlotsMask]]]]) ifFalse: [^UnimplementedOperation]. + self deny: destReg = TempReg. + header := objectMemory headerForSlots: slots format: (objectMemory instSpecOfClassFormat: classFormat) classIndex: classIndex. cogit MoveAw: objectMemory freeStartAddress R: destReg. self genStoreHeader: header intoNewInstance: destReg using: TempReg. cogit LoadEffectiveAddressMw: (objectMemory smallObjectBytesForSlots: slots) r: destReg R: TempReg; MoveR: TempReg Aw: objectMemory freeStartAddress. (initializeInstance and: [slots > 0]) ifTrue: [cogit genMoveConstant: objectMemory nilObject R: TempReg. 0 to: slots - 1 do: [:i| cogit MoveR: TempReg Mw: i * objectMemory wordSize + objectMemory baseHeaderSize r: destReg]]. ^0! Item was added: + ----- Method: CogObjectRepresentationForSpur>>genSetGCNeeded (in category 'bytecode generator support') ----- + genSetGCNeeded + <inline: true> + cogit + MoveCq: 1 R: TempReg; + MoveR: TempReg Aw: coInterpreter needGCFlagAddress! Item was added: + ----- Method: CurrentImageCoInterpreterFacadeForSpurObjectRepresentation>>needGCFlagAddress (in category 'accessing') ----- + needGCFlagAddress + ^self addressForLabel: #needGCFlag! Item was added: + ----- Method: CurrentImageCoInterpreterFacadeForSpurObjectRepresentation>>scavengeThreshold (in category 'accessing') ----- + scavengeThreshold + ^objectMemory scavengeThreshold! Item was changed: ----- Method: InterpreterPrimitives>>sHEAFn (in category 'simulation support') ----- sHEAFn <doNotGenerate> - self break. ^true! Item was added: + ----- Method: RegisterAllocatingCogit>>assertCorrectSimStackPtr (in category 'compile abstract instructions') ----- + assertCorrectSimStackPtr + <inline: true> "generates nothing anyway" + self cCode: '' inSmalltalk: + [deadCode ifFalse: + [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) + = (self debugStackPointerFor: bytecodePC)]. + self deny: self duplicateRegisterAssignmentsInTemporaries]. + ! Item was changed: ----- Method: RegisterAllocatingCogit>>liveRegisters (in category 'simulation stack') ----- liveRegisters | regsSet | + needsFrame + ifTrue: [regsSet := 0] + ifFalse: + [regsSet := (methodOrBlockNumArgs > self numRegArgs + or: [methodOrBlockNumArgs = 0]) + ifTrue: + [self registerMaskFor: ReceiverResultReg] + ifFalse: + [(self numRegArgs > 1 and: [methodOrBlockNumArgs > 1]) + ifFalse: [self registerMaskFor: ReceiverResultReg and: Arg0Reg] + ifTrue: [self registerMaskFor: ReceiverResultReg and: Arg0Reg and: Arg1Reg]]]. - self assert: needsFrame. - regsSet := 0. 0 to: simStackPtr do: [:i| regsSet := regsSet bitOr: (self simStackAt: i) registerMask]. LowcodeVM ifTrue: [(simNativeSpillBase max: 0) to: simNativeStackPtr do: [:i| regsSet := regsSet bitOr: (self simNativeStackAt: i) nativeRegisterMask]]. ^regsSet! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith:forwards: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup forwards: forwards "At a merge point the cogit expects the stack to be in the same state as mergeSimStack. mergeSimStack is the state as of some jump forward or backward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. The state of optStatus must agree. Generate code to merge the current simStack with that of the target fixup, the goal being to keep as many registers live as possible. If the merge is forwards registers can be deassigned (since registers are always written to temp vars). But if backwards, nothing can be deassigned, and the state /must/ reflect the target." "self printSimStack; printSimStack: fixup mergeSimStack" "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" <var: #fixup type: #'BytecodeFixup *'> | startIndex mergeSimStack currentEntry targetEntry writtenToRegisters | <var: #mergeSimStack type: #'SimStackEntry *'> <var: #targetEntry type: #'SimStackEntry *'> <var: #currentEntry type: #'SimStackEntry *'> (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. startIndex := opcodeIndex. "for debugging" "Assignments amongst the registers must be made in order to avoid overwriting. If necessary exchange registers amongst simStack's entries to resolve any conflicts." self resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: mergeSimStack. (self asserta: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack)) ifFalse: [Notification new tag: #failedMerge; signal]. "Compute written to registers. Perhaps we should use 0 in place of methodOrBlockNumTemps but Smalltalk does not assign to arguments." writtenToRegisters := 0. (self pushForMergeWith: mergeSimStack) ifTrue: [methodOrBlockNumTemps to: simStackPtr do: [:i| currentEntry := self simStack: simStack at: i. targetEntry := self simStack: mergeSimStack at: i. writtenToRegisters := writtenToRegisters bitOr: targetEntry registerMask. (currentEntry reconcileForwardsWith: targetEntry) ifTrue: [self assert: i >= methodOrBlockNumTemps. self deassignRegisterForTempVar: targetEntry in: mergeSimStack. targetEntry type: SSRegister; register: targetEntry liveRegister]. "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: spilled ifFalse: [simSpillBase := i - 1]. simStack at: i put: (self cCode: [mergeSimStack at: i] inSmalltalk: [(mergeSimStack at: i) copy])"]] ifFalse: [simStackPtr to: methodOrBlockNumTemps by: -1 do: [:i| currentEntry := self simStack: simStack at: i. targetEntry := self simStack: mergeSimStack at: i. writtenToRegisters := writtenToRegisters bitOr: targetEntry registerMask. (currentEntry reconcileForwardsWith: targetEntry) ifTrue: [self assert: i >= methodOrBlockNumTemps. self deassignRegisterForTempVar: targetEntry in: mergeSimStack. targetEntry type: SSRegister; register: targetEntry liveRegister]. "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: spilled ifFalse: [simSpillBase := i - 1]. simStack at: i put: (self cCode: [mergeSimStack at: i] inSmalltalk: [(mergeSimStack at: i) copy])"]]. "Note that since we've deassigned any conflicts beyond the temps above we need only compare the temps here." methodOrBlockNumTemps - 1 to: 0 by: -1 do: [:i| targetEntry := self simStack: mergeSimStack at: i. (targetEntry registerMask noMask: writtenToRegisters) ifTrue: [currentEntry := self simStack: simStack at: i. writtenToRegisters := writtenToRegisters bitOr: targetEntry registerMask. (currentEntry reconcileForwardsWith: targetEntry) ifTrue: + [self assert: i >= methodOrBlockNumTemps. - [self assert: i >= methodOrBlockNumArgs. self deassignRegisterForTempVar: targetEntry in: mergeSimStack]]]. optStatus isReceiverResultRegLive ifFalse: [forwards ifTrue: "a.k.a. fixup isReceiverResultRegSelf: (fixup isReceiverResultRegSelf and: [optStatus isReceiverResultRegLive])" [fixup isReceiverResultRegSelf: false] ifFalse: [fixup isReceiverResultRegSelf ifTrue: [self putSelfInReceiverResultReg]]]! Item was added: + ----- Method: SimpleStackBasedCogit>>genExtEnsureAllocatableSlots (in category 'bytecode generators') ----- + genExtEnsureAllocatableSlots + "SistaV1 * 236 11101100 iiiiiiii Ensure Allocatable Slots (+ Extend A * 256)" + | slots skip | + slots := (extA bitShift: 8) + byte1. + extA := 0. + self + MoveAw: objectMemory freeStartAddress R: TempReg; + CmpCq: objectMemory getScavengeThreshold - (objectMemory bytesPerOop * slots) R: TempReg. + skip := self JumpAboveOrEqual: 0. + objectRepresentation genSetGCNeeded. + self CallRT: ceCheckForInterruptTrampoline. + skip jmpTarget: self Label. + self annotateBytecode: skip getJmpTarget. + ^0! Item was changed: ----- Method: SistaCogit>>genBinaryConstOpVarInlinePrimitive: (in category 'inline primitive generators') ----- genBinaryConstOpVarInlinePrimitive: prim "Const op var version of binary inline primitives." "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution. See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:" <option: #SistaVM> | ra val untaggedVal adjust | ra := self allocateRegForStackEntryAt: 0. self ssTop popToReg: ra. self ssPop: 1. val := self ssTop constant. self ssPop: 1. untaggedVal := val - objectMemory smallIntegerTag. prim caseOf: { "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow" [0] -> [self AddCq: untaggedVal R: ra]. [1] -> [self MoveCq: val R: TempReg. self SubR: ra R: TempReg. objectRepresentation genAddSmallIntegerTagsTo: TempReg. self MoveR: TempReg R: ra]. [2] -> [objectRepresentation genShiftAwaySmallIntegerTagsInScratchReg: ra. self MoveCq: untaggedVal R: TempReg. self MulR: TempReg R: ra. objectRepresentation genSetSmallIntegerTagsIn: ra]. + "2011 through 2015 Variable-sized pointers new, byte new, 16-bit new, 32-bit new, 64-bit new" + "2016 through 2020, bitAnd:, bitOr:, bitXor, bitShiftLeft:, bitShiftRight:, SmallInteger op SmallInteger => SmallInteger, no overflow" [16] -> [ self AndCq: val R: ra ]. [17] -> [ self OrCq: val R: ra ]. [18] -> [ self XorCw: untaggedVal R: ra. ]. [19] -> [ objectRepresentation genConvertSmallIntegerToIntegerInReg: ra. self MoveCq: untaggedVal R: TempReg. self LogicalShiftLeftR: ra R: TempReg. objectRepresentation genAddSmallIntegerTagsTo: TempReg. self MoveR: TempReg R: ra]. [20] -> [objectRepresentation genConvertSmallIntegerToIntegerInReg: ra. self MoveCq: untaggedVal R: TempReg. self ArithmeticShiftRightR: ra R: TempReg. objectRepresentation genClearAndSetSmallIntegerTagsIn: TempReg. self MoveR: TempReg R: ra]. "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)" "CmpCqR is SubRCq so everything is reversed, but because no CmpRCq things are reversed again and we invert the sense of the jumps." [32] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpLess opFalse: JumpGreaterOrEqual destReg: ra ]. [33] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpGreater opFalse: JumpLessOrEqual destReg: ra ]. [34] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpLessOrEqual opFalse: JumpGreater destReg: ra ]. [35] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpGreaterOrEqual opFalse: JumpLess destReg: ra ]. [36] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpZero opFalse: JumpNonZero destReg: ra ]. [37] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpNonZero opFalse: JumpZero destReg: ra ]. "2064 through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop" [64] -> [objectRepresentation genConvertSmallIntegerToIntegerInReg: ra. adjust := (objectMemory baseHeaderSize >> objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" adjust ~= 0 ifTrue: [ self AddCq: adjust R: ra. ]. self genMoveConstant: val R: TempReg. self MoveXwr: ra R: TempReg R: ra]. [65] -> [objectRepresentation genConvertSmallIntegerToIntegerInReg: ra. adjust := objectMemory baseHeaderSize - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" self AddCq: adjust R: ra. self genMoveConstant: val R: TempReg. self MoveXbr: ra R: TempReg R: ra. objectRepresentation genConvertIntegerToSmallIntegerInReg: ra] } otherwise: [^EncounteredUnknownBytecode]. self ssPushRegister: ra. ^0! Item was changed: ----- Method: SistaMethodZone>>setCogCodeZoneThreshold: (in category 'accessing') ----- setCogCodeZoneThreshold: ratio <api> <var: #ratio type: #double> - self break. (ratio >= 0.1 and: [ratio <= 1.0]) ifFalse: [^PrimErrBadArgument]. thresholdRatio := ratio. self computeAllocationThreshold. ^0! Item was added: + ----- Method: Spur32BitCoMemoryManager>>needGCFlagAddress (in category 'trampoline support') ----- + needGCFlagAddress + <api> + <returnTypeC: #usqInt> + ^self cCode: [(self addressOf: needGCFlag) asUnsignedInteger] + inSmalltalk: [cogit simulatedReadWriteVariableAddress: #needGCFlag in: self]! Item was added: + ----- Method: Spur64BitCoMemoryManager>>needGCFlagAddress (in category 'trampoline support') ----- + needGCFlagAddress + <api> + <returnTypeC: #usqInt> + ^self cCode: [(self addressOf: needGCFlag) asUnsignedInteger] + inSmalltalk: [cogit simulatedReadWriteVariableAddress: #needGCFlag in: self]! Item was added: + ----- Method: SpurMemoryManager>>checkForAvailableSlots: (in category 'gc - scavenging') ----- + checkForAvailableSlots: slots + "Check for slots worth of free space being available. Answer if that many slots are available. + If that many slots are not availabe, schedule a scavenge." + <inline: true> + freeStart + (self bytesPerOop * slots) <= scavengeThreshold ifTrue: + [^true]. + needGCFlag := true. + ^false! Item was added: + ----- Method: StackDepthFinder>>ensureAllocateableSlots: (in category 'as yet unclassified') ----- + ensureAllocateableSlots: numSlots + "nothing to do here..."! Item was changed: ----- Method: StackInterpreter class>>initializeBytecodeTableForSistaV1 (in category 'initialization') ----- initializeBytecodeTableForSistaV1 "See e.g. the cass comment for EncoderForSistaV1" "StackInterpreter initializeBytecodeTableForSistaV1" "Note: This table will be used to generate a C switch statement." initializationOptions at: #SistaV1BytecodeSet put: (SistaV1BytecodeSet := true). BytecodeTable := Array new: 256. BytecodeEncoderClassName := #EncoderForSistaV1. BytecodeSetHasDirectedSuperSend := true. BytecodeSetHasExtensions := true. LongStoreBytecode := 245. self table: BytecodeTable from: #( "1 byte bytecodes" ( 0 15 pushReceiverVariableBytecode) ( 16 31 pushLiteralVariable16CasesBytecode) ( 32 63 pushLiteralConstantBytecode) ( 64 75 pushTemporaryVariableBytecode) ( 76 pushReceiverBytecode) ( 77 pushConstantTrueBytecode) ( 78 pushConstantFalseBytecode) ( 79 pushConstantNilBytecode) ( 80 pushConstantZeroBytecode) ( 81 pushConstantOneBytecode) ( 82 extPushPseudoVariable) ( 83 duplicateTopBytecode) ( 84 87 unknownBytecode) ( 88 returnReceiver) ( 89 returnTrue) ( 90 returnFalse) ( 91 returnNil) ( 92 returnTopFromMethod) ( 93 returnNilFromBlock) ( 94 returnTopFromBlock) ( 95 extNopBytecode) ( 96 bytecodePrimAdd) ( 97 bytecodePrimSubtract) ( 98 bytecodePrimLessThanSistaV1) "for booleanCheatSistaV1:" ( 99 bytecodePrimGreaterThanSistaV1) "for booleanCheatSistaV1:" (100 bytecodePrimLessOrEqualSistaV1) "for booleanCheatSistaV1:" (101 bytecodePrimGreaterOrEqualSistaV1) "for booleanCheatSistaV1:" (102 bytecodePrimEqualSistaV1) "for booleanCheatSistaV1:" (103 bytecodePrimNotEqualSistaV1) "for booleanCheatSistaV1:" (104 bytecodePrimMultiply) (105 bytecodePrimDivide) (106 bytecodePrimMod) (107 bytecodePrimMakePoint) (108 bytecodePrimBitShift) (109 bytecodePrimDiv) (110 bytecodePrimBitAnd) (111 bytecodePrimBitOr) (112 bytecodePrimAt) (113 bytecodePrimAtPut) (114 bytecodePrimSize) (115 bytecodePrimNext) "i.e. a 0 arg special selector" (116 bytecodePrimNextPut) "i.e. a 1 arg special selector" (117 bytecodePrimAtEnd) (118 bytecodePrimIdenticalSistaV1) "for booleanCheatSistaV1:" (119 bytecodePrimClass) (120 bytecodePrimNotIdenticalSistaV1) "was blockCopy:" (121 bytecodePrimValue) (122 bytecodePrimValueWithArg) (123 bytecodePrimDo) "i.e. a 1 arg special selector" (124 bytecodePrimNew) "i.e. a 0 arg special selector" (125 bytecodePrimNewWithArg) "i.e. a 1 arg special selector" (126 bytecodePrimPointX) "i.e. a 0 arg special selector" (127 bytecodePrimPointY) "i.e. a 0 arg special selector" (128 143 sendLiteralSelector0ArgsBytecode) (144 159 sendLiteralSelector1ArgBytecode) (160 175 sendLiteralSelector2ArgsBytecode) (176 183 shortUnconditionalJump) (184 191 shortConditionalJumpTrue) (192 199 shortConditionalJumpFalse) (200 207 storeAndPopReceiverVariableBytecode) (208 215 storeAndPopTemporaryVariableBytecode) (216 popStackBytecode) (217 unconditionnalTrapBytecode) (218 223 unknownBytecode) "2 byte bytecodes" (224 extABytecode) (225 extBBytecode) (226 extPushReceiverVariableBytecode) (227 extPushLiteralVariableBytecode) (228 extPushLiteralBytecode) (229 longPushTemporaryVariableBytecode) (230 unknownBytecode) (231 pushNewArrayBytecode) (232 extPushIntegerBytecode) (233 extPushCharacterBytecode) (234 extSendBytecode) (235 extSendSuperBytecode) + (236 extEnsureAllocatableSlots) - (236 unknownBytecode) (237 extUnconditionalJump) (238 extJumpIfTrue) (239 extJumpIfFalse) (240 extSistaStoreAndPopReceiverVariableBytecode) (241 extSistaStoreAndPopLiteralVariableBytecode) (242 longStoreAndPopTemporaryVariableBytecode) (243 extSistaStoreReceiverVariableBytecode) (244 extSistaStoreLiteralVariableBytecode) (245 longStoreTemporaryVariableBytecode) (246 247 unknownBytecode) "3 byte bytecodes" (248 callPrimitiveBytecode) (249 extPushFullClosureBytecode) (250 extPushClosureBytecode) (251 extPushRemoteTempOrInstVarLongBytecode) (252 extStoreRemoteTempOrInstVarLongBytecode) (253 extStoreAndPopRemoteTempOrInstVarLongBytecode) (254 extJumpIfNotInstanceOfBehaviorsBytecode) (255 unknownBytecode) )! Item was added: + ----- Method: StackInterpreter>>extEnsureAllocatableSlots (in category 'miscellaneous bytecodes') ----- + extEnsureAllocatableSlots + "SistaV1 * 236 11101100 iiiiiiii Ensure Allocatable Slots (+ Extend A * 256)" + | slots ok | + slots := (extA bitShift: 8) + self fetchByte. + self fetchNextBytecode. + extA := 0. + ok := objectMemory checkForAvailableSlots: slots. + ok ifFalse: + [self externalizeIPandSP. + self checkForEventsMayContextSwitch: true. + self browserPluginReturnIfNeeded. + self internalizeIPandSP]! Item was changed: ----- Method: StackToRegisterMappingCogit class>>initializeBytecodeTableForSistaV1 (in category 'class initialization') ----- initializeBytecodeTableForSistaV1 "StackToRegisterMappingCogit initializeBytecodeTableForSistaV1" numPushNilsFunction := #sistaV1:Num:Push:Nils:. pushNilSizeFunction := #sistaV1PushNilSize:numInitialNils:. BytecodeSetHasDirectedSuperSend := true. FirstSpecialSelector := 96. NumSpecialSelectors := 32. self flag: 'Special selector send class must be inlined to agree with the interpreter, which inlines class. If class is sent to e.g. a general instance of ProtoObject then unless class is inlined there will be an MNU. It must be that the Cointerpreter and Cogit have identical semantics. We get away with not hardwiring the other special selectors either because in the Cointerpreter they are not inlined or because they are inlined only to instances of classes for which there will always be a method.'. self generatorTableFrom: #( "1 byte bytecodes" "pushes" (1 0 15 genPushReceiverVariableBytecode isInstVarRef needsFrameNever: 1) (1 16 31 genPushLitVarDirSup16CasesBytecode needsFrameNever: 1) (1 32 63 genPushLiteralConstantBytecode needsFrameNever: 1) (1 64 75 genPushTemporaryVariableBytecode needsFrameIfMod16GENumArgs: 1) (1 76 76 genPushReceiverBytecode needsFrameNever: 1) (1 77 77 genPushConstantTrueBytecode needsFrameNever: 1) (1 78 78 genPushConstantFalseBytecode needsFrameNever: 1) (1 79 79 genPushConstantNilBytecode needsFrameNever: 1) (1 80 80 genPushConstantZeroBytecode needsFrameNever: 1) (1 81 81 genPushConstantOneBytecode needsFrameNever: 1) (1 82 82 genExtPushPseudoVariable) (1 83 83 duplicateTopBytecode needsFrameNever: 1) (1 84 87 unknownBytecode) "returns" (1 88 88 genReturnReceiver return needsFrameIfInBlock: isMappedInBlock 0) (1 89 89 genReturnTrue return needsFrameIfInBlock: isMappedInBlock 0) (1 90 90 genReturnFalse return needsFrameIfInBlock: isMappedInBlock 0) (1 91 91 genReturnNil return needsFrameIfInBlock: isMappedInBlock 0) (1 92 92 genReturnTopFromMethod return needsFrameIfInBlock: isMappedInBlock -1) (1 93 93 genReturnNilFromBlock return needsFrameNever: -1) (1 94 94 genReturnTopFromBlock return needsFrameNever: -1) (1 95 95 genExtNopBytecode needsFrameNever: 0) "sends" (1 96 96 genSpecialSelectorArithmetic isMapped AddRR) (1 97 97 genSpecialSelectorArithmetic isMapped SubRR) (1 98 98 genSpecialSelectorComparison isMapped JumpLess) (1 99 99 genSpecialSelectorComparison isMapped JumpGreater) (1 100 100 genSpecialSelectorComparison isMapped JumpLessOrEqual) (1 101 101 genSpecialSelectorComparison isMapped JumpGreaterOrEqual) (1 102 102 genSpecialSelectorComparison isMapped JumpZero) (1 103 103 genSpecialSelectorComparison isMapped JumpNonZero) (1 104 109 genSpecialSelectorSend isMapped) " #* #/ #\\ #@ #bitShift: //" (1 110 110 genSpecialSelectorArithmetic isMapped AndRR) (1 111 111 genSpecialSelectorArithmetic isMapped OrRR) (1 112 117 genSpecialSelectorSend isMapped) "#at: #at:put: #size #next #nextPut: #atEnd" (1 118 118 genSpecialSelectorEqualsEquals needsFrameNever: notMapped -1) "not mapped because it is directly inlined (for now)" (1 119 119 genSpecialSelectorClass needsFrameIfStackGreaterThanOne: notMapped 0) "not mapped because it is directly inlined (for now)" (1 120 120 genSpecialSelectorNotEqualsEquals needsFrameNever: notMapped -1) "not mapped because it is directly inlined (for now)" (1 121 127 genSpecialSelectorSend isMapped) "#value #value: #do: #new #new: #x #y" (1 128 143 genSendLiteralSelector0ArgsBytecode isMapped) (1 144 159 genSendLiteralSelector1ArgBytecode isMapped) (1 160 175 genSendLiteralSelector2ArgsBytecode isMapped) "jumps" (1 176 183 genShortUnconditionalJump branch v3:ShortForward:Branch:Distance:) (1 184 191 genShortJumpIfTrue branch isBranchTrue isMapped "because of mustBeBoolean" v3:ShortForward:Branch:Distance:) (1 192 199 genShortJumpIfFalse branch isBranchFalse isMapped "because of mustBeBoolean" v3:ShortForward:Branch:Distance:) (1 200 207 genStoreAndPopReceiverVariableBytecode isInstVarRef is1ByteInstVarStore isMappedIfImmutability needsFrameIfImmutability: -1) (1 208 215 genStoreAndPopTemporaryVariableBytecode) (1 216 216 genPopStackBytecode needsFrameNever: -1) (1 217 217 genUnconditionalTrapBytecode isMapped) (1 218 223 unknownBytecode) "2 byte bytecodes" (2 224 224 extABytecode extension) (2 225 225 extBBytecode extension) "pushes" (2 226 226 genExtPushReceiverVariableBytecode isInstVarRef) "Needs a frame for context inst var access" (2 227 227 genExtPushLitVarDirSupBytecode needsFrameNever: 1) (2 228 228 genExtPushLiteralBytecode needsFrameNever: 1) (2 229 229 genLongPushTemporaryVariableBytecode) (2 230 230 unknownBytecode) (2 231 231 genPushNewArrayBytecode) (2 232 232 genExtPushIntegerBytecode needsFrameNever: 1) (2 233 233 genExtPushCharacterBytecode needsFrameNever: 1) "returns" "sends" (2 234 234 genExtSendBytecode isMapped) (2 235 235 genExtSendSuperBytecode isMapped) "sista bytecodes" + (2 236 236 genExtEnsureAllocatableSlots isMapped) - (2 236 236 unknownBytecode) "jumps" (2 237 237 genExtUnconditionalJump branch isMapped "because of interrupt check" v4:Long:Branch:Distance:) (2 238 238 genExtJumpIfTrue branch isBranchTrue isMapped "because of mustBeBoolean" v4:Long:Branch:Distance:) (2 239 239 genExtJumpIfFalse branch isBranchFalse isMapped "because of mustBeBoolean" v4:Long:Branch:Distance:) "stores" (2 240 240 genSistaExtStoreAndPopReceiverVariableBytecode isInstVarRef isMappedIfImmutability) (2 241 241 genSistaExtStoreAndPopLiteralVariableBytecode isMappedIfImmutability) (2 242 242 genLongStoreAndPopTemporaryVariableBytecode) (2 243 243 genSistaExtStoreReceiverVariableBytecode isInstVarRef isMappedIfImmutability) (2 244 244 genSistaExtStoreLiteralVariableBytecode isMappedIfImmutability) (2 245 245 genLongStoreTemporaryVariableBytecode) (2 246 247 unknownBytecode) "3 byte bytecodes" (3 248 248 genCallPrimitiveBytecode) (3 249 249 genExtPushFullClosureBytecode) (3 250 250 genExtPushClosureBytecode block v4:Block:Code:Size:) (3 251 251 genExtPushRemoteTempOrInstVarLongBytecode) (3 252 252 genExtStoreRemoteTempOrInstVarLongBytecode isMappedIfImmutability) (3 253 253 genExtStoreAndPopRemoteTempOrInstVarLongBytecode isMappedIfImmutability) (3 254 254 genExtJumpIfNotInstanceOfBehaviorsBytecode branch v4:Long:BranchIfNotInstanceOf:Distance:) (3 255 255 unknownBytecode))! Item was changed: ----- Method: StackToRegisterMappingCogit>>assertCorrectSimStackPtr (in category 'compile abstract instructions') ----- assertCorrectSimStackPtr <inline: true> "generates nothing anyway" self cCode: '' inSmalltalk: [deadCode ifFalse: [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) + = (self debugStackPointerFor: bytecodePC)]]. - = (self debugStackPointerFor: bytecodePC)]. - self deny: self duplicateRegisterAssignmentsInTemporaries]. ! Item was added: + ----- Method: StackToRegisterMappingCogit>>genExtEnsureAllocatableSlots (in category 'bytecode generators') ----- + genExtEnsureAllocatableSlots + "SistaV1 * 236 11101100 iiiiiiii Ensure Allocatable Slots (+ Extend A * 256)" + self ssFlushTo: simStackPtr. + ^super genExtEnsureAllocatableSlots!

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magic decode for image files
by K K Subbu 12 Apr '17

12 Apr '17

Hi, I have attached a pattern match file that can be used by the file(1) command to decode Squeak/Cog/Spur image files. $ file -m magic Pharo-50770.image Pharo-40627.image Pharo-50770.image: Spur image 32b little-endian Pharo-40627.image: Cog image 32b little-endian,closure,nativefloat $ file -m magic Squeak3.8.1-6747full.image Squeak64-3.8g-6548.image Squeak3.8.1-6747full.image: Squeak image 32b little-endian Squeak64-3.8g-6548.image: Spur image 64b big-endian The file may be appended to /etc/magic (system-wide) or $HOME/.magic (for one user). It will help package maintainers pick the right vm for an Image. Ideally, this file should be generated by VMMaker under platforms/Cross/.., so patterns can be kept in sync with ImageFormat. I am rejoining this list after a break that took a lot longer than I expected :-(. Glad to be back, though it looks like I have a lot of catchup to do. Regards .. Subbu

2 7

[OpenSmalltalk/opensmalltalk-vm] 148e5a: Merge commit 'f155ee36a5c843c9f01c1ffc3b32399fdeb3...
by GitHub 11 Apr '17

11 Apr '17

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 148e5a288f56e2ff8f1ffbe9f877423a290079d4 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/148e5a288f56e2ff8f… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2017-04-09 (Sun, 09 Apr 2017) Changed paths: M .appveyor.yml M .travis.yml M deploy/pharo/deploy-key.sh A deploy/pharo/filter-exec.sh M deploy/pharo/pack-vm.sh Log Message: ----------- Merge commit 'f155ee36a5c843c9f01c1ffc3b32399fdeb32720' # Conflicts: # opensmalltalk-vm/.appveyor.yml # opensmalltalk-vm/.travis.yml # opensmalltalk-vm/deploy/pharo/deploy-key.sh # opensmalltalk-vm/deploy/pharo/pack-vm.sh Commit: 72f4f3100d5fe64b1d39274ca834b4309f9d4426 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/72f4f3100d5fe64b1d… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2017-04-09 (Sun, 09 Apr 2017) Changed paths: R deploy/pharo/deploy-files.pharo.org-appveyor.sh Log Message: ----------- remove unnecesary file Commit: 69a5e59f93e79e934e04bfeefd30d6dc31977af2 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/69a5e59f93e79e934e… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2017-04-10 (Mon, 10 Apr 2017) Changed paths: M platforms/unix/vm/sqUnixHeartbeat.c Log Message: ----------- enhance threaded missing rights to change priority message Commit: 0e1fc3adf468beebab9583da554c828e2f899d44 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/0e1fc3adf468beebab… Author: Esteban Lorenzano <estebanlm(a)gmail.com> Date: 2017-04-11 (Tue, 11 Apr 2017) Changed paths: M platforms/unix/vm/sqUnixHeartbeat.c Log Message: ----------- Merge pull request #132 from estebanlm/CogLatestTree improve linux Threaded Heartbeat VM text and instructions Compare: https://github.com/OpenSmalltalk/opensmalltalk-vm/compare/f155ee36a5c8...0e…

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Vm-dev April 2017