Vm-dev March 2017

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39 participants
154 discussions

Optimization bug in Pharo 64-bit Mac VM [was BUG? A problem with callbacks that shows up in 64bits (but is on 32bits too)]
by Eliot Miranda 10 Mar '17

10 Mar '17

Hi All, but especially Nicolas and C experts, if you build a Mac 64-bit Pharo VM in production and assert configurations and run the below wget files.pharo.org/get-files/60/pharo64.zip wget files.pharo.org/get-files/60/sources.zip unzip pharo64.zip unzip sources.zip pharo64cfvm Pharo64-60438.image eval "VGTigerDemo runDemo" & pharo64cavm Pharo64-60438.image eval "VGTigerDemo runDemo" you'll see that in the Assert VM the screen is clean and the tiger is displayed within a white rectangle, but in the production VM there are lots of garbage pixels at the bottom and bottom right of the screen. So somewhere in the display pipeline we have an optimization-related bug. The Assert VM is optimized at -O1 and the production VM at -Os (favour space over time). On Fri, Mar 10, 2017 at 12:13 PM, Eliot Miranda <eliot.miranda(a)gmail.com> wrote: > Hi Esteban, > > first of all hanks so much for the instructions. It's so nice to just > run the commands below and be able to reproduce immediately instead of > having to root around through build servers, following links. Thanks, it > saves me a huge amount of time. i really appreciate the effort. > > Second, I find I can make the primitive fail much sooner if I pick up the > main window and move it. I was running it on one machine, wanted to run it > on another with a different VM but the main window was in the way of the > command. So I moved the main window so I could read the command line and > lo and behold it failed immediately. So if I start the demo,and then pick > up the window and move it, the primitive fails within very few seconds. > That could be a clue. > > On Fri, Mar 10, 2017 at 7:35 AM, Esteban Lorenzano <estebanlm(a)gmail.com> > wrote: > >> >> Hi, >> >> I’m tumbling into an error in Pharo, because we use callbacks >> intensively, in Athens(cairo)-to-World conversion in particular, and people >> is sending always their crash reports… we made the whole conversion a lot >> more robust since problems started to arise, but now I hit a wall I cannot >> solve: I think problem is in something in callbacks. >> >> And problem is showing very easy on 64bits (while in 32bits it takes time >> and is more random). >> >> Here is the easiest way to reproduce it (in mac): >> >> wget files.pharo.org/get-files/60/pharo64-mac-latest.zip >> wget files.pharo.org/get-files/60/pharo64.zip >> wget files.pharo.org/get-files/60/sources.zip >> unzip pharo64-mac-latest.zip >> unzip pharo64.zip >> unzip sources.zip >> ./Pharo.app/Contents/MacOS/Pharo ./Pharo64-60438.image eval "VGTigerDemo >> runDemo" >> >> eventually (like 5-6 seconds after, if not immediately), you will have a >> stack like this: >> >> SmallInteger(Object)>>primitiveFailed: >> SmallInteger(Object)>>primitiveFailed >> SmallInteger(VMCallbackContext64)>>primSignal:andReturnAs:fromContext: >> GrafPort>>copyBits >> GrafPort>>image:at:sourceRect:rule: >> FormCanvas>>image:at:sourceRect:rule: >> FormCanvas(Canvas)>>drawImage:at:sourceRect: >> FormCanvas(Canvas)>>drawImage:at: >> VGTigerDemo>>runDemo >> VGTigerDemo class>>runDemo >> UndefinedObject>>DoIt >> OpalCompiler>>evaluate >> OpalCompiler(AbstractCompiler)>>evaluate: >> [ result := Smalltalk compiler evaluate: aStream. >> self hasSessionChanged >> ifFalse: [ self stdout >> print: result; >> lf ] ] in EvaluateCommandLineHandler>>evaluate: >> in Block: [ result := Smalltalk compiler evaluate: aStream.... >> BlockClosure>>on:do: >> EvaluateCommandLineHandler>>evaluate: >> EvaluateCommandLineHandler>>evaluateArguments >> EvaluateCommandLineHandler>>activate >> EvaluateCommandLineHandler class(CommandLineHandler class)>>activateWith: >> [ aCommandLinehandler activateWith: commandLine ] in >> PharoCommandLineHandler(BasicCommandLineHandler)>>activateSubCommand: in >> Block: [ aCommandLinehandler activateWith: commandLine ] >> BlockClosure>>on:do: >> PharoCommandLineHandler(BasicCommandLineHandler)>>activateSubCommand: >> PharoCommandLineHandler(BasicCommandLineHandler)>>handleSubcommand >> PharoCommandLineHandler(BasicCommandLineHandler)>>handleArgument: >> [ self >> handleArgument: >> (self arguments >> ifEmpty: [ '' ] >> ifNotEmpty: [ :arguments | arguments first ]) ] >> in PharoCommandLineHandler(BasicCommandLineHandler)>>activate in Block: >> [ self... >> BlockClosure>>on:do: >> PharoCommandLineHandler(BasicCommandLineHandler)>>activate >> PharoCommandLineHandler>>activate >> PharoCommandLineHandler class(CommandLineHandler class)>>activateWith: >> [ super activateWith: aCommandLine ] in PharoCommandLineHandler >> class>>activateWith: in Block: [ super activateWith: aCommandLine ] >> >> Any idea? >> >> thanks! >> Esteban > > > > > -- > _,,,^..^,,,_ > best, Eliot > -- _,,,^..^,,,_ best, Eliot

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Demo Of My "Live Compiler Debugger"
by Kruck, Bastian 09 Mar '17

09 Mar '17

Hello again, thank you Clément and Eliot for your reactions on my simulation issues. For time reasons, I didn’t get it running yet, and try to build my demo without it for now. Here is a demo of my current work: https://www.youtube.com/watch?v=RN_2ggE3YQk I have built a debugger that allows us to debug multiple language levels within the same debugger. In this video-walkthrough, I am in an application and debugging the issue that minSmallInt // -1 does return minSmallInt.[1] I step through the application, AST, and Smalltalk Bytecode. On the lower levels, I have a feature to debug the translators and finally fix the bug in the JIT-Compiler right in the debugger. This is why I try to make the VMMaker run the Slang and JIT simulation: To get the result of a primitive with some given arguments and step through its execution. So far, I got the Slang up and running. What is missing to enable my debugger stepping through the Bochs-Simulated JIT, is that I didn’t get the enilopmarts and stack setup right and wasn’t really sure where to fetch my evaluation result. In that process, I created some general wrapping and unwrapping methods which I needed. I may try to clean up my changes to the VMMaker (e.g. general wrapping/unwrapping) to feed them back to the trunk, if desired. I also experimented with using this debugger to debug a Smalltalk-hosted interpreter of a LISP-dialect.[2] The walkthrough at the top is going to be the core of my master thesis. I will speak about it on SAC in April.[3] So guys, what do you think about this? Are you full of question marks or did the video make sense to you? Just drop a short email to me with your current thoughts. I really appreciate your feedback :) Best regards, Basti [1] This was an actual bug in Cogit: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/6 [2] Kruck, B. et al. Multi-Level Debugging For Interpreter Developers (WIP-Paper at LaMod), Demo: https://www.youtube.com/watch?v=6KfQ6Vpe-hU&t=2m48s [3] Kruck, B. et al. Crossing Abstraction Barriers When Debugging in Dynamic Languages (To appear in SAC17)

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VM Maker: VMMaker.oscog-eem.2144.mcz
by commits＠source.squeak.org 09 Mar '17

09 Mar '17

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2144.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2144 Author: eem Time: 4 March 2017, 7:26:19.274398 pm UUID: 04b5cdd0-8070-4427-8771-913885fada41 Ancestors: VMMaker.oscog-eem.2143 64-bit Sista: Spur64BitMemoryManager must export fetchClassTagOf:. Spur: Check 64-bit translation for signed comparisons in SpurPlanningCompactor as well as 32-bit. Cogit: Rename blockPass, saveForBlockCompile et al to compilationPass, saveForRecompile etc. This so that RegisterAllocatingCogit can recompile when discovering a loop that needs a merge so that the register set computed at the end of a loop can be installed at the head. Refactor initializeFixupAt: into it and initializeFixup: to support RAC's recompilation. Add some inlines to eliminate some thin intermediate functions. Add support for adding #ifdef's to struct defs and use it to avoid CogSSBytecodeFixup's simNativeStackPtr and simNativeStackSize in non-Lowcode VMs. RegisterAllocatingCogit: Arrange to recompile when discovering loops with merges required to jump to the head. Installing the register set at the end of the loop at its beginning means a much faster back branch on the common path and should be a win for simple loops. Refactor resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: into it and conflictingRegistersBetweenSimStackAnd: for use by ensureRegisterAssignmentsAreAtHeadOfLoop:. Fix several slips where methodOrBlockNumArgs was used instead of methodOrBlockNumTemps. Nuke unused method & variable. =============== Diff against VMMaker.oscog-eem.2143 =============== Item was added: + ----- Method: CogAbstractInstruction>>reinitialize (in category 'initialization') ----- + reinitialize + annotation := nil. + dependent := nil. + operands at: 0 put: (operands at: 1 put: (operands at: 2 put: 0))! Item was added: + ----- Method: CogBytecodeFixup class>>filteredInstVarNames (in category 'translation') ----- + filteredInstVarNames + "Override to eliminate bcpc," + ^super filteredInstVarNames copyWithout: 'bcpc'! Item was changed: ----- Method: CogBytecodeFixup class>>instVarNamesAndTypesForTranslationDo: (in category 'translation') ----- instVarNamesAndTypesForTranslationDo: aBinaryBlock "enumerate aBinaryBlock with the names and C type strings for the inst vars to include in a BytecodeFixup struct." + self filteredInstVarNames do: - self allInstVarNames do: [:ivn| + aBinaryBlock + value: ivn + value: (ivn = 'targetInstruction' + ifTrue: [#'AbstractInstruction *'] + ifFalse: + [#sqInt])]! - ivn ~= 'bcpc' ifTrue: - [aBinaryBlock - value: ivn - value: (ivn = 'targetInstruction' - ifTrue: [#'AbstractInstruction *'] - ifFalse: - [#sqInt])]]! Item was changed: ----- Method: CogBytecodeFixup>>recordBcpc: (in category 'simulation') ----- recordBcpc: theBytecodePC <inline: true> self cCode: '' inSmalltalk: [(bcpc isNil or: [bcpc = theBytecodePC]) ifTrue: [bcpc := theBytecodePC] ifFalse: [bcpc := bcpc isInteger ifTrue: [{bcpc. theBytecodePC}] + ifFalse: + [(bcpc includes: theBytecodePC) ifTrue: [^self]. + bcpc, {theBytecodePC}]]]! - ifFalse: [bcpc, {theBytecodePC}]]]! Item was added: + ----- Method: CogSSBytecodeFixup class>>filteredInstVarNames (in category 'translation') ----- + filteredInstVarNames + "Override to add ifdef LowcodeVM around the native stack info. + self typedef" + ^super filteredInstVarNames + copyReplaceAll: #('simNativeStackPtr' 'simNativeStackSize') + with: #('#if LowcodeVM' 'simNativeStackPtr' 'simNativeStackSize' '#endif')! Item was changed: ----- Method: CogSSBytecodeFixup>>reinitialize (in category 'accessing') ----- reinitialize <inline: true> + targetInstruction := simStackPtr := 0. + LowcodeVM ifTrue: + [simNativeStackPtr := simNativeStackSize := 0]! - targetInstruction := 0. - simStackPtr := 0. - LowcodeVM ifTrue: [ - simNativeStackPtr := 0. - ]! Item was changed: CogClass subclass: #Cogit instanceVariableNames: 'coInterpreter objectMemory objectRepresentation processor threadManager methodZone methodZoneBase codeBase minValidCallAddress lastNInstructions simulatedAddresses simulatedTrampolines simulatedVariableGetters simulatedVariableSetters printRegisters printInstructions compilationTrace clickConfirm breakPC breakBlock singleStep guardPageSize traceFlags traceStores breakMethod methodObj enumeratingCogMethod methodHeader initialPC endPC methodOrBlockNumArgs inBlock needsFrame hasYoungReferent primitiveIndex backEnd literalsManager postCompileHook methodLabel stackCheckLabel blockEntryLabel blockEntryNoContextSwitch blockNoContextSwitchOffset stackOverflowCall sendMiss missOffset entryPointMask checkedEntryAlignment uncheckedEntryAlignment cmEntryOffset entry cmNoCheckEntryOffset noCheckEntry fullBlockEntry cbEntryOffset fullBlockNoContextSwitchEntry cbNoSwitchEntryOffset picMNUAbort picInterpretAbort endCPICCase0 endCPICCase1 firstCPICCaseOffset cPICCaseSize cP ICEndSize closedPICSize openPICSize fixups abstractOpcodes generatorTable byte0 byte1 byte2 byte3 bytecodePC bytecodeSetOffset opcodeIndex numAbstractOpcodes blockStarts blockCount labelCounter cStackAlignment expectedSPAlignment expectedFPAlignment codeModified maxLitIndex ceMethodAbortTrampoline cePICAbortTrampoline ceCheckForInterruptTrampoline ceCPICMissTrampoline ceReturnToInterpreterTrampoline ceBaseFrameReturnTrampoline ceSendMustBeBooleanAddTrueTrampoline ceSendMustBeBooleanAddFalseTrampoline ceCannotResumeTrampoline ceEnterCogCodePopReceiverReg ceCallCogCodePopReceiverReg ceCallCogCodePopReceiverAndClassRegs cePrimReturnEnterCogCode cePrimReturnEnterCogCodeProfiling ceNonLocalReturnTrampoline ceFetchContextInstVarTrampoline ceStoreContextInstVarTrampoline ceEnclosingObjectTrampoline ceFlushICache ceCheckFeaturesFunction ceTraceLinkedSendTrampoline ceTraceBlockActivationTrampoline ceTraceStoreTrampoline ceGetFP ceGetSP ceCaptureCStackPointers ordinarySendTrampolines superSen dTrampolines directedSuperSendTrampolines dynamicSuperSendTrampolines outerSendTrampolines selfSendTrampolines firstSend lastSend realCEEnterCogCodePopReceiverReg realCECallCogCodePopReceiverReg realCECallCogCodePopReceiverAndClassRegs trampolineTableIndex trampolineAddresses objectReferencesInRuntime runtimeObjectRefIndex cFramePointerInUse debugPrimCallStackOffset ceTryLockVMOwner ceUnlockVMOwner extA extB numExtB tempOop numIRCs indexOfIRC theIRCs receiverTags implicitReceiverSendTrampolines cogMethodSurrogateClass cogBlockMethodSurrogateClass nsSendCacheSurrogateClass CStackPointer CFramePointer cPICPrototype cPICEndOfCodeOffset cPICEndOfCodeLabel ceMallocTrampoline ceFreeTrampoline ceFFICalloutTrampoline debugBytecodePointers debugOpcodeIndices disassemblingMethod' + classVariableNames: 'AltBlockCreationBytecodeSize AltFirstSpecialSelector AltNSSendIsPCAnnotated AltNumSpecialSelectors AnnotationConstantNames AnnotationShift AnnotationsWithBytecodePCs BlockCreationBytecodeSize Debug DisplacementMask DisplacementX2N EagerInstructionDecoration FirstAnnotation FirstSpecialSelector HasBytecodePC IsAbsPCReference IsAnnotationExtension IsDirectedSuperSend IsDisplacementX2N IsNSDynamicSuperSend IsNSImplicitReceiverSend IsNSSelfSend IsNSSendCall IsObjectReference IsRelativeCall IsSendCall IsSuperSend MapEnd MaxCPICCases MaxCompiledPrimitiveIndex MaxStackAllocSize MaxX2NDisplacement NSCClassTagIndex NSCEnclosingObjectIndex NSCNumArgsIndex NSCSelectorIndex NSCTargetIndex NSSendIsPCAnnotated NumObjRefsInRuntime NumOopsPerNSC NumSpecialSelectors NumTrampolines ProcessorClass RRRName' - classVariableNames: 'AltBlockCreationBytecodeSize AltFirstSpecialSelector AltNSSendIsPCAnnotated AltNumSpecialSelectors AnnotationConstantNames AnnotationShift AnnotationsWithBytecodePCs BlockCreationBytecodeSize Debug DisplacementMask DisplacementX2N EagerInstructionDecoration FirstAnnotation FirstSpecialSelector HasBytecodePC IsAbsPCReference IsAnnotationExtension IsDirectedSuperSend IsDisplacementX2N IsNSDynamicSuperSend IsNSImplicitReceiverSend IsNSSelfSend IsNSSendCall IsObjectReference IsRelativeCall IsSendCall IsSuperSend MapEnd MaxCPICCases MaxCompiledPrimitiveIndex MaxStackAllocSize MaxX2NDisplacement NSCClassTagIndex NSCEnclosingObjectIndex NSCNumArgsIndex NSCSelectorIndex NSCTargetIndex NSSendIsPCAnnotated NeedsFixupFlag NumObjRefsInRuntime NumOopsPerNSC NumSpecialSelectors NumTrampolines ProcessorClass RRRName' poolDictionaries: 'CogAbstractRegisters CogCompilationConstants CogMethodConstants CogRTLOpcodes VMBasicConstants VMBytecodeConstants VMObjectIndices VMStackFrameOffsets' category: 'VMMaker-JIT'! Cogit class instanceVariableNames: 'generatorTable primitiveTable'! !Cogit commentStamp: 'eem 2/25/2017 17:53' prior: 0! I am the code generator for the Cog VM. My job is to produce machine code versions of methods for faster execution and to manage inline caches for faster send performance. I can be tested in the current image using my class-side in-image compilation facilities. e.g. try StackToRegisterMappingCogit genAndDis: (Integer >> #benchFib) I have concrete subclasses that implement different levels of optimization: SimpleStackBasedCogit is the simplest code generator. StackToRegisterMappingCogit is the current production code generator It defers pushing operands to the stack until necessary and implements a register-based calling convention for low-arity sends. SistaCogit is an experimental code generator with support for counting conditional branches, intended to support adaptive optimization. RegisterAllocatingCogit is an experimental code generator with support for allocating temporary variables to registers. It is inended to serve as the superclass to SistaCogit once it is working. SistaRegisterAllocatingCogit and SistaCogitClone are temporary classes that allow testing a clone of SistaCogit that inherits from RegisterAllocatingCogit. Once things work these will be merged and will replace SistaCogit. coInterpreter <CoInterpreterSimulator> the VM's interpreter with which I cooperate methodZoneManager <CogMethodZoneManager> the manager of the machine code zone objectRepresentation <CogObjectRepresentation> the object used to generate object accesses processor <BochsIA32Alien|?> the simulator that executes the IA32/x86 machine code I generate when simulating execution in Smalltalk simulatedTrampolines <Dictionary of Integer -> MessageSend> the dictionary mapping trap jump addresses to run-time routines used to warp from simulated machine code in to the Smalltalk run-time. simulatedVariableGetters <Dictionary of Integer -> MessageSend> the dictionary mapping trap read addresses to variables in run-time objects used to allow simulated machine code to read variables in the Smalltalk run-time. simulatedVariableSetters <Dictionary of Integer -> MessageSend> the dictionary mapping trap write addresses to variables in run-time objects used to allow simulated machine code to write variables in the Smalltalk run-time. printRegisters printInstructions clickConfirm <Boolean> flags controlling debug printing and code simulation breakPC <Integer> machine code pc breakpoint cFramePointer cStackPointer <Integer> the variables representing the C stack & frame pointers, which must change on FFI callback and return selectorOop <sqInt> the oop of the methodObj being compiled methodObj <sqInt> the bytecode method being compiled initialPC endPC <Integer> the start and end pcs of the methodObj being compiled methodOrBlockNumArgs <Integer> argument count of current method or block being compiled needsFrame <Boolean> whether methodObj or block needs a frame to execute primitiveIndex <Integer> primitive index of current method being compiled methodLabel <CogAbstractOpcode> label for the method header blockEntryLabel <CogAbstractOpcode> label for the start of the block dispatch code stackOverflowCall <CogAbstractOpcode> label for the call of ceStackOverflow in the method prolog sendMissCall <CogAbstractOpcode> label for the call of ceSICMiss in the method prolog entryOffset <Integer> offset of method entry code from start (header) of method entry <CogAbstractOpcode> label for the first instruction of the method entry code noCheckEntryOffset <Integer> offset of the start of a method proper (after the method entry code) from start (header) of method noCheckEntry <CogAbstractOpcode> label for the first instruction of start of a method proper fixups <Array of <AbstractOpcode Label | nil>> the labels for forward jumps that will be fixed up when reaching the relevant bytecode. fixups has one element per byte in methodObj's bytecode; initialPC maps to fixups[0]. abstractOpcodes <Array of <AbstractOpcode>> the code generated when compiling methodObj byte0 byte1 byte2 byte3 <Integer> individual bytes of current bytecode being compiled in methodObj bytecodePointer <Integer> bytecode pc (same as Smalltalk) of the current bytecode being compiled opcodeIndex <Integer> the index of the next free entry in abstractOpcodes (this code is translated into C where OrderedCollection et al do not exist) numAbstractOpcodes <Integer> the number of elements in abstractOpcocdes blockStarts <Array of <BlockStart>> the starts of blocks in the current method blockCount the index into blockStarts as they are being noted, and hence eventually the total number of blocks in the current method labelCounter <Integer> a nicety for numbering labels not needed in the production system but probably not expensive enough to worry about ceStackOverflowTrampoline <Integer> ceSend0ArgsTrampoline <Integer> ceSend1ArgsTrampoline <Integer> ceSend2ArgsTrampoline <Integer> ceSendNArgsTrampoline <Integer> ceSendSuper0ArgsTrampoline <Integer> ceSendSuper1ArgsTrampoline <Integer> ceSendSuper2ArgsTrampoline <Integer> ceSendSuperNArgsTrampoline <Integer> ceSICMissTrampoline <Integer> ceCPICMissTrampoline <Integer> ceStoreCheckTrampoline <Integer> ceReturnToInterpreterTrampoline <Integer> ceBaseFrameReturnTrampoline <Integer> ceSendMustBeBooleanTrampoline <Integer> ceClosureCopyTrampoline <Integer> the various trampolines (system-call-like jumps from machine code to the run-time). See Cogit>>generateTrampolines for the mapping from trampoline to run-time routine and then read the run-time routine for a funcitonal description. ceEnterCogCodePopReceiverReg <Integer> the enilopmart (jump from run-time to machine-code) methodZoneBase <Integer> ! Cogit class instanceVariableNames: 'generatorTable primitiveTable'! Item was removed: - ----- Method: InLineLiteralsManager>>resetForBlockCompile (in category 'compile abstract instructions') ----- - resetForBlockCompile! Item was added: + ----- Method: InLineLiteralsManager>>resetForRecompile (in category 'compile abstract instructions') ----- + resetForRecompile! Item was removed: - ----- Method: InLineLiteralsManager>>saveForBlockCompile (in category 'compile abstract instructions') ----- - saveForBlockCompile! Item was added: + ----- Method: InLineLiteralsManager>>saveForRecompile (in category 'compile abstract instructions') ----- + saveForRecompile! Item was removed: - ----- Method: OutOfLineLiteralsManager>>resetForBlockCompile (in category 'initialization') ----- - resetForBlockCompile - firstOpcodeIndex := savedFirstOpcodeIndex. - nextLiteralIndex := savedNextLiteralIndex. - lastDumpedLiteralIndex := savedLastDumpedLiteralIndex! Item was added: + ----- Method: OutOfLineLiteralsManager>>resetForRecompile (in category 'initialization') ----- + resetForRecompile + <inline: true> + firstOpcodeIndex := savedFirstOpcodeIndex. + nextLiteralIndex := savedNextLiteralIndex. + lastDumpedLiteralIndex := savedLastDumpedLiteralIndex! Item was removed: - ----- Method: OutOfLineLiteralsManager>>saveForBlockCompile (in category 'initialization') ----- - saveForBlockCompile - savedFirstOpcodeIndex := firstOpcodeIndex. - savedNextLiteralIndex := nextLiteralIndex. - savedLastDumpedLiteralIndex := lastDumpedLiteralIndex! Item was added: + ----- Method: OutOfLineLiteralsManager>>saveForRecompile (in category 'initialization') ----- + saveForRecompile + + <inline: true> + savedFirstOpcodeIndex := firstOpcodeIndex. + savedNextLiteralIndex := nextLiteralIndex. + savedLastDumpedLiteralIndex := lastDumpedLiteralIndex! Item was changed: StackToRegisterMappingCogit subclass: #RegisterAllocatingCogit + instanceVariableNames: 'numFixups mergeSimStacksBase nextFixup scratchSimStack scratchSpillBase scratchOptStatus ceSendMustBeBooleanAddTrueLongTrampoline ceSendMustBeBooleanAddFalseLongTrampoline recompileForLoopRegisterAssignments' - instanceVariableNames: 'numFixups mergeSimStacksBase nextFixup scratchSimStack scratchSpillBase scratchOptStatus ceSendMustBeBooleanAddTrueLongTrampoline ceSendMustBeBooleanAddFalseLongTrampoline' classVariableNames: '' poolDictionaries: '' category: 'VMMaker-JIT'! !RegisterAllocatingCogit commentStamp: 'eem 2/9/2017 10:40' prior: 0! RegisterAllocatingCogit is an optimizing code generator that is specialized for register allocation. On the contrary to StackToRegisterMappingCogit, RegisterAllocatingCogit keeps at each control flow merge point the state of the simulated stack to merge into and not only an integer fixup. Each branch and jump record the current state of the simulated stack, and each fixup is responsible for merging this state into the saved simulated stack. Instance Variables ceSendMustBeBooleanAddFalseLongTrampoline: <Integer> ceSendMustBeBooleanAddTrueLongTrampoline: <Integer> mergeSimStacksBase: <Integer> nextFixup: <Integer> numFixups: <Integer> scratchOptStatus: <CogSSOptStatus> scratchSimStack: <Array of CogRegisterAllocatingSimStackEntry> scratchSpillBase: <Integer> ceSendMustBeBooleanAddFalseLongTrampoline - the must-be-boolean trampoline for long jump false bytecodes (the existing ceSendMustBeBooleanAddFalseTrampoline is used for short branches) ceSendMustBeBooleanAddTrueLongTrampoline - the must-be-boolean trampoline for long jump true bytecodes (the existing ceSendMustBeBooleanAddTrueTrampoline is used for short branches) mergeSimStacksBase - the base address of the alloca'ed memory for merge fixups nextFixup - the index into mergeSimStacksBase from which the next needed mergeSimStack will be allocated numFixups - a conservative (over) estimate of the number of merge fixups needed in a method scratchOptStatus - a scratch variable to hold the state of optStatus while merge code is generated scratchSimStack - a scratch variable to hold the state of simStack while merge code is generated scratchSpillBase - a scratch variable to hold the state of spillBase while merge code is generated! Item was changed: ----- Method: RegisterAllocatingCogit>>compileAbstractInstructionsFrom:through: (in category 'compile abstract instructions') ----- compileAbstractInstructionsFrom: start through: end "Loop over bytecodes, dispatching to the generator for each bytecode, handling fixups in due course. Override to provide a development-time only escape for failed merges due to partially implemented + parallel move. Override to recompile after a loop requiring a merge is detected." + ^[| result initialOpcodeIndex initialCounterIndex initialIndexOfIRC | + compilationPass := 1. + initialOpcodeIndex := opcodeIndex. + initialCounterIndex := self maybeCounterIndex."for SistaCogit" + literalsManager saveForRecompile. + NewspeakVM ifTrue: + [initialIndexOfIRC := indexOfIRC]. + [recompileForLoopRegisterAssignments := false. + result := super compileAbstractInstructionsFrom: start through: end. + result = 0 and: [recompileForLoopRegisterAssignments]] + whileTrue: + [self reinitializeAllButBackwardFixupsFrom: start through: end. + self resetSimStack: start. + self reinitializeOpcodesFrom: initialOpcodeIndex to: opcodeIndex - 1. + compilationPass := compilationPass + 1. + nextFixup := 0. + opcodeIndex := initialOpcodeIndex. + self maybeSetCounterIndex: initialCounterIndex. "For SistaCogit" + literalsManager resetForRecompile. + NewspeakVM ifTrue: + [indexOfIRC := initialIndexOfIRC]]. + result] + on: Notification + do: [:ex| + ex tag == #failedMerge ifTrue: + [coInterpreter transcript + ensureCr; nextPutAll: 'FAILED MERGE IN '; + nextPutAll: (coInterpreter nameOfClass: (coInterpreter methodClassOf: methodObj)); + nextPutAll: '>>#'; nextPutAll: (coInterpreter stringOf: (coInterpreter maybeSelectorOfMethod: methodObj)); + flush. + ^ShouldNotJIT]. + ex pass]! - parallel move." - ^[super compileAbstractInstructionsFrom: start through: end] - on: Notification - do: [:ex| - ex tag == #failedMerge ifTrue: - [coInterpreter transcript - ensureCr; nextPutAll: 'FAILED MERGE IN '; - nextPutAll: (coInterpreter nameOfClass: (coInterpreter methodClassOf: methodObj)); - nextPutAll: '>>#'; nextPutAll: (coInterpreter stringOf: (coInterpreter maybeSelectorOfMethod: methodObj)); - flush. - ^ShouldNotJIT]. - ex pass]! Item was added: + ----- Method: RegisterAllocatingCogit>>conflictingRegistersBetweenSimStackAnd: (in category 'bytecode generator support') ----- + conflictingRegistersBetweenSimStackAnd: mergeSimStack + <var: #mergeSimStack type: #'SimStackEntry *'> + | currentRegsMask mergeRegsMask potentialConflictRegMask | + <var: #currentEntry type: #'SimStackEntry *'> + <var: #targetEntry type: #'SimStackEntry *'> + currentRegsMask := mergeRegsMask := potentialConflictRegMask := 0. + 0 to: simStackPtr do: + [:i| | currentEntry targetEntry currentRegMask mergeRegMask | + currentRegMask := (currentEntry := self simStack: simStack at: i) registerMaskOrNone. + mergeRegMask := (targetEntry := self simStack: mergeSimStack at: i) registerMaskOrNone. + (currentRegMask ~= mergeRegMask + and: [currentRegMask ~= 0 or: [mergeRegMask ~= 0]]) ifTrue: + [potentialConflictRegMask := potentialConflictRegMask bitOr: (currentRegMask bitOr: mergeRegMask)]. + currentRegsMask := currentRegsMask bitOr: currentRegMask. + mergeRegsMask := mergeRegsMask bitOr: mergeRegMask]. + ^potentialConflictRegMask bitAnd: (currentRegsMask bitAnd: mergeRegsMask)! Item was changed: ----- Method: RegisterAllocatingCogit>>deassignRegisterForTempVar:in: (in category 'bytecode generator support') ----- deassignRegisterForTempVar: targetEntry in: mergeSimStack "If merging a non-temp with a temp that has a live register we can assign to the register, but must unassign the register from the temp, otherwise the temp will acquire the merged value without an assignment. The targetEntry + must also be transmogrified into an SSRegister entry, which is done in the caller." - must also be transmogrified into an SSRegister entry." <var: #targetEntry type: #'SimStackEntry *'> <var: #duplicateEntry type: #'SimStackEntry *'> <var: #mergeSimStack type: #'SimStackEntry *'> <inline: true> | reg | reg := targetEntry liveRegister. self assert: (reg ~= NoReg and: [targetEntry type = SSConstant or: [targetEntry isFrameTempVar]]). targetEntry type = SSConstant ifTrue: [simStackPtr to: 0 by: -1 do: [:j| | duplicateEntry | duplicateEntry := self simStack: mergeSimStack at: j. (duplicateEntry registerOrNone = reg and: [duplicateEntry type = SSBaseOffset or: [duplicateEntry type = SSSpill]]) ifTrue: [duplicateEntry liveRegister: NoReg]]] ifFalse: [simStackPtr to: 0 by: -1 do: [:j| | duplicateEntry | duplicateEntry := self simStack: mergeSimStack at: j. (targetEntry isSameEntryAs: duplicateEntry) ifTrue: [j < methodOrBlockNumTemps ifTrue: [duplicateEntry liveRegister: NoReg] + ifFalse: [duplicateEntry type: SSRegister; register: reg]]]]! - ifFalse: [duplicateEntry type: SSRegister; register: reg]]]]. - targetEntry - type: SSRegister; - register: reg! Item was changed: ----- Method: RegisterAllocatingCogit>>ensureFixupAt: (in category 'bytecode generator support') ----- ensureFixupAt: targetPC "Make sure there's a flagged fixup at the target pc in fixups. Initially a fixup's target is just a flag. Later on it is replaced with a proper instruction. Override to enerate stack merging code if required." | fixup | <var: #fixup type: #'BytecodeFixup *'> self assert: targetPC > bytecodePC. fixup := self fixupAt: targetPC. fixup needsFixup ifTrue: [fixup mergeSimStack ifNil: [self setMergeSimStackOf: fixup] ifNotNil: [self mergeCurrentSimStackWith: fixup forwards: true]] ifFalse: + [self assert: (fixup mergeSimStack isNil or: [compilationPass = 2]). - [self assert: fixup mergeSimStack isNil. self moveVolatileSimStackEntriesToRegisters. + fixup mergeSimStack + ifNil: [self setMergeSimStackOf: fixup] + ifNotNil: [self assert: (self simStack: simStack isIdenticalTo: fixup mergeSimStack)]]. - self setMergeSimStackOf: fixup]. ^super ensureFixupAt: targetPC! Item was added: + ----- Method: RegisterAllocatingCogit>>ensureRegisterAssignmentsAreAtHeadOfLoop: (in category 'bytecode generator support') ----- + ensureRegisterAssignmentsAreAtHeadOfLoop: target + "Compiling a loop body will compute a set of live registers. The backward branch must merge + with the head of the loop. So it is preferrable to make the register assignments at the end of + the loop available at the head. To do this, simply copy the register assignments to the loop + head's fixup in the first compilation pass and schedule a second compilation pass. On the + second pass the merge will occur when encountering the fixup for the loop head, using + exactly the same code as for a merge at the end of an if." + | conflictingRegsMask | + compilationPass > 1 ifTrue: + ["self deny: (self mergeRequiredToTarget: target mergeSimStack)." + self assert: (target mergeSimStack isNil or: [self simStack: simStack isIdenticalTo: target mergeSimStack]). + ^self]. + (self mergeRequiredToTarget: target mergeSimStack) ifFalse: + [^self]. + "Schedule a recompile and merge the end-of-loop assignments into the head of the loop, + giving priority to the assignments at this point, and preserving any other non-conflicting + assignments." + recompileForLoopRegisterAssignments := true. + conflictingRegsMask := self conflictingRegistersBetweenSimStackAnd: target mergeSimStack. + self deny: (self register: FPReg isInMask: conflictingRegsMask). + 0 to: simStackPtr do: + [:i| | currentEntry targetEntry | + currentEntry := self simStack: simStack at: i. + targetEntry := self simStack: target mergeSimStack at: i. + currentEntry liveRegister ~= NoReg + ifTrue: + [targetEntry liveRegister: currentEntry liveRegister] + ifFalse: + [(targetEntry registerMask anyMask: conflictingRegsMask) ifTrue: + [targetEntry liveRegister: NoReg]]]. + optStatus isReceiverResultRegLive ifTrue: + [target isReceiverResultRegSelf: true]! Item was removed: - ----- Method: RegisterAllocatingCogit>>genExtJumpIfNotInstanceOfBehaviorsOrPopBytecode (in category 'bytecode generators') ----- - genExtJumpIfNotInstanceOfBehaviorsOrPopBytecode - "SistaV1: * 254 11111110 kkkkkkkk jjjjjjjj branch If Not Instance Of Behavior/Array Of Behavior kkkkkkkk (+ Extend A * 256, where Extend A >= 0) distance jjjjjjjj (+ Extend B * 256, where Extend B >= 0)" - - | reg literal distance targetFixUp | - - reg := self allocateRegForStackEntryAt: 0. - self ssTop popToReg: reg. - - literal := self getLiteral: (extA * 256 + byte1). - extA := 0. - distance := extB * 256 + byte2. - extB := 0. - numExtB := 0. - - "Because ensureFixupAt: will generate code to merge with the target simStack when required, it is - necessary to tease apart the jump and the merge so that the merge code is only executed if the - branch is taken. i.e. if merge code is required we generate - jump not cond Lcontinue - ... merge code ... - jump Ltarget - Lcontinue: - instead of the incorrect - ... merge code ... - jump cond Ltarget" - (self mergeRequiredForJumpTo: bytecodePC + 3 + distance) ifTrue: - [self shouldBeImplemented]. - - targetFixUp := self cCoerceSimple: (self ensureFixupAt: bytecodePC + 3 + distance) to: #'AbstractInstruction *'. - - (objectMemory isArrayNonImm: literal) - ifTrue: [objectRepresentation branchIf: reg notInstanceOfBehaviors: literal target: targetFixUp] - ifFalse: [objectRepresentation branchIf: reg notInstanceOfBehavior: literal target: targetFixUp]. - - self ssPop: 1. - - ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>genJumpBackTo: (in category 'bytecode generator support') ----- genJumpBackTo: targetPC | target | + "On first pass install register allocations (if any) as of the end of the loop and back up to recompile. + One the second pass generate + (any merge elided because register assignments copied to loop head in first pass) - "We generate - merge cmp stackLimit jumpAboveOrEqual target flush checkForInterrupts + merge from flushed (N.B. If stack was flushed before loop we could conceivably jump to the pre-loop merge code) - marge from flushed jmp target self printSimStack; printSimStack: target mergeSimStack" self assert: targetPC < bytecodePC. target := self fixupAt: targetPC. + self ensureRegisterAssignmentsAreAtHeadOfLoop: target. - self mergeCurrentSimStackWith: target forwards: false. self MoveAw: coInterpreter stackLimitAddress R: TempReg. self CmpR: TempReg R: SPReg. "N.B. FLAGS := SPReg - TempReg" self JumpAboveOrEqual: target. self ssFlushTo: simStackPtr. self CallRT: ceCheckForInterruptTrampoline. self annotateBytecode: self Label. self flushLiveRegistersForSuspensionPoint. self mergeCurrentSimStackWith: target forwards: false. self Jump: target. deadCode := true. "can't fall through" ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith:forwards: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup forwards: forwards "At a merge point the cogit expects the stack to be in the same state as mergeSimStack. mergeSimStack is the state as of some jump forward or backward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. The state of optStatus must agree. Generate code to merge the current simStack with that of the target fixup, the goal being to keep as many registers live as possible. If the merge is forwards registers can be deassigned (since registers are always written to temp vars). But if backwards, nothing can be deassigned, and the state /must/ reflect the target." "self printSimStack; printSimStack: fixup mergeSimStack" "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" <var: #fixup type: #'BytecodeFixup *'> | startIndex mergeSimStack currentEntry targetEntry writtenToRegisters | <var: #mergeSimStack type: #'SimStackEntry *'> <var: #targetEntry type: #'SimStackEntry *'> <var: #currentEntry type: #'SimStackEntry *'> (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. startIndex := opcodeIndex. "for debugging" "Assignments amongst the registers must be made in order to avoid overwriting. If necessary exchange registers amongst simStack's entries to resolve any conflicts." self resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: mergeSimStack. (self asserta: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack)) ifFalse: [Notification new tag: #failedMerge; signal]. + "Compute written to registers. Perhaps we should use 0 in place of methodOrBlockNumArgs + but Smalltalk does not assign to arguments." writtenToRegisters := 0. (self pushForMergeWith: mergeSimStack) ifTrue: [methodOrBlockNumArgs to: simStackPtr do: [:i| currentEntry := self simStack: simStack at: i. targetEntry := self simStack: mergeSimStack at: i. writtenToRegisters := writtenToRegisters bitOr: targetEntry registerMask. (currentEntry reconcileForwardsWith: targetEntry) ifTrue: [self assert: i >= methodOrBlockNumArgs. + self deassignRegisterForTempVar: targetEntry in: mergeSimStack. + targetEntry + type: SSRegister; + register: targetEntry liveRegister]. - self deassignRegisterForTempVar: targetEntry in: mergeSimStack]. "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: spilled ifFalse: [simSpillBase := i - 1]. simStack at: i put: (self cCode: [mergeSimStack at: i] inSmalltalk: [(mergeSimStack at: i) copy])"]] ifFalse: [simStackPtr to: methodOrBlockNumArgs by: -1 do: [:i| currentEntry := self simStack: simStack at: i. targetEntry := self simStack: mergeSimStack at: i. writtenToRegisters := writtenToRegisters bitOr: targetEntry registerMask. (currentEntry reconcileForwardsWith: targetEntry) ifTrue: [self assert: i >= methodOrBlockNumArgs. + self deassignRegisterForTempVar: targetEntry in: mergeSimStack. + targetEntry + type: SSRegister; + register: targetEntry liveRegister]. - self deassignRegisterForTempVar: targetEntry in: mergeSimStack]. "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: spilled ifFalse: [simSpillBase := i - 1]. simStack at: i put: (self cCode: [mergeSimStack at: i] inSmalltalk: [(mergeSimStack at: i) copy])"]]. + "Note that since we've deassigned any conflicts beyond the temps above we need only compare the temps here." + methodOrBlockNumTemps - 1 to: 0 by: -1 do: - methodOrBlockNumArgs - 1 to: 0 by: -1 do: [:i| targetEntry := self simStack: mergeSimStack at: i. (targetEntry registerMask noMask: writtenToRegisters) ifTrue: [currentEntry := self simStack: simStack at: i. writtenToRegisters := writtenToRegisters bitOr: targetEntry registerMask. (currentEntry reconcileForwardsWith: targetEntry) ifTrue: [self assert: i >= methodOrBlockNumArgs. self deassignRegisterForTempVar: targetEntry in: mergeSimStack]]]. optStatus isReceiverResultRegLive ifFalse: [forwards ifTrue: "a.k.a. fixup isReceiverResultRegSelf: (fixup isReceiverResultRegSelf and: [optStatus isReceiverResultRegLive])" [fixup isReceiverResultRegSelf: false] ifFalse: [fixup isReceiverResultRegSelf ifTrue: [self putSelfInReceiverResultReg]]]! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeWithFixupIfRequired: (in category 'simulation stack') ----- mergeWithFixupIfRequired: fixup "If this bytecode has a fixup, some kind of merge needs to be done. There are 4 cases: 1) the bytecode has no fixup (fixup isNotAFixup) do nothing 2) the bytecode has a non merge fixup the fixup has needsNonMergeFixup. The code generating non merge fixup (currently only special selector code) is responsible for the merge so no need to do it. We set deadCode to false as the instruction can be reached from jumps. 3) the bytecode has a merge fixup, but execution flow *cannot* fall through to the merge point. the fixup has needsMergeFixup and deadCode = true. ignores the current simStack as it does not mean anything restores the simStack to the state the jumps to the merge point expects it to be. 4) the bytecode has a merge fixup and execution flow *can* fall through to the merge point. the fixup has needsMergeFixup and deadCode = false. Merge the state into the fixup's state via mergeCurrentSimStackWith:forwards:. In addition, if this is a backjump merge point, we patch the fixup to hold the current simStackPtr for later assertions. self printSimStack: fixup mergeSimStack" <var: #fixup type: #'BytecodeFixup *'> "case 1" fixup notAFixup ifTrue: [^0]. "case 2" fixup isNonMergeFixup ifTrue: [deadCode ifTrue: [self deny: fixup simStackPtr isNil. simStackPtr := fixup simStackPtr. self restoreSimStackAtMergePoint: fixup. deadCode := false] ifFalse: [self flushRegistersOnlyLiveOnFallThrough: fixup]. ^0]. "cases 3 and 4" self assert: fixup isMergeFixup. self traceMerge: fixup. deadCode ifTrue: [simStackPtr := fixup simStackPtr] "case 3" + ifFalse: [(fixup isBackwardBranchFixup and: [compilationPass > 1]) ifTrue: + [fixup simStackPtr: simStackPtr]. + self mergeCurrentSimStackWith: fixup forwards: true]. "case 4" - ifFalse: [self mergeCurrentSimStackWith: fixup forwards: true]. "case 4" "cases 3 and 4" deadCode := false. fixup isBackwardBranchFixup ifTrue: + [self assert: fixup mergeSimStack isNil == (compilationPass = 1). + fixup mergeSimStack ifNil: + [self setMergeSimStackOf: fixup]]. - [self assert: fixup mergeSimStack isNil. - self setMergeSimStackOf: fixup]. fixup targetInstruction: self Label. self assert: simStackPtr = fixup simStackPtr. self cCode: '' inSmalltalk: [self assert: fixup simStackPtr = (self debugStackPointerFor: bytecodePC)]. self restoreSimStackAtMergePoint: fixup. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>pushForMergeWith: (in category 'bytecode generator support') ----- pushForMergeWith: mergeSimStack "Answer if values must be pushed from simStack to merge with mergeSimStack, otherwise < 0 (the default)." <var: #mergeSimStack type: #'SimStackEntry *'> <inline: true> + simStackPtr to: methodOrBlockNumTemps by: -1 do: - simStackPtr to: methodOrBlockNumArgs by: -1 do: [:i| + (self simStack: mergeSimStack at: i) spilled ~= (self simStack: simStack at: i) spilled ifTrue: - (self simStack: mergeSimStack at: i) spilled ~=(self simStack: simStack at: i) spilled ifTrue: [^(self simStack: mergeSimStack at: i) spilled]]. ^false! Item was added: + ----- Method: RegisterAllocatingCogit>>reinitializeAllButBackwardFixupsFrom:through: (in category 'compile abstract instructions') ----- + reinitializeAllButBackwardFixupsFrom: start through: end + "When a method must be recompiled due to moving a loop's register + assignments to the head of a loop, backward fixups must be marked + as such, and all but backward fixups must be reinitialized." + <inline: true> + | descriptor nExts pc distance targetPC | + <var: #descriptor type: #'BytecodeDescriptor *'> + pc := start. + nExts := 0. + [pc <= end] whileTrue: + [byte0 := (objectMemory fetchByte: pc ofObject: methodObj) + bytecodeSetOffset. + descriptor := self generatorAt: byte0. + (descriptor isBranch + and: [self isBackwardBranch: descriptor at: pc exts: nExts in: methodObj]) ifTrue: + [distance := self spanFor: descriptor at: pc exts: nExts in: methodObj. + targetPC := pc + descriptor numBytes + distance. + self initializeFixupAt: targetPC]. + descriptor isBlockCreation + ifTrue: + [distance := self spanFor: descriptor at: pc exts: nExts in: methodObj. + pc := pc + descriptor numBytes + distance] + ifFalse: [pc := pc + descriptor numBytes]. + nExts := descriptor isExtension ifTrue: [nExts + 1] ifFalse: [0]]. + start to: end do: + [:i| | fixup | + fixup := self fixupAt: i. + (fixup notAFixup or: [fixup isBackwardBranchFixup]) ifFalse: + [fixup reinitialize]]! Item was added: + ----- Method: RegisterAllocatingCogit>>reinitializeOpcodesFrom:to: (in category 'bytecode generator support') ----- + reinitializeOpcodesFrom: start to: end + <inline: true> + start to: end do: + [:i| + (self abstractInstructionAt: i) reinitialize]! Item was added: + ----- Method: RegisterAllocatingCogit>>resetSimStack: (in category 'bytecode generator support') ----- + resetSimStack: startPC + <inline: true> + simSpillBase := methodOrBlockNumTemps. + simStackPtr := methodOrBlockNumTemps - 1. + self voidReceiverResultRegContainsSelf. + self flushLiveRegistersForSend. + self cCode: '' inSmalltalk: + [0 to: methodOrBlockNumTemps - 1 do: + [:i| + (self simStackAt: i) bcptr: startPC]]! Item was changed: ----- Method: RegisterAllocatingCogit>>resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: (in category 'bytecode generator support') ----- resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: mergeSimStack <var: #mergeSimStack type: #'SimStackEntry *'> "One simple algorithm is to spill everything if there are any conflicts and then pop back. But this is terrible :-( Can we do better? Yes... Consider the following two simStacks target: 0: | rA | __ | rB | rC | rD | <- sp current: 0: | __ | __ | rD | rA | rC | <- sp If we were to assign in a naive order, 0 through sp rA would be overwritten before its value in current[3] is written to rC, and rC would be overwritten before its value in current[4] is written to rD. But if we swap the registers in current so that they respect the reverse ordering in target we can assign directly: swap current[3] & current[4] 0: | __ | __ | rD | rC | rA | <- sp now do the assignment in the order target[0] := current[0], target[1] := current[1], ... target[4] := current[4], i.e. rA := current[0]; rB := rD; (rC := rC); (rD := rD). So find any conflicts, and if there are any, swap registers in the simStack to resolve them. The trivial case of a single conflict is resolved by assigning that conflict to TempReg." + | conflictingRegsMask | + conflictingRegsMask := self conflictingRegistersBetweenSimStackAnd: mergeSimStack. - | currentRegsMask mergeRegsMask potentialConflictRegMask conflictingRegsMask - currentRegMask mergeRegMask currentEntry targetEntry | - <var: #currentEntry type: #'SimStackEntry *'> - <var: #targetEntry type: #'SimStackEntry *'> - currentRegsMask := mergeRegsMask := potentialConflictRegMask := 0. - 0 to: simStackPtr do: - [:i| - currentRegMask := (currentEntry := self simStack: simStack at: i) registerMaskOrNone. - mergeRegMask := (targetEntry := self simStack: mergeSimStack at: i) registerMaskOrNone. - (currentRegMask ~= mergeRegMask - and: [currentRegMask ~= 0 or: [mergeRegMask ~= 0]]) ifTrue: - [potentialConflictRegMask := potentialConflictRegMask bitOr: (currentRegMask bitOr: mergeRegMask)]. - currentRegsMask := currentRegsMask bitOr: currentRegMask. - mergeRegsMask := mergeRegsMask bitOr: mergeRegMask]. - conflictingRegsMask := potentialConflictRegMask bitAnd: (currentRegsMask bitAnd: mergeRegsMask). conflictingRegsMask ~= 0 ifTrue: [(self isAPowerOfTwo: conflictingRegsMask) "Multiple conflicts mean we have to sort" ifFalse: [self swapCurrentRegistersInMask: conflictingRegsMask accordingToRegisterOrderIn: mergeSimStack] ifTrue: [self assignToTempRegConflictingRegisterIn: conflictingRegsMask]].! Item was changed: ----- Method: RegisterAllocatingCogit>>simSelfOnStackInReceiverResultReg (in category 'bytecode generator support') ----- simSelfOnStackInReceiverResultReg "For assert checking only." + methodOrBlockNumTemps to: simStackPtr do: - methodOrBlockNumArgs to: simStackPtr do: [:i| (((self addressOf: simSelf) isSameEntryAs: (self simStackAt: i)) and: [(self simStackAt: i) registerOrNone = ReceiverResultReg]) ifTrue: [^true]]. ^false! Item was changed: ----- Method: Spur64BitMemoryManager>>fetchClassTagOf: (in category 'interpreter access') ----- fetchClassTagOf: oop + <api> | tagBits | ^(tagBits := oop bitAnd: self tagMask) ~= 0 ifTrue: [tagBits] ifFalse: [self classIndexOf: oop]! Item was added: + ----- Method: SpurPlanningCompactor class>>identify32BitSignedComparisons (in category 'analysis') ----- + identify32BitSignedComparisons + "self identify32BitSignedComparisons" + self identifySignedComparisonsFor: #(ObjectMemory Spur32BitMemoryManager) + noise: #('(manager bytesInObject: largestFreeChunk) >= spaceEstimate' + '(self classIndexOf: o*) > self isForwardedObjectClassIndexPun' + 'GCModeFull > 0' + 'ReceiverIndex + (objectMemory integerValueOf: sp*) < (objectMemory lengthOf: o*)' + 'availableSpace > 0' + 'bytes + 2 * 8 > availableSpace' + 'fmt* < manager firstCompiledMethodFormat' + 'fmt* < self firstCompiledMethodFormat' + 'fmt* <= 5' + 'gcPhaseInProgress > 0' + 'i <= finishIndex' + 'numPointerSlots > 0' + 'scavenger rememberedSetSize > 0')! Item was added: + ----- Method: SpurPlanningCompactor class>>identify64BitSignedComparisons (in category 'analysis') ----- + identify64BitSignedComparisons + "self identify64BitSignedComparisons" + self identifySignedComparisonsFor: #(ObjectMemory Spur64BitMemoryManager) + noise: #('(manager bytesInObject: largestFreeChunk) >= spaceEstimate' + '(self classIndexOf: o*) > self isForwardedObjectClassIndexPun' + 'GCModeFull > 0' + 'ReceiverIndex + (objectMemory integerValueOf: sp*) < (objectMemory lengthOf: o*)' + 'availableSpace > 0' + 'bytes + 2 * 8 > availableSpace' + 'fmt* < manager firstCompiledMethodFormat' + 'fmt* < self firstCompiledMethodFormat' + 'fmt* <= 5' + 'gcPhaseInProgress > 0' + 'i <= finishIndex' + 'numPointerSlots > 0' + 'scavenger rememberedSetSize > 0')! Item was removed: - ----- Method: SpurPlanningCompactor class>>identifySignedComparisons (in category 'analysis') ----- - identifySignedComparisons - "self identifySignedComparisons" - | vmm cg noise | - noise := #('(manager bytesInObject: largestFreeChunk) >= spaceEstimate' - '(self classIndexOf: o*) > self isForwardedObjectClassIndexPun' - 'GCModeFull > 0' - 'ReceiverIndex + (objectMemory integerValueOf: sp*) < (objectMemory lengthOf: o*)' - 'availableSpace > 0' - 'bytes + 2 * 8 > availableSpace' - 'fmt* < manager firstCompiledMethodFormat' - 'fmt* < self firstCompiledMethodFormat' - 'fmt* <= 5' - 'gcPhaseInProgress > 0' - 'i <= finishIndex' - 'i >= 0' - 'numPointerSlots > 0' - 'scavenger rememberedSetSize > 0'). - vmm := (VMMaker forPlatform: 'Cross') - interpreterClass: StackInterpreter; - options: #(ObjectMemory Spur32BitMemoryManager). - cg := [vmm buildCodeGeneratorForInterpreter] - on: Notification - do: [:ex| - ex tag == #getVMMaker - ifTrue: [ex resume: vmm] - ifFalse: [ex pass]]. - cg vmClass preGenerationHook: cg. - cg inferTypesForImplicitlyTypedVariablesAndMethods. - cg retainMethods: self selectors. - cg prepareMethods. - cg doInlining: true. - self selectors sort do: - [:sel| - (cg methodNamed: sel) ifNotNil: - [:m| - m parseTree nodesDo: - [:node| - (node isSend - and: [(#(< > <= >=) includes: node selector) - and: [({node receiver. node args first } anySatisfy: - [:o| (cg typeFor: o in: m) - ifNil: [true] - ifNotNil: [:t| (cg isIntegralCType: t) and: [t first ~= $u]]]) - and: [noise noneSatisfy: [:n| n match: node printString]]]]) ifTrue: - [Transcript ensureCr; nextPutAll: sel; space; print: node; flush]]]]! Item was added: + ----- Method: SpurPlanningCompactor class>>identifySignedComparisonsFor:noise: (in category 'analysis') ----- + identifySignedComparisonsFor: options noise: noise + "self identify32BitSignedComparisons" + "self identify64BitSignedComparisons" + | vmm cg | + vmm := (VMMaker forPlatform: 'Cross') + interpreterClass: StackInterpreter; + options: options. + cg := [vmm buildCodeGeneratorForInterpreter] + on: Notification + do: [:ex| + ex tag == #getVMMaker + ifTrue: [ex resume: vmm] + ifFalse: [ex pass]]. + cg vmClass preGenerationHook: cg. + cg inferTypesForImplicitlyTypedVariablesAndMethods. + cg retainMethods: self selectors. + cg prepareMethods. + cg doInlining: true. + self selectors sort do: + [:sel| + (cg methodNamed: sel) ifNotNil: + [:m| + m parseTree nodesDo: + [:node| + (node isSend + and: [(#(< > <= >=) includes: node selector) + and: [({node receiver. node args first } anySatisfy: + [:o| (cg typeFor: o in: m) + ifNil: [true] + ifNotNil: [:t| (cg isIntegralCType: t) and: [t first ~= $u]]]) + and: [noise noneSatisfy: [:n| n match: node printString]]]]) ifTrue: + [Transcript ensureCr; nextPutAll: sel; space; print: node; flush]]]]! Item was changed: SimpleStackBasedCogit subclass: #StackToRegisterMappingCogit + instanceVariableNames: 'prevBCDescriptor numPushNilsFunction pushNilSizeFunction methodOrBlockNumTemps regArgsHaveBeenPushed simSelf simStack simStackPtr simSpillBase optStatus ceCallCogCodePopReceiverArg0Regs ceCallCogCodePopReceiverArg1Arg0Regs methodAbortTrampolines picAbortTrampolines picMissTrampolines ceCall0ArgsPIC ceCall1ArgsPIC ceCall2ArgsPIC debugStackPointers debugFixupBreaks realCECallCogCodePopReceiverArg0Regs realCECallCogCodePopReceiverArg1Arg0Regs deadCode useTwoPaths currentCallCleanUpSize simNativeStack simNativeStackPtr simNativeSpillBase simNativeStackSize hasNativeFrame compilationPass' - instanceVariableNames: 'prevBCDescriptor numPushNilsFunction pushNilSizeFunction methodOrBlockNumTemps regArgsHaveBeenPushed simSelf simStack simStackPtr simSpillBase optStatus ceCallCogCodePopReceiverArg0Regs ceCallCogCodePopReceiverArg1Arg0Regs methodAbortTrampolines picAbortTrampolines picMissTrampolines ceCall0ArgsPIC ceCall1ArgsPIC ceCall2ArgsPIC debugStackPointers debugFixupBreaks realCECallCogCodePopReceiverArg0Regs realCECallCogCodePopReceiverArg1Arg0Regs deadCode useTwoPaths currentCallCleanUpSize simNativeStack simNativeStackPtr simNativeSpillBase simNativeStackSize hasNativeFrame blockPass' classVariableNames: 'NeedsMergeFixupFlag NeedsNonMergeFixupFlag' poolDictionaries: 'CogCompilationConstants VMMethodCacheConstants VMObjectIndices VMStackFrameOffsets' category: 'VMMaker-JIT'! StackToRegisterMappingCogit class instanceVariableNames: 'numPushNilsFunction pushNilSizeFunction'! + !StackToRegisterMappingCogit commentStamp: 'eem 3/3/2017 10:29' prior: 0! - !StackToRegisterMappingCogit commentStamp: 'eem 2/9/2017 10:07' prior: 0! StackToRegisterMappingCogit is an optimizing code generator that eliminates a lot of stack operations and inlines some special selector arithmetic. It does so by a simple stack-to-register mapping scheme based on deferring the generation of code to produce operands until operand-consuming operations. The operations that consume operands are sends, stores and returns. See methods in the class-side documentation protocol for more detail. Instance Variables + compilationPass: <Integer> + currentCallCleanUpSize: <Integer> + ceCall0ArgsPIC: <Integer> + ceCall1ArgsPIC: <Integer> + ceCall2ArgsPIC: <Integer> + ceCallCogCodePopReceiverArg0Regs: <Integer> + ceCallCogCodePopReceiverArg1Arg0Regs: <Integer> + deadCode <Boolean> - callerSavedRegMask: <Integer> - ceEnter0ArgsPIC: <Integer> - ceEnter1ArgsPIC: <Integer> - ceEnter2ArgsPIC: <Integer> - ceEnterCogCodePopReceiverArg0Regs: <Integer> - ceEnterCogCodePopReceiverArg1Arg0Regs: <Integer> debugBytecodePointers: <Set of Integer> debugFixupBreaks: <Set of Integer> debugStackPointers: <CArrayAccessor of (Integer|nil)> + hasNativeFrame <Boolean> methodAbortTrampolines: <CArrayAccessor of Integer> methodOrBlockNumTemps: <Integer> + numPushNilsFunction: <Symbol> optStatus: <Integer> picAbortTrampolines: <CArrayAccessor of Integer> picMissTrampolines: <CArrayAccessor of Integer> + pushNilSizeFunction: <Symbol> + realCECallCogCodePopReceiverArg0Regs: <Integer> + realCECallCogCodePopReceiverArg1Arg0Regs: <Integer> - realCEEnterCogCodePopReceiverArg0Regs: <Integer> - realCEEnterCogCodePopReceiverArg1Arg0Regs: <Integer> regArgsHaveBeenPushed: <Boolean> + simNativeSpillBase: <Integer> + simNativeStack: <CArrayAccessor of CogSimStackNativeEntry> + simNativeStackPtr: <Integer> + simNativeStackSize: <Integer> simSelf: <CogSimStackEntry> simSpillBase: <Integer> simStack: <CArrayAccessor of CogSimStackEntry> simStackPtr: <Integer> traceSimStack: <Integer> useTwoPaths <Boolean> + compilationPass + - counter indicating whether on the first pass through bytecodes in a V3-style embedded block or not. The V3 closure implementation uses pushNil to initialize temporary variables and this makes an initial pushNil ambiguous. With the V3 bytecode set, the JIT must compile to the end of the block to discover if a pushNil is for initializing a temp or to produce an operand. - callerSavedRegMask - - the bitmask of the ABI's caller-saved registers + currentCallCleanUpSize + - the number of bytes to remove from the stack in a Lowcode call. + + ceCall0ArgsPIC ceCall1ArgsPIC ceCall2ArgsPIC - ceEnter0ArgsPIC ceEnter1ArgsPIC ceEnter2ArgsPIC - the trampoline for entering an N-arg PIC + ceCallCogCodePopReceiverArg0Regs ceCallCogCodePopReceiverArg1Arg0Regs + - the trampoline for invokinging a method with N register args - ceEnterCogCodePopReceiverArg0Regs ceEnterCogCodePopReceiverArg1Arg0Regs - - the trampoline for entering a method with N register args debugBytecodePointers - a Set of bytecode pcs for setting breakpoints (simulation only) + deadCode + - set to true to indicate that the next bytecode (up to the next fixup) is not reachable. Used to avoid generating dead code. + debugFixupBreaks - a Set of fixup indices for setting breakpoints (simulation only) debugStackPointers - an Array of stack depths for each bytecode for code verification + hasNativeFrame + - set to true when Lowcode creates a native stack frame for Lowcode callouts. + methodAbortTrampolines - a CArrayAccessor of abort trampolines for 0, 1, 2 and N args methodOrBlockNumTemps - the number of method or block temps (including args) in the current compilation unit (method or block) optStatus - the variable used to track the status of ReceiverResultReg for avoiding reloading that register with self between adjacent inst var accesses + numPushNilsFunction + - the function used to determine the number of push nils at the beginning of a block. This abstracts away from the specific bytecode set(s). + picAbortTrampolines - a CArrayAccessor of abort trampolines for 0, 1, 2 and N args picMissTrampolines - a CArrayAccessor of abort trampolines for 0, 1, 2 and N args + pushNilSizeFunction + - the function used to determine the number of bytes in the push nils bytecode(s) at the beginning of a block. This abstracts away from the specific bytecode set(s). - realCEEnterCogCodePopReceiverArg0Regs realCEEnterCogCodePopReceiverArg1Arg0Regs - - the real trampolines for ebtering machine code with N reg args when in the Debug regime + realCECallCogCodePopReceiverArg0Regs realCECallCogCodePopReceiverArg1Arg0Regs + - the real trampolines for invoking machine code with N reg args when in the Debug regime + regArgsHaveBeenPushed - whether the register args have been pushed before frame build (e.g. when an interpreter primitive is called) + simNativeSpillBase + - the variable tracking how much of the Lowcode simulation stack has been spilled to the real stack + + simNativeStack + - the Lowcode simulation stack itself + + simNativeStackPtr + - the pointer to the top of the Lowcode simulation stack + + simNativeStackSize + - the size of the Lowcode stack so far + simSelf - the simulation stack entry representing self in the current compilation unit simSpillBase - the variable tracking how much of the simulation stack has been spilled to the real stack simStack - the simulation stack itself simStackPtr - the pointer to the top of the simulation stack useTwoPaths - a variable controlling whether to create two paths through a method based on the existence of inst var stores. With immutability this causes a frameless path to be generated if an otherwise frameless method is frameful simply because of inst var stores. In this case the test to take the first frameless path is if the receiver is not immutable. Without immutability, if a frameless method contains two or more inst var stores, the first path will be code with no store check, chosen by a single check for the receiver being in new space. ! StackToRegisterMappingCogit class instanceVariableNames: 'numPushNilsFunction pushNilSizeFunction'! Item was changed: ----- Method: StackToRegisterMappingCogit>>compileBlockBodies (in category 'compile abstract instructions') ----- compileBlockBodies <inline: false> | result compiledBlocksCount blockStart savedNeedsFrame savedNumArgs savedNumTemps initialStackPtr initialOpcodeIndex initialIndexOfIRC initialCounterIndex | <var: #blockStart type: #'BlockStart *'> self assert: blockCount > 0. "scanBlock: in compileBlockEntry: sets both of these appropriately for each block." savedNeedsFrame := needsFrame. savedNumArgs := methodOrBlockNumArgs. savedNumTemps := methodOrBlockNumTemps. inBlock := InVanillaBlock. compiledBlocksCount := 0. [compiledBlocksCount < blockCount] whileTrue: + [compilationPass := 1. - [blockPass := 1. blockStart := self blockStartAt: compiledBlocksCount. (result := self scanBlock: blockStart) < 0 ifTrue: [^result]. initialOpcodeIndex := opcodeIndex. initialCounterIndex := self maybeCounterIndex."for SistaCogit" + literalsManager saveForRecompile. - literalsManager saveForBlockCompile. NewspeakVM ifTrue: [initialIndexOfIRC := indexOfIRC]. [self compileBlockEntry: blockStart. initialStackPtr := simStackPtr. (result := self compileAbstractInstructionsFrom: blockStart startpc + (self pushNilSize: methodObj numInitialNils: blockStart numInitialNils) through: blockStart startpc + blockStart span - 1) < 0 ifTrue: [^result]. "If the final simStackPtr is less than the initial simStackPtr then scanBlock: over- estimated the number of initial nils (because it assumed one or more pushNils to produce an operand were pushNils to initialize temps. This is very rare, so compensate by checking, adjusting numInitialNils and recompiling the block body. N.B. No need to reinitialize the literalsManager because it answers existing literals." initialStackPtr = simStackPtr] whileFalse: [self assert: (initialStackPtr > simStackPtr or: [deadCode]). + compilationPass := compilationPass + 1. "for asserts" - blockPass := blockPass + 1. "for asserts :-(" blockStart numInitialNils: blockStart numInitialNils + simStackPtr - initialStackPtr. blockStart fakeHeader dependent: nil. self reinitializeFixupsFrom: blockStart startpc + blockStart numInitialNils through: blockStart startpc + blockStart span - 1. self cCode: 'bzero(abstractOpcodes + initialOpcodeIndex, (opcodeIndex - initialOpcodeIndex) * sizeof(AbstractInstruction))' inSmalltalk: [initialOpcodeIndex to: opcodeIndex - 1 do: [:i| abstractOpcodes at: i put: (CogCompilerClass for: self)]]. opcodeIndex := initialOpcodeIndex. self maybeSetCounterIndex: initialCounterIndex. "For SistaCogit" + literalsManager resetForRecompile. - literalsManager resetForBlockCompile. NewspeakVM ifTrue: [indexOfIRC := initialIndexOfIRC]]. compiledBlocksCount := compiledBlocksCount + 1]. needsFrame := savedNeedsFrame. methodOrBlockNumArgs := savedNumArgs. methodOrBlockNumTemps := savedNumTemps. ^0! Item was added: + ----- Method: StackToRegisterMappingCogit>>initializeFixup: (in category 'compile abstract instructions') ----- + initializeFixup: fixup + "Initialize a fixup. These are the targets of backward branches. A backward branch fixup's + simStackPtr needs to be set when generating the code for the bytecode at the targetPC. + Initially a fixup's target is just a flag. Later on it is replaced with a proper instruction." + <var: #fixup type: #'BytecodeFixup *'> + <inline: true> + fixup + becomeMergeFixup; + setIsBackwardBranchFixup! Item was changed: ----- Method: StackToRegisterMappingCogit>>initializeFixupAt: (in category 'compile abstract instructions') ----- initializeFixupAt: targetPC "Make sure there's a flagged fixup at the targetPC in fixups. + These are the targets of backward branches. A backward branch fixup's simStackPtr - These are the targets of backward branches. A backward branch fixup's simStackPtr needs to be set when generating the code for the bytecode at the targetPC. Initially a fixup's target is just a flag. Later on it is replaced with a proper instruction." - <returnTypeC: #'BytecodeFixup *'> | fixup | - <var: #fixup type: #'BytecodeFixup *'> fixup := self fixupAt: targetPC. + self initializeFixup: fixup! - fixup - becomeMergeFixup; - setIsBackwardBranchFixup. - ^fixup! Item was changed: ----- Method: StackToRegisterMappingCogit>>maybeCompilingFirstPassOfBlockWithInitialPushNil (in category 'debugging') ----- maybeCompilingFirstPassOfBlockWithInitialPushNil "For assert checking; or rather for avoiding assert fails when dealing with the hack for block temps in the SqueakV3PlusClosures bytecode set." + ^inBlock = InVanillaBlock and: [methodOrBlockNumTemps > methodOrBlockNumArgs and: [compilationPass = 1]]! - ^inBlock = InVanillaBlock and: [methodOrBlockNumTemps > methodOrBlockNumArgs and: [blockPass = 1]]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushAll (in category 'simulation stack') ----- ssFlushAll + <inline: true> self ssFlushTo: simStackPtr nativeFlushTo: simNativeStackPtr! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushTo: (in category 'simulation stack') ----- ssFlushTo: index + <inline: true> self ssFlushTo: index nativeFlushTo: simNativeStackPtr.! Item was changed: ----- Method: StackToRegisterMappingCogit>>traceMerge: (in category 'simulation only') ----- traceMerge: fixup <cmacro: '(ign) 0'> + | index original | - | index | (compilationTrace anyMask: 16) ifTrue: [index := (fixups object identityIndexOf: fixup) - 1. + (fixup isBackwardBranchFixup and: [compilationPass > 1 and: [(original := fixup simStackPtr) < 0]]) ifTrue: + [fixup simStackPtr: simStackPtr]. + + [coInterpreter transcript + ensureCr; + print: index; nextPut: $/; print: index + initialPC; + nextPut: $:; space. + fixup printStateOn: coInterpreter transcript. + coInterpreter transcript cr; flush] + ensure: [original ifNotNil: [fixup simStackPtr: original]]]! - coInterpreter transcript - ensureCr; - print: index; nextPut: $/; print: index + initialPC; - nextPut: $:; space. - fixup printStateOn: coInterpreter transcript. - coInterpreter transcript cr; flush]! Item was changed: ----- Method: VMStructType class>>printTypedefOn: (in category 'translation') ----- printTypedefOn: aStream aStream nextPutAll: 'typedef struct '. self needsTypeTag ifTrue: [aStream nextPutAll: self structTagName; space]. aStream nextPut: ${; cr. self instVarNamesAndTypesForTranslationDo: [:ivn :typeArg| | type | + ivn first == $# + ifTrue: [aStream nextPutAll: ivn] + ifFalse: + [type := typeArg. + #(BytesPerWord BaseHeaderSize BytesPerOop) do: + [:sizeConstant| | index sizeConstantSize | + (type notNil + and: [(index := type indexOf: sizeConstant ifAbsent: 0) > 0]) ifTrue: + [sizeConstantSize := VMBasicConstants classPool at: sizeConstant. + type := (type at: index + 1) = sizeConstantSize ifTrue: + [type := type copyReplaceFrom: index to: index + 1 with: #(). + type size = 1 ifTrue: [type first] ifFalse: [type]]]]. + type ifNotNil: + [type isArray + ifTrue: + [aStream tab: 1. + aStream nextPutAll: type first. + (type first last isSeparator or: [type first last = $*]) ifFalse: + [aStream tab: 2]. + aStream nextPutAll: ivn. + type last first isSeparator ifFalse: + [aStream space]. + aStream nextPutAll: type last] + ifFalse: + [aStream tab: 1. + aStream nextPutAll: type. + (type last isSeparator or: [type last = $*]) ifFalse: + [aStream tab: 1]. + aStream nextPutAll: ivn]]. + aStream nextPut: $;]. + aStream cr]. - type := typeArg. - #(BytesPerWord BaseHeaderSize BytesPerOop) do: - [:sizeConstant| | index sizeConstantSize | - (type notNil - and: [(index := type indexOf: sizeConstant ifAbsent: 0) > 0]) ifTrue: - [sizeConstantSize := VMBasicConstants classPool at: sizeConstant. - type := (type at: index + 1) = sizeConstantSize ifTrue: - [type := type copyReplaceFrom: index to: index + 1 with: #(). - type size = 1 ifTrue: [type first] ifFalse: [type]]]]. - type ifNotNil: - [type isArray - ifTrue: - [aStream tab: 1. - aStream nextPutAll: type first. - (type first last isSeparator or: [type first last = $*]) ifFalse: - [aStream tab: 2]. - aStream nextPutAll: ivn. - type last first isSeparator ifFalse: - [aStream space]. - aStream - nextPutAll: type last; - nextPut: $;; - cr] - ifFalse: - [aStream tab: 1. - aStream nextPutAll: type. - (type last isSeparator or: [type last = $*]) ifFalse: - [aStream tab: 1]. - aStream - nextPutAll: ivn; - nextPut: $;; - cr]]]. aStream nextPutAll: ' } '; nextPutAll: self structTypeName; nextPut: $;; cr. self name ~= self structTypeName ifTrue: [(self withAllSuperclasses copyUpThrough: (self class whichClassIncludesSelector: #structTypeName) theNonMetaClass) do: [:structClass| aStream cr; nextPutAll: '#define '; nextPutAll: structClass name; space; nextPutAll: self structTypeName]. aStream cr]. aStream flush!

3 2

VM Maker: VMMaker.oscog-eem.2146.mcz
by commits＠source.squeak.org 09 Mar '17

09 Mar '17

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2146.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2146 Author: eem Time: 8 March 2017, 3:49:13.650181 pm UUID: da6aee6e-4738-4161-b221-3c8135ac1bf7 Ancestors: VMMaker.oscog-rsf.2145 Fix code generation regression from VMMaker.oscog-eem.2144. =============== Diff against VMMaker.oscog-rsf.2145 =============== Item was removed: - ----- Method: CogAbstractInstruction>>reinitialize (in category 'initialization') ----- - reinitialize - annotation := nil. - dependent := nil. - operands at: 0 put: (operands at: 1 put: (operands at: 2 put: 0))! Item was added: + ----- Method: CogAbstractInstruction>>reinitializeOpcode (in category 'initialization') ----- + reinitializeOpcode + <inline: true> + annotation := nil. + dependent := nil. + operands at: 0 put: (operands at: 1 put: (operands at: 2 put: 0))! Item was changed: ----- Method: RegisterAllocatingCogit>>reinitializeOpcodesFrom:to: (in category 'bytecode generator support') ----- reinitializeOpcodesFrom: start to: end <inline: true> start to: end do: [:i| + (self abstractInstructionAt: i) reinitializeOpcode]! - (self abstractInstructionAt: i) reinitialize]!

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error generating latest sources (VMMaker.oscog-eem.2144)
by Esteban Lorenzano 08 Mar '17

08 Mar '17

Hi, I’m having this error when trying to generate sources from latest VMMaker 'conflicting implementations for #reinitialize’ as I see in the sources, CogAbstractInstruction>>reinitialize was recently added, but I have no idea how can I fix this problem :( any ideas? cheers! Esteban

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Crash in Objective-C autorelease pool management for events...
by Eliot Miranda 06 Mar '17

06 Mar '17

Hi, just got the following crash in a VM built from tip: Sisyphus.Cog$ spurcfvm -version /Users/eliot/oscogvm/build.macos32x86/squeak.cog.spur/CocoaFast.app/Contents/MacOS/Squeak 5.0 5.0.201703021704 Mac OS X built on Mar 2 2017 09:05:42 PST Compiler: 4.2.1 Compatible Apple LLVM 7.0.0 (clang-700.1.76) [Production Spur VM] CoInterpreter VMMaker.oscog-eem.2142 uuid: a11f8834-2f47-4326-aac8-64dac840dec3 Mar 2 2017 StackToRegisterMappingCogit VMMaker.oscog-eem.2142 uuid: a11f8834-2f47-4326-aac8-64dac840dec3 Mar 2 2017 VM: 201703021704 eliot@Sisyphus:oscogvm $ Date: Thu Mar 2 09:04:07 2017 -0800 $ Plugins: 201703021704 eliot@Sisyphus:oscogvm $ Segmentation fault Mon Mar 6 12:47:08 2017 VM: 201703021704 eliot@Sisyphus:oscogvm $ Date: Thu Mar 2 09:04:07 2017 -0800 $ Plugins: 201703021704 eliot@Sisyphus:oscogvm $ C stack backtrace & registers: eax 0x743c9450 ebx 0x734be010 ecx 0x996b2242 edx 0x20000000 edi 0x734be000 esi 0x734be000 ebp 0xbff20408 esp 0xbff201c8 eip 0x996930a7 0 libobjc.A.dylib 0x996930a7 objc_msgSend + 23 1 Squeak 0x0012716f reportStackState + 819 2 Squeak 0x001274e1 sigsegv + 129 3 libsystem_platform.dylib 0x947b903b _sigtramp + 43 4 ??? 0xffffffff 0x0 + 4294967295 5 CoreFoundation 0x92d5ddaf _CFAutoreleasePoolPop + 47 6 HIToolbox 0x9958a844 IMKInputSessionProcessEventRefWithCompletionHandler + 142 7 HIToolbox 0x99589954 InputMethodInstanceProcessEventRef_WithCompletionHandler + 115 8 HIToolbox 0x995726ed __TSMEventToInputMethod_WithCompletionHandler_block_invoke + 122 9 HIToolbox 0x99576e52 __TrySendLockEvent_BeforeEventToInputMethod_WithContinuationHandler_block_invoke + 33 10 HIToolbox 0x99576f29 __SendTSMDocumentLockEvent_WithCompletionHandler_block_invoke + 120 11 HIToolbox 0x9931f37f __SendTSMEvent_WithCompletionHandler_block_invoke + 72 12 HIToolbox 0x993224ca __SendEventToEventTargetWithCompletionHandler_block_invoke + 25 13 HIToolbox 0x9932249b ___ZL23DispatchEventToHandlersP14EventTargetRecP14OpaqueEventRefP14HandlerCallRec_block_invoke + 127 14 AppKit 0x9066f27c ___NSTSMEventHandler_block_invoke + 25 15 AppKit 0x90662273 -[NSTextInputContext handleTSMEvent:completionHandler:] + 1250 16 AppKit 0x90661d2b _NSTSMEventHandler + 302 17 HIToolbox 0x994825a4 _Z22_InvokeEventHandlerUPPP25OpaqueEventHandlerCallRefP14OpaqueEventRefPvPFlS0_S2_S3_E + 36 18 HIToolbox 0x992c0681 _ZL23DispatchEventToHandlersP14EventTargetRecP14OpaqueEventRefP14HandlerCallRec + 2291 19 HIToolbox 0x992bf65c _ZL30SendEventToEventTargetInternalP14OpaqueEventRefP20OpaqueEventTargetRefP14HandlerCallRec + 402 20 HIToolbox 0x992bf4c3 SendEventToEventTargetWithOptions + 95 21 HIToolbox 0x9931eff9 SendTSMEvent_WithCompletionHandler + 451 22 HIToolbox 0x9957262a TrySendLockEvent_BeforeEventToInputMethod_WithContinuationHandler + 409 23 HIToolbox 0x995723fb TSMEventToInputMethod_WithCompletionHandler + 154 24 HIToolbox 0x993034b8 TSMProcessRawKeyEventWithOptionsAndCompletionHandler + 3895 25 AppKit 0x90ce46a4 __61-[NSTextInputContext _handleEvent:options:completionHandler:]_block_invoke993 + 147 26 AppKit 0x90660652 -[NSTextInputContext tryTSMProcessRawKeyEvent:dispatchCondition:setupForDispatch:furtherCondition:dispatchWork:continuation:] + 129 27 AppKit 0x9066031d -[NSTextInputContext _handleEvent:options:completionHandler:] + 1708 28 AppKit 0x9065fc4e -[NSTextInputContext handleEvent:] + 128 29 AppKit 0x9065fb4b -[NSView interpretKeyEvents:] + 205 30 Squeak 0x00123588 -[sqSqueakOSXOpenGLView keyDown:] + 302 31 AppKit 0x90be7f9b -[NSWindow _reallySendEvent:isDelayedEvent:] + 8478 32 AppKit 0x904cb3ca -[NSWindow sendEvent:] + 526 33 AppKit 0x904c79c4 -[NSApplication sendEvent:] + 4765 34 Squeak 0x0011bda5 -[SqueakOSXApplication sendEvent:] + 106 35 Squeak 0x0011d9c8 -[sqSqueakOSXApplication(events) pumpRunLoopEventSendAndSignal:] + 115 36 Squeak 0x0011da66 -[sqSqueakOSXApplication(events) pumpRunLoop] + 76 37 Squeak 0x001257ca nativeIoProcessEvents + 208 38 Squeak 0x0012581e ioProcessEvents + 35 39 Squeak 0x00127ccb -[sqSqueakMainApplication(events) ioGetNextEvent:] + 23 40 Squeak 0x001258b1 ioGetNextEvent + 65 41 Squeak 0x000e4b50 primitiveGetNextEvent + 106 42 ??? 0x07286832 0x0 + 120088626 43 Squeak 0x000ad22c interpret + 635 44 Squeak 0x00128628 -[sqSqueakMainApplication runSqueak] + 476 45 Foundation 0x9486d0ae __NSFirePerformWithOrder + 416 46 CoreFoundation 0x92da781e __CFRUNLOOP_IS_CALLING_OUT_TO_AN_OBSERVER_CALLBACK_FUNCTION__ + 30 47 CoreFoundation 0x92da7760 __CFRunLoopDoObservers + 400 48 CoreFoundation 0x92d990c2 __CFRunLoopRun + 946 49 CoreFoundation 0x92d98aa6 CFRunLoopRunSpecific + 390 50 CoreFoundation 0x92d9890b CFRunLoopRunInMode + 123 51 HIToolbox 0x992e68f8 RunCurrentEventLoopInMode + 262 52 HIToolbox 0x992e6503 ReceiveNextEventCommon + 192 53 HIToolbox 0x992e642c _BlockUntilNextEventMatchingListInModeWithFilter + 99 54 AppKit 0x903f3b41 _DPSNextEvent + 742 55 AppKit 0x903f31e5 -[NSApplication nextEventMatchingMask:untilDate:inMode:dequeue:] + 350 56 AppKit 0x903e7b9c -[NSApplication run] + 907 57 AppKit 0x9035cfa0 NSApplicationMain + 2082 58 libdyld.dylib 0x970bb6d9 start + 1 Smalltalk stack dump: 0xbff4cb9c M EventSensor>fetchMoreEvents 0x7d93890: a(n) EventSensor 0xbff4cbb4 M EventSensor>nextEventFromQueue 0x7d93890: a(n) EventSensor 0xbff4cbcc M EventSensor>nextEvent 0x7d93890: a(n) EventSensor 0xbff4cbf4 M HandMorph>processEvents 0x906ce50: a(n) HandMorph 0xbff4cc10 M [] in WorldState>doOneCycleNowFor: 0x904a618: a(n) WorldState 0xbff4cc34 M Array(SequenceableCollection)>do: 0x869b950: a(n) Array 0xbff4cc50 M WorldState>handsDo: 0x904a618: a(n) WorldState 0xbff4cc70 M WorldState>doOneCycleNowFor: 0x904a618: a(n) WorldState 0xbff4cc8c M WorldState>doOneCycleFor: 0x904a618: a(n) WorldState 0xbff4cca8 M PasteUpMorph>doOneCycle 0x9036e90: a(n) PasteUpMorph 0xbff4ccc0 M [] in MorphicProject>spawnNewProcess 0x9036f58: a(n) MorphicProject 0xbff4cce0 I [] in BlockClosure>newProcess 0x144c4e00: a(n) BlockClosure Most recent primitives ... utcMicrosecondClock // primGetNextEvent: stack page bytes 4096 available headroom 2788 minimum unused headroom 2344 (Segmentation fault) _,,,^..^,,,_ best, Eliot

1 0

VM Maker: VMMaker.oscog-rsf.2145.mcz
by commits＠source.squeak.org 06 Mar '17

06 Mar '17

Ronie Salgado Faila uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-rsf.2145.mcz ==================== Summary ==================== Name: VMMaker.oscog-rsf.2145 Author: rsf Time: 6 March 2017, 5:35:20.115331 am UUID: 65262519-75c7-4e77-b531-4c7c5838a206 Ancestors: VMMaker.oscog-eem.2144 Refactoring the register allocation for the Lowcode instructions. The new register allocators are not yet tested because an error on the previous does not allow me to generate the sources for testing the refactoring. =============== Diff against VMMaker.oscog-eem.2144 =============== Item was changed: ----- Method: CCodeGenerator>>initializeCTranslationDictionary (in category 'C translation support') ----- initializeCTranslationDictionary "Initialize the dictionary mapping message names to actions for C code generation." | pairs | translationDict := Dictionary new: 200. pairs := #( #& #generateAnd:on:indent: #| #generateOr:on:indent: #abs #generateAbs:on:indent: #and: #generateSequentialAnd:on:indent: #or: #generateSequentialOr:on:indent: #not #generateNot:on:indent: #+ #generatePlus:on:indent: #- #generateMinus:on:indent: #negated #generateNegated:on:indent: #* #generateTimes:on:indent: #/ #generateDivide:on:indent: #// #generateDivide:on:indent: #\\ #generateModulo:on:indent: #<< #generateShiftLeft:on:indent: #>> #generateShiftRight:on:indent: #>>> #generateSignedShiftRight:on:indent: #min: #generateMin:on:indent: #max: #generateMax:on:indent: #between:and: #generateBetweenAnd:on:indent: #bitAnd: #generateBitAnd:on:indent: #bitOr: #generateBitOr:on:indent: #bitXor: #generateBitXor:on:indent: #bitShift: #generateBitShift:on:indent: #signedBitShift: #generateSignedBitShift:on:indent: #bitInvert32 #generateBitInvert:on:indent: #bitInvert64 #generateBitInvert:on:indent: #bitClear: #generateBitClear:on:indent: #truncateTo: #generateTruncateTo:on:indent: #rounded #generateRounded:on:indent: #byteSwap32 #generateByteSwap32:on:indent: #byteSwap64 #generateByteSwap64:on:indent: #byteSwapped32IfBigEndian: generateByteSwap32IfBigEndian:on:indent: #byteSwapped64IfBigEndian: generateByteSwap64IfBigEndian:on:indent: #< #generateLessThan:on:indent: #<= #generateLessThanOrEqual:on:indent: #= #generateEqual:on:indent: #> #generateGreaterThan:on:indent: #>= #generateGreaterThanOrEqual:on:indent: #~= #generateNotEqual:on:indent: #== #generateEqual:on:indent: #~~ #generateNotEqual:on:indent: #isNil #generateIsNil:on:indent: #notNil #generateNotNil:on:indent: #whileTrue: #generateWhileTrue:on:indent: #whileFalse: #generateWhileFalse:on:indent: #whileTrue #generateDoWhileTrue:on:indent: #whileFalse #generateDoWhileFalse:on:indent: #to:do: #generateToDo:on:indent: #to:by:do: #generateToByDo:on:indent: #repeat #generateRepeat:on:indent: #timesRepeat: #generateTimesRepeat:on:indent: #ifTrue: #generateIfTrue:on:indent: #ifFalse: #generateIfFalse:on:indent: #ifTrue:ifFalse: #generateIfTrueIfFalse:on:indent: #ifFalse:ifTrue: #generateIfFalseIfTrue:on:indent: #ifNotNil: #generateIfNotNil:on:indent: #ifNil: #generateIfNil:on:indent: #ifNotNil:ifNil: #generateIfNotNilIfNil:on:indent: #ifNil:ifNotNil: #generateIfNilIfNotNil:on:indent: #at: #generateAt:on:indent: #at:put: #generateAtPut:on:indent: #basicAt: #generateAt:on:indent: #basicAt:put: #generateAtPut:on:indent: #integerValueOf: #generateIntegerValueOf:on:indent: #integerObjectOf: #generateIntegerObjectOf:on:indent: #isIntegerObject: #generateIsIntegerObject:on:indent: #cCode: #generateInlineCCode:on:indent: #cCode:inSmalltalk: #generateInlineCCode:on:indent: #cPreprocessorDirective: #generateInlineCPreprocessorDirective:on:indent: #cppIf:ifTrue:ifFalse: #generateInlineCppIfElse:on:indent: #cppIf:ifTrue: #generateInlineCppIfElse:on:indent: #cCoerce:to: #generateCCoercion:on:indent: #cCoerceSimple:to: #generateCCoercion:on:indent: #addressOf: #generateAddressOf:on:indent: #addressOf:put: #generateAddressOf:on:indent: #asAddress:put: #generateAsAddress:on:indent: #signedIntFromLong64 #generateSignedIntFromLong64:on:indent: #signedIntFromLong #generateSignedIntFromLong:on:indent: #signedIntFromShort #generateSignedIntFromShort:on:indent: #signedIntToLong64 #generateSignedIntToLong64:on:indent: #signedIntToLong #generateSignedIntToLong:on:indent: #signedIntToShort #generateSignedIntToShort:on:indent: #preIncrement #generatePreIncrement:on:indent: #preDecrement #generatePreDecrement:on:indent: #inline: #generateInlineDirective:on:indent: #asFloat #generateAsFloat:on:indent: #asInteger #generateAsInteger:on:indent: #asIntegerPtr #generateAsIntegerPtr:on:indent: #asUnsignedInteger #generateAsUnsignedInteger:on:indent: #asUnsignedIntegerPtr #generateAsUnsignedIntegerPtr:on:indent: #asLong #generateAsLong:on:indent: #asUnsignedLong #generateAsUnsignedLong:on:indent: #asUnsignedLongLong #generateAsUnsignedLongLong:on:indent: #asVoidPointer #generateAsVoidPointer:on:indent: #asSymbol #generateAsSymbol:on:indent: #flag: #generateFlag:on:indent: #anyMask: #generateBitAnd:on:indent: #allMask: #generateAllMask:on:indent: #noMask: #generateNoMask:on:indent: #raisedTo: #generateRaisedTo:on:indent: #touch: #generateTouch:on:indent: #bytesPerOop #generateBytesPerOop:on:indent: #bytesPerWord #generateBytesPerWord:on:indent: #wordSize #generateBytesPerWord:on:indent: #baseHeaderSize #generateBaseHeaderSize:on:indent: #minSmallInteger #generateSmallIntegerConstant:on:indent: #maxSmallInteger #generateSmallIntegerConstant:on:indent: #sharedCodeNamed:inCase: #generateSharedCodeDirective:on:indent: #perform: #generatePerform:on:indent: #perform:with: #generatePerform:on:indent: #perform:with:with: #generatePerform:on:indent: #perform:with:with:with: #generatePerform:on:indent: #perform:with:with:with:with: #generatePerform:on:indent: #perform:with:with:with:with:with: #generatePerform:on:indent: #value #generateValue:on:indent: #value: #generateValue:on:indent: #value:value: #generateValue:on:indent: #value:value:value: #generateValue:on:indent: #value:value:value:value: #generateValue:on:indent: + #value:value:value:value:value: #generateValue:on:indent: + #value:value:value:value:value:value: #generateValue:on:indent: #deny: #generateDeny:on:indent: #shouldNotImplement #generateSmalltalkMetaError:on:indent: #shouldBeImplemented #generateSmalltalkMetaError:on:indent: #subclassResponsibility #generateSmalltalkMetaError:on:indent: ). 1 to: pairs size by: 2 do: [:i | translationDict at: (pairs at: i) put: (pairs at: i + 1)]. pairs := #( #ifTrue: #generateIfTrueAsArgument:on:indent: #ifFalse: #generateIfFalseAsArgument:on:indent: #ifTrue:ifFalse: #generateIfTrueIfFalseAsArgument:on:indent: #ifFalse:ifTrue: #generateIfFalseIfTrueAsArgument:on:indent: #ifNotNil: #generateIfNotNilAsArgument:on:indent: #ifNil: #generateIfNilAsArgument:on:indent: #ifNotNil:ifNil: #generateIfNotNilIfNilAsArgument:on:indent: #ifNil:ifNotNil: #generateIfNilIfNotNilAsArgument:on:indent: #cCode: #generateInlineCCodeAsArgument:on:indent: #cCode:inSmalltalk: #generateInlineCCodeAsArgument:on:indent: #cppIf:ifTrue:ifFalse: #generateInlineCppIfElseAsArgument:on:indent: #cppIf:ifTrue: #generateInlineCppIfElseAsArgument:on:indent: #value #generateValueAsArgument:on:indent: #value: #generateValueAsArgument:on:indent: #value:value: #generateValueAsArgument:on:indent: ). asArgumentTranslationDict := Dictionary new: 8. 1 to: pairs size by: 2 do: [:i | asArgumentTranslationDict at: (pairs at: i) put: (pairs at: i + 1)]. ! Item was added: + ----- Method: CogSimStackNativeEntry>>nativeRegisterSecondOrNone (in category 'accessing') ----- + nativeRegisterSecondOrNone + ^type = SSRegisterPair + ifTrue: [registerSecond] + ifFalse: [NoReg]! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateFloatRegNotConflictingWith: (in category 'simulation stack') ----- + allocateFloatRegNotConflictingWith: regMask + | reg | + "if there's a free register, use it" + reg := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: regMask). + reg = NoReg ifTrue: "No free register, choose one that does not conflict with regMask" + [reg := self freeAnyFloatRegNotConflictingWith: regMask]. + ^ reg! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloat2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeFloat2: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rTop topRegistersMask | + topRegistersMask := 0. + rTop := rNext := NoReg. + + self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ rTop := self ssNativeTop nativeFloatRegisterOrNone]. + (self ssNativeValue: 1) nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeFloatRegisterOrNone)]. + + rTop = NoReg ifTrue: + [ rTop := self allocateFloatRegNotConflictingWith: topRegistersMask ]. + + rNext = NoReg ifTrue: + [ rNext := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop) ]. + self deny: (rTop = NoReg or: [rNext = NoReg]). + + ^ aBlock value: rTop value: rNext + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloat2ResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeFloat2ResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | frNext frTop topRegistersMask rResult | + topRegistersMask := 0. + frTop := frNext := NoReg. + rResult := NoReg. + + self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ frTop := self ssNativeTop nativeFloatRegisterOrNone]. + (self ssNativeValue: 1) nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ topRegistersMask := self registerMaskFor: (frNext := (self ssNativeValue: 1) nativeFloatRegisterOrNone)]. + + frTop = NoReg ifTrue: + [ frTop := self allocateFloatRegNotConflictingWith: topRegistersMask ]. + + frNext = NoReg ifTrue: + [ frNext := self allocateFloatRegNotConflictingWith: (self registerMaskFor: frTop) ]. + + "Result" + rResult := self allocateRegNotConflictingWith: 0. + + self deny: (frTop = NoReg or: [frNext = NoReg or: [rResult]]). + + ^ aBlock value: frTop value: frNext value: rResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloat: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeFloat: aBlock + <option: #LowcodeVM> + <inline: true> + + | frTop topRegistersMask | + topRegistersMask := 0. + frTop := NoReg. + + self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ frTop := self ssNativeTop nativeFloatRegisterOrNone]. + + frTop = NoReg ifTrue: + [ frTop := self allocateFloatRegNotConflictingWith: topRegistersMask ]. + self deny: (frTop = NoReg). + + ^ aBlock value: frTop + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeFloatInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + "Used by storeFloat32ToMemory and storeFloat64ToMemory" + | frTop rTop | + frTop := rTop := NoReg. + + "Integer registers" + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: + [ rTop := self ssNativeTop nativeRegisterOrNone]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: 0 ]. + + "Float registers" + (self ssNativeValue: 1) nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ frTop := (self ssNativeValue: 1) nativeFloatRegisterOrNone]. + + frTop = NoReg ifTrue: + [ frTop := self allocateFloatRegNotConflictingWith: 0 ]. + + self deny: (frTop = NoReg or: [rTop = NoReg]). + + ^ aBlock value: frTop value: rTop! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatResultFloat: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeFloatResultFloat: aBlock + <option: #LowcodeVM> + <inline: true> + + | frTop frResult | + frTop := NoReg. + frResult := NoReg. + + "Float argument" + self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ frTop := self ssNativeTop nativeFloatRegisterOrNone]. + + frTop = NoReg ifTrue: + [ frTop := self allocateFloatRegNotConflictingWith: self emptyRegisterMask ]. + + "Float result". + frResult := self allocateFloatRegNotConflictingWith: (self registerMaskFor: frTop). + self deny: (frTop = NoReg or: [frResult = NoReg]). + + ^ aBlock value: frTop value: frResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatResultInteger2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeFloatResultInteger2: aBlock + <option: #LowcodeVM> + <inline: true> + + | frTop rResult rResult2 | + frTop := NoReg. + rResult2 := rResult := NoReg. + + "Float argument" + self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ frTop := self ssNativeTop nativeFloatRegisterOrNone]. + + frTop = NoReg ifTrue: + [ frTop := self allocateFloatRegNotConflictingWith: self emptyRegisterMask ]. + + "Integer result". + rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask). + rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rResult). + + self deny: (frTop = NoReg or: [rResult = NoReg or: [rResult2 = NoReg]]). + + ^ aBlock value: frTop value: rResult value: rResult2 + + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeFloatResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | frTop rResult | + frTop := NoReg. + rResult := NoReg. + + "Float argument" + self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ frTop := self ssNativeTop nativeFloatRegisterOrNone]. + + frTop = NoReg ifTrue: + [ frTop := self allocateFloatRegNotConflictingWith: self emptyRegisterMask ]. + + "Integer result". + rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask). + + self deny: (frTop = NoReg or: [rResult = NoReg]). + + ^ aBlock value: frTop value: rResult + + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatResultOop: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeFloatResultOop: aBlock + <option: #LowcodeVM> + <inline: true> + + | frTop rResult | + frTop := NoReg. + rResult := NoReg. + + "Float argument" + self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue: + [ frTop := self ssNativeTop nativeFloatRegisterOrNone]. + + frTop = NoReg ifTrue: + [ frTop := self allocateFloatRegNotConflictingWith: self emptyRegisterMask ]. + + "Integer result". + rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask). + + self deny: (frTop = NoReg or: [rResult = NoReg]). + + ^ aBlock value: frTop value: rResult + + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger2: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rTop topRegistersMask | + topRegistersMask := 0. + rTop := rNext := NoReg. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue: + [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)]. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: topRegistersMask ]. + + rNext = NoReg ifTrue: + [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ]. + + self deny: (rTop = NoReg or: [rNext = NoReg]). + ^ aBlock value: rTop value: rNext + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2ResultFloat: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger2ResultFloat: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rTop topRegistersMask frResult | + topRegistersMask := 0. + rTop := rNext := NoReg. + frResult := NoReg + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue: + [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)]. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: topRegistersMask ]. + + rNext = NoReg ifTrue: + [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ]. + + "Results" + frResult := self allocateFloatRegNotConflictingWith: self emptyRegisterMask. + + self deny: (rTop = NoReg or: [rNext = NoReg or: [frResult = NoReg]]). + + ^ aBlock value: rTop value: rNext value: frResult! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2ResultInteger2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger2ResultInteger2: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rTop topRegistersMask rResult rResult2 | + topRegistersMask := 0. + rTop := rNext := NoReg. + rResult := rResult2 := NoReg + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue: + [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)]. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: topRegistersMask ]. + + rNext = NoReg ifTrue: + [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ]. + + self deny: (rTop = NoReg or: [rNext = NoReg]). + + "Results" + rResult := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop and: rNext). + rResult2 := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rResult). + self deny: (rResult = NoReg or: [rResult2 = NoReg]). + + ^ aBlock value: rTop value: rNext value: rResult value: rResult2! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2ResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger2ResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rTop topRegistersMask rResult | + topRegistersMask := 0. + rTop := rNext := NoReg. + rResult := NoReg + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue: + [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)]. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: topRegistersMask ]. + + rNext = NoReg ifTrue: + [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ]. + + self deny: (rTop = NoReg or: [rNext = NoReg]). + + "Results" + rResult := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop and: rNext). + self deny: (rResult = NoReg). + + ^ aBlock value: rTop value: rNext value: rResult! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2ResultOop: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger2ResultOop: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rTop topRegistersMask rResult | + topRegistersMask := 0. + rTop := rNext := NoReg. + rResult := NoReg + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue: + [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)]. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: topRegistersMask ]. + + rNext = NoReg ifTrue: + [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ]. + + self deny: (rTop = NoReg or: [rNext = NoReg]). + + "Results" + rResult := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop and: rNext). + self deny: (rResult = NoReg). + + ^ aBlock value: rTop value: rNext value: rResult! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger3: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger3: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rNextNext nativeValueIndex rTop registerMask | + rTop := rNext := rNextNext := NoReg. + nativeValueIndex := 1. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone. + ]. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rNextNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + ]. + ]. + + rTop = NoReg ifTrue: [ + registerMask := 0. + rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext]. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rTop := self allocateRegNotConflictingWith: registerMask + ]. + + rNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rNext := self allocateRegNotConflictingWith: registerMask + ]. + + rNextNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop and: rNext. + rNextNext := self allocateRegNotConflictingWith: registerMask + ]. + + self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg]]). + ^ aBlock value: rTop value: rNext value: rNextNext + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger3ResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger3ResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rNextNext rResult nativeValueIndex rTop registerMask | + rTop := rNext := rNextNext := NoReg. + nativeValueIndex := 1. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone. + ]. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rNextNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + ]. + ]. + + rTop = NoReg ifTrue: [ + registerMask := 0. + rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext]. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rTop := self allocateRegNotConflictingWith: registerMask + ]. + + rNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rNext := self allocateRegNotConflictingWith: registerMask + ]. + + rNextNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop and: rNext. + rNextNext := self allocateRegNotConflictingWith: registerMask + ]. + + self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg]]). + + "Allocate the result" + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rNextNext). + self deny: (rResult = NoReg). + + ^ aBlock value: rTop value: rNext value: rNextNext value: rResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger4: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger4: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rNextNext rNextNextNext nativeValueIndex rTop registerMask | + rTop := rNext := rNextNext := rNextNextNext := NoReg. + nativeValueIndex := 1. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + ]. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rNextNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [ + rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone. + ]. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rNextNextNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rTop = NoReg ifTrue: [ + registerMask := 0. + rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext]. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)]. + rTop := self allocateRegNotConflictingWith: registerMask + ]. + + rNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)]. + rNext := self allocateRegNotConflictingWith: registerMask + ]. + + rNextNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop and: rNext. + rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)]. + rNextNext := self allocateRegNotConflictingWith: registerMask + ]. + + rNextNextNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop and: rNext and: rNextNext. + rNextNextNext := self allocateRegNotConflictingWith: registerMask + ]. + + self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg or: [rNextNextNext = NoReg]]]). + ^ aBlock value: rTop value: rNext value: rNextNext value: rNextNextNext + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger4ResultInteger2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger4ResultInteger2: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rNextNext rNextNextNext nativeValueIndex rTop registerMask rResult rResult2 | + rTop := rNext := rNextNext := rNextNextNext := NoReg. + rResult := rResult2 := NoReg. + nativeValueIndex := 1. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + ]. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rNextNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [ + rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone. + ]. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rNextNextNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rTop = NoReg ifTrue: [ + registerMask := 0. + rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext]. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)]. + rTop := self allocateRegNotConflictingWith: registerMask + ]. + + rNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)]. + rNext := self allocateRegNotConflictingWith: registerMask + ]. + + rNextNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop and: rNext. + rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)]. + rNextNext := self allocateRegNotConflictingWith: registerMask + ]. + + rNextNextNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop and: rNext and: rNextNext. + rNextNextNext := self allocateRegNotConflictingWith: registerMask + ]. + + self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg or: [rNextNextNext = NoReg]]]). + + "Result registers" + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rNextNext and: rNextNextNext). + rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rNextNext and: rNextNextNext and: rResult). + + ^ aBlock value: rTop value: rNext value: rNextNext value: rNextNextNext value: rResult value: rResult2 + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger4ResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger4ResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | rNext rNextNext rNextNextNext nativeValueIndex rTop registerMask rResult | + rTop := rNext := rNextNext := rNextNextNext := NoReg. + rResult := NoReg. + nativeValueIndex := 1. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue: + [ rNext := self ssNativeTop nativeRegisterSecondOrNone] + ]. + + rNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + ]. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rNextNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [ + rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone. + ]. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rNextNextNext = NoReg ifTrue: [ + (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [ + rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone. + nativeValueIndex := nativeValueIndex + 1 + ]. + ]. + + rTop = NoReg ifTrue: [ + registerMask := 0. + rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext]. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)]. + rTop := self allocateRegNotConflictingWith: registerMask + ]. + + rNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop. + rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)]. + rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)]. + rNext := self allocateRegNotConflictingWith: registerMask + ]. + + rNextNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop and: rNext. + rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)]. + rNextNext := self allocateRegNotConflictingWith: registerMask + ]. + + rNextNextNext = NoReg ifTrue: [ + registerMask := self registerMaskFor: rTop and: rNext and: rNextNext. + rNextNextNext := self allocateRegNotConflictingWith: registerMask + ]. + + self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg or: [rNextNextNext = NoReg]]]). + + "Result registers" + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rNextNext and: rNextNextNext). + + ^ aBlock value: rTop value: rNext value: rNextNext value: rNextNextNext value: rResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger7ResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger7ResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + "Effective address 64. This instruction should not be generated on 32-bits mode" + self abort + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | rTop | + rTop := NoReg. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask]. + + self deny: (rTop = NoReg). + ^ aBlock value: rTop + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerOop2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeIntegerOop2: aBlock + <option: #LowcodeVM> + <inline: true> + + | rTop rOopTop rOopNext topRegisterMask oopTopRegisterMask | + rTop := rOopTop := rOopNext := NoReg. + oopTopRegisterMask := topRegisterMask := 0. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + oopTopRegisterMask := self registerMaskFor: rTop. + ]. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + topRegisterMask := self registerMaskFor: rOopTop. + ]. + + (self ssValue: 1) registerOrNone ~= NoReg ifTrue: [ + rOopNext := (self ssValue: 1) registerOrNone. + topRegisterMask := topRegisterMask bitOr: (self registerMaskFor: rOopNext). + oopTopRegisterMask := oopTopRegisterMask bitOr: (self registerMaskFor: rOopNext). + ]. + + rTop = NoReg ifTrue: [ + rTop := self allocateRegNotConflictingWith: topRegisterMask + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: oopTopRegisterMask + ]. + + rOopNext = NoReg ifTrue: [ + rOopNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rOopTop) + ]. + + self deny: (rTop = NoReg or: [rOopTop = NoReg or: [rOopNext = NoReg]]). + ^ aBlock value: rTop value: rOopTop value: rOopNext + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerOop: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeIntegerOop: aBlock + <option: #LowcodeVM> + <inline: true> + + | rTop rOopTop topRegisterMask | + rTop := rOopTop := NoReg. + topRegisterMask := 0. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + ]. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + topRegisterMask := self registerMaskFor: rOopTop. + ]. + + rTop = NoReg ifTrue: [ + rTop := self allocateRegNotConflictingWith: topRegisterMask + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) + ]. + + self deny: (rTop = NoReg or: [rOopTop = NoReg]). + ^ aBlock value: rTop value: rOopTop + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerOopResultOop: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeIntegerOopResultOop: aBlock + <option: #LowcodeVM> + <inline: true> + + | rTop rOopTop rOopResult topRegisterMask | + rTop := rOopTop:= NoReg. + rOopResult := NoReg. + topRegisterMask := 0. + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + ]. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + topRegisterMask := self registerMaskFor: rOopTop. + ]. + + rTop = NoReg ifTrue: [ + rTop := self allocateRegNotConflictingWith: topRegisterMask + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) + ]. + + rOopResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rOopTop). + + self deny: (rTop = NoReg or: [rOopTop = NoReg or: [rOopResult = NoReg]]). + + ^ aBlock value: rTop value: rOopTop value: rOopResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerResultFloat: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeIntegerResultFloat: aBlock + <option: #LowcodeVM> + <inline: true> + + | rTop frResult| + rTop := NoReg. + frResult := NoReg + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask]. + + frResult := self allocateFloatRegNotConflictingWith: self emptyRegisterMask. + + self deny: (rTop = NoReg or: [frResult = NoReg]). + ^ aBlock value: rTop value: frResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerResultInteger2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeIntegerResultInteger2: aBlock + <option: #LowcodeVM> + <inline: true> + + | rTop rResult rResult2 | + rTop := NoReg. + rResult := rResult := NoReg + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask]. + + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop). + rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rResult). + + self deny: (rTop = NoReg or: [rResult = NoReg or: [rResult2 = NoReg]]). + ^ aBlock value: rTop value: rResult value: rResult2 + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeIntegerResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | rTop rResult| + rTop := NoReg. + rResult := NoReg + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask]. + + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop). + + self deny: (rTop = NoReg or: [rResult = NoReg]). + ^ aBlock value: rTop value: rResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerResultOop: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeIntegerResultOop: aBlock + <option: #LowcodeVM> + <inline: true> + + | rTop rResult| + rTop := NoReg. + rResult := NoReg + + self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [ + rTop := self ssNativeTop nativeRegisterOrNone. + ]. + + rTop = NoReg ifTrue: + [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask]. + + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop). + + self deny: (rTop = NoReg or: [rResult = NoReg]). + ^ aBlock value: rTop value: rResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOop2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeOop2: aBlock + <option: #LowcodeVM> + <inline: true> + + | rOopTop rOopNext oopTopRegisterMask | + rOopTop := rOopNext := NoReg. + oopTopRegisterMask := 0. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + ]. + + (self ssValue: 1) registerOrNone ~= NoReg ifTrue: [ + rOopNext := (self ssValue: 1) registerOrNone. + oopTopRegisterMask := self registerMaskFor: rOopNext. + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: oopTopRegisterMask + ]. + + rOopNext = NoReg ifTrue: [ + rOopNext := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop) + ]. + + self deny: (rOopTop = NoReg or: [rOopNext = NoReg ]). + ^ aBlock value: rOopTop value: rOopNext + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOop2ResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeOop2ResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | rOopTop rOopNext rResult oopTopRegisterMask | + rOopTop := rOopNext := NoReg. + rResult := NoReg. + oopTopRegisterMask := 0. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + ]. + + (self ssValue: 1) registerOrNone ~= NoReg ifTrue: [ + rOopNext := (self ssValue: 1) registerOrNone. + oopTopRegisterMask := self registerMaskFor: rOopNext. + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: oopTopRegisterMask + ]. + + rOopNext = NoReg ifTrue: [ + rOopNext := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop) + ]. + + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop and: rOopNext). + + self deny: (rOopTop = NoReg or: [rOopNext = NoReg or: [rResult = NoReg]]). + ^ aBlock value: rOopTop value: rOopNext value: rResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOop: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeOop: aBlock + <option: #LowcodeVM> + <inline: true> + + | rOopTop | + rOopTop := NoReg. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask) + ]. + + self deny: (rOopTop = NoReg). + ^ aBlock value: rOopTop + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOopResultFloat: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeOopResultFloat: aBlock + <option: #LowcodeVM> + <inline: true> + + | rOopTop frResult | + rOopTop := NoReg. + frResult := NoReg. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask) + ]. + + frResult := self allocateFloatRegNotConflictingWith: (self emptyRegisterMask). + + self deny: (rOopTop = NoReg or: [frResult = NoReg]). + ^ aBlock value: rOopTop value: frResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOopResultInteger2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeOopResultInteger2: aBlock + <option: #LowcodeVM> + <inline: true> + + | rOopTop rResult rResult2 | + rOopTop := NoReg. + rResult := rResult2 := NoReg. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask) + ]. + + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop). + rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop and: rResult). + + self deny: (rOopTop = NoReg or: [rResult = NoReg]). + ^ aBlock value: rOopTop value: rResult value: rResult2 + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOopResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeOopResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | rOopTop rResult | + rOopTop := NoReg. + rResult := NoReg. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask) + ]. + + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop). + + self deny: (rOopTop = NoReg or: [rResult = NoReg]). + ^ aBlock value: rOopTop value: rResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOopResultOop: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeOopResultOop: aBlock + <option: #LowcodeVM> + <inline: true> + + | rOopTop rResult | + rOopTop := NoReg. + rResult := NoReg. + + self ssTop registerOrNone ~= NoReg ifTrue: [ + rOopTop := self ssTop registerOrNone. + ]. + + rOopTop = NoReg ifTrue: [ + rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask) + ]. + + rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop). + + self deny: (rOopTop = NoReg or: [rResult = NoReg]). + ^ aBlock value: rOopTop value: rResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeResultFloat: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeResultFloat: aBlock + <option: #LowcodeVM> + <inline: true> + + | frResult | + frResult := NoReg. + + "Float result". + frResult := self allocateFloatRegNotConflictingWith: (self emptyRegisterMask). + self deny: (frResult = NoReg). + + ^ aBlock value: frResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeResultInteger2: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeResultInteger2: aBlock + <option: #LowcodeVM> + <inline: true> + + | rResult rResult2 | + rResult := rResult2 := NoReg. + + "Float result". + rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask). + rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rResult). + self deny: (rResult = NoReg or: [rResult2 = NoReg]). + + ^ aBlock value: rResult value: rResult2 + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeResultInteger: (in category 'inline primitive register allocation') ----- + allocateRegistersForLowcodeResultInteger: aBlock + <option: #LowcodeVM> + <inline: true> + + | rResult | + rResult := NoReg. + + "Float result". + rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask). + self deny: (rResult = NoReg). + + ^ aBlock value: rResult + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>freeAnyFloatRegNotConflictingWith: (in category 'simulation stack') ----- + freeAnyFloatRegNotConflictingWith: regMask + "Spill the closest register on stack not conflicting with regMask. + Assertion Failure if regMask has already all the registers" + <var: #desc type: #'CogSimStackEntry *'> + | reg index | + self assert: needsFrame. + reg := NoReg. + index := simSpillBase max: 0. + LowcodeVM ifTrue: [ + index := simNativeSpillBase max: 0. + [reg = NoReg and: [index < simNativeStackPtr]] whileTrue: + [ | desc | + desc := self simNativeStackAt: index. + (desc type = SSRegisterSingleFloat or: [desc type = SSRegisterDoubleFloat]) ifTrue: + [(regMask anyMask: (self registerMaskFor: desc register)) ifFalse: + [reg := desc register]]. + index := index + 1]. + ]. + self deny: reg = NoReg. + self ssAllocateRequiredFloatReg: reg. + ^reg! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeAdd32 (in category 'inline primitive generators generated code') ----- genLowcodeAdd32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self AddR: second R: first. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeAdd64 (in category 'inline primitive generators generated code') ----- genLowcodeAdd64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh first second firstLow | - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh first second firstHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue | + secondLow := secondLowValue. + secondHigh := secondHighValue. + firstLow := firstLowValue. + firstHigh := firstHighValue. + ]. - (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (secondLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)]. - - (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)]. - - (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstHigh := ClassReg)]. - (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh. self ssNativePop: 1. self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh. self ssNativePop: 1. self AddR: secondLow R: firstLow. self AddcR: secondHigh R: firstHigh. self ssPushNativeRegister: firstLow secondRegister: firstHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self AddR: second R: first. self ssPushNativeRegister: first. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeAlloca32 (in category 'inline primitive generators generated code') ----- genLowcodeAlloca32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | size | + self allocateRegistersForLowcodeInteger: [:sizeValue | + size := sizeValue. + ]. - (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (size := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - size = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: size. self ssNativePop: 1. self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg. self SubR: size R: TempReg. self AndCq: -16 R: TempReg. self MoveR: TempReg R: size. self MoveR: size Aw: coInterpreter nativeStackPointerAddress. self ssPushNativeRegister: size. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeAlloca64 (in category 'inline primitive generators generated code') ----- genLowcodeAlloca64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | sizeHigh size sizeLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:sizeLowValue :sizeHighValue | + sizeLow := sizeLowValue. + sizeHigh := sizeHighValue. + ]. - (sizeLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (sizeLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (sizeHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: sizeLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (sizeHigh := Arg1Reg)]. - (sizeLow = ReceiverResultReg or: [sizeHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: sizeLow secondReg: sizeHigh. self ssNativePop: 1. self SubR: sizeLow R: SPReg. self MoveR: SPReg R: sizeLow. self ssPushNativeRegister: sizeLow. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:sizeValue | + size := sizeValue. + ]. - (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (size := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - size = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: size. self ssNativePop: 1. self SubR: size R: SPReg. self MoveR: SPReg R: size. self ssPushNativeRegister: size. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeAnd32 (in category 'inline primitive generators generated code') ----- genLowcodeAnd32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self AndR: second R: first. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeAnd64 (in category 'inline primitive generators generated code') ----- genLowcodeAnd64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh first second firstLow | - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh first second firstHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue | + secondLow := secondLowValue. + secondHigh := secondHighValue. + firstLow := firstLowValue. + firstHigh := firstHighValue. + ]. - (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (secondLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)]. - - (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)]. - - (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstHigh := ClassReg)]. - (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh. self ssNativePop: 1. self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh. self ssNativePop: 1. self AndR: secondLow R: firstLow. self AndR: secondHigh R: firstHigh. self ssPushNativeRegister: firstLow secondRegister: firstHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self AndR: second R: first. self ssPushNativeRegister: first. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeArithmeticRightShift32 (in category 'inline primitive generators generated code') ----- genLowcodeArithmeticRightShift32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value shiftAmount | + self allocateRegistersForLowcodeInteger2: [:shiftAmountValue :valueValue | + shiftAmount := shiftAmountValue. + value := valueValue. + ]. - (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (shiftAmount := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: shiftAmount. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ArithmeticShiftRightR: shiftAmount R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeArithmeticRightShift64 (in category 'inline primitive generators generated code') ----- genLowcodeArithmeticRightShift64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value result shiftAmountHigh shiftAmount resultLow valueLow resultHigh shiftAmountLow valueHigh | + self allocateRegistersForLowcodeInteger2ResultInteger: [:shiftAmountValue :valueValue :resultValue | + shiftAmount := shiftAmountValue. + value := valueValue. + result := resultValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | value result shiftAmount shiftAmountHigh resultLow valueLow resultHigh shiftAmountLow valueHigh | - (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (shiftAmount := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: shiftAmount)) bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: shiftAmount. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeBeginCall (in category 'inline primitive generators generated code') ----- genLowcodeBeginCall + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | alignment | alignment := extA. self beginHighLevelCall: alignment. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeBoolean32ToOop (in category 'inline primitive generators generated code') ----- genLowcodeBoolean32ToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value inst cont object trueJump | + self allocateRegistersForLowcodeIntegerResultOop: [:valueValue :objectValue | + value := valueValue. + object := objectValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := Arg1Reg)]. - (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self CmpCq: 0 R: value. trueJump := self JumpNonZero: 0. "False" self annotate: (self MoveCw: objectMemory falseObject R: value) objRef: objectMemory falseObject. cont := self Jump: 0. "True" inst := self MoveCw: objectMemory trueObject R: value. trueJump jmpTarget: inst. self annotate: inst objRef: objectMemory trueObject. cont jmpTarget: self Label. self ssPushRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeBoolean64ToOop (in category 'inline primitive generators generated code') ----- genLowcodeBoolean64ToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value inst trueJump2 cont valueLow object trueJump valueHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2ResultOop: [:valueLowValue :valueHighValue :objectValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + object := objectValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - - (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := SendNumArgsReg)]. - ((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self OrR: valueLow R: valueHigh. trueJump := self JumpNonZero: 0. "False" self annotate: (self MoveCw: objectMemory falseObject R: valueLow) objRef: objectMemory falseObject. cont := self Jump: 0. "True" inst := self MoveCw: objectMemory trueObject R: valueLow. trueJump jmpTarget: inst. self annotate: inst objRef: objectMemory trueObject. cont jmpTarget: self Label. self ssPushRegister: valueLow. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultOop: [:valueValue :objectValue | + value := valueValue. + object := objectValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := Arg1Reg)]. - (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self CmpCq: 0 R: value. trueJump := self JumpNonZero: 0. "False" self annotate: (self MoveCw: objectMemory falseObject R: value) objRef: objectMemory falseObject. cont := self Jump: 0. "True" inst := self MoveCw: objectMemory trueObject R: value. trueJump jmpTarget: inst. self annotate: inst objRef: objectMemory trueObject. cont jmpTarget: self Label. self ssPushRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeByteSizeOf (in category 'inline primitive generators generated code') ----- genLowcodeByteSizeOf + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self ssFlushAll. objectRepresentation genLcByteSizeOf: object to: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeCallArgumentFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: DPFPReg0. self ssNativePop: 1. self MoveRs: DPFPReg0 M32: BytesPerWord negated r: SPReg. self SubCq: BytesPerWord R: SPReg. currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeCallArgumentFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: DPFPReg0. self ssNativePop: 1. self MoveRd: DPFPReg0 M64: -8 r: SPReg. self SubCq: 8 R: SPReg. currentCallCleanUpSize := currentCallCleanUpSize + 8. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentInt32 (in category 'inline primitive generators generated code') ----- genLowcodeCallArgumentInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: TempReg. self ssNativePop: 1. self PushR: TempReg. currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentInt64 (in category 'inline primitive generators generated code') ----- genLowcodeCallArgumentInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" BytesPerWord = 4 ifTrue: [ self ssNativeTop nativeStackPopToReg: TempReg secondReg: ReceiverResultReg. self ssNativePop: 1. self PushR: TempReg. self PushR: ReceiverResultReg. currentCallCleanUpSize := currentCallCleanUpSize + 8. ] ifFalse: [ self ssNativeTop nativeStackPopToReg: TempReg. self ssNativePop: 1. self PushR: TempReg. currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentPointer (in category 'inline primitive generators generated code') ----- genLowcodeCallArgumentPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: TempReg. self ssNativePop: 1. self PushR: TempReg. currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentSpace (in category 'inline primitive generators generated code') ----- genLowcodeCallArgumentSpace + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" "Allocate space" self SubCq: extA R: SPReg. currentCallCleanUpSize := currentCallCleanUpSize + extA. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentStructure (in category 'inline primitive generators generated code') ----- genLowcodeCallArgumentStructure + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" "Fetch the pointer" self ssNativeTop nativeStackPopToReg: TempReg. self ssNativePop: 1. "Allocate space" self SubCq: extA R: SPReg. currentCallCleanUpSize := currentCallCleanUpSize + extA. "Copy the structure" backEnd genMemCopy: TempReg to: SPReg constantSize: extA. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCallInstruction (in category 'inline primitive generators generated code') ----- genLowcodeCallInstruction + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | function | function := extA. self CallRT: function. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCallPhysical (in category 'inline primitive generators generated code') ----- genLowcodeCallPhysical + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | registerID | registerID := extA. self CallR: registerID. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCheckSessionIdentifier (in category 'inline primitive generators generated code') ----- genLowcodeCheckSessionIdentifier + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | expectedSession | expectedSession := extA. self ssPushNativeConstantInt32: (expectedSession = coInterpreter getThisSessionID ifTrue: [1] ifFalse: [0]). extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeCompareAndSwap32 (in category 'inline primitive generators generated code') ----- genLowcodeCompareAndSwap32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | newValue check oldValue value | + self allocateRegistersForLowcodeInteger3ResultInteger: [:newValueValue :oldValueValue :checkValue :valueValue | + newValue := newValueValue. + oldValue := oldValueValue. + check := checkValue. + value := valueValue. + ]. - (newValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (newValue := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (oldValue := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: newValue))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (oldValue := Arg1Reg)]. - - (check := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: newValue)) bitOr: (self registerMaskFor: oldValue))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (check := SendNumArgsReg)]. - - (value := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: newValue)) bitOr: (self registerMaskFor: oldValue)) bitOr: (self registerMaskFor: check))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := ClassReg)]. - (((newValue = ReceiverResultReg or: [oldValue = ReceiverResultReg]) or: [check = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: newValue. self ssNativePop: 1. self ssNativeTop nativePopToReg: oldValue. self ssNativePop: 1. self ssNativeTop nativePopToReg: check. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeDiv32 (in category 'inline primitive generators generated code') ----- genLowcodeDiv32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self DivR: second R: first Quo: first Rem: second. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeDiv64 (in category 'inline primitive generators generated code') ----- genLowcodeDiv64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue | + second := secondValue. + first := firstValue. + result := resultValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeDuplicateFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value dup2 | + self allocateRegistersForLowcodeFloatResultFloat: [:valueValue :dup2Value | + value := valueValue. + dup2 := dup2Value. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - - (dup2 := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (dup2 := DPFPReg1)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveRs: value Rs: dup2. self ssPushNativeRegisterSingleFloat: value; ssPushNativeRegisterSingleFloat: dup2. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeDuplicateFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value dup2 | + self allocateRegistersForLowcodeFloatResultFloat: [:valueValue :dup2Value | + value := valueValue. + dup2 := dup2Value. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - - (dup2 := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (dup2 := DPFPReg1)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveRd: value Rd: dup2. self ssPushNativeRegisterDoubleFloat: value; ssPushNativeRegisterDoubleFloat: dup2. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateInt32 (in category 'inline primitive generators generated code') ----- genLowcodeDuplicateInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value dup2 | + self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :dup2Value | + value := valueValue. + dup2 := dup2Value. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (dup2 := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (dup2 := Arg1Reg)]. - (value = ReceiverResultReg or: [dup2 = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value R: dup2. self ssPushNativeRegister: value; ssPushNativeRegister: dup2. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateInt64 (in category 'inline primitive generators generated code') ----- genLowcodeDuplicateInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value dup2Low dup2 valueLow dup2High valueHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2ResultInteger2: [:valueLowValue :valueHighValue :dup2LowValue :dup2HighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + dup2Low := dup2LowValue. + dup2High := dup2HighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - - (dup2Low := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (dup2Low := SendNumArgsReg)]. - - (dup2High := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh)) bitOr: (self registerMaskFor: dup2Low))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (dup2High := ClassReg)]. - (((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [dup2Low = ReceiverResultReg]) or: [dup2High = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self MoveR: valueLow R: dup2Low. self MoveR: valueHigh R: dup2High. self ssPushNativeRegister: valueLow secondRegister: valueHigh. self ssPushNativeRegister: dup2Low secondRegister: dup2High. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :dup2Value | + value := valueValue. + dup2 := dup2Value. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (dup2 := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (dup2 := Arg1Reg)]. - (value = ReceiverResultReg or: [dup2 = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value R: dup2. self ssPushNativeRegister: value. self ssPushNativeRegister: dup2. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicatePointer (in category 'inline primitive generators generated code') ----- genLowcodeDuplicatePointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | dup2 pointerValue | + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValueValue :dup2Value | + pointerValue := pointerValueValue. + dup2 := dup2Value. + ]. - (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointerValue := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (dup2 := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointerValue))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (dup2 := Arg1Reg)]. - (pointerValue = ReceiverResultReg or: [dup2 = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointerValue. self ssNativePop: 1. self MoveR: pointerValue R: dup2. self ssPushNativeRegister: pointerValue; ssPushNativeRegister: dup2. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeEffectiveAddress32 (in category 'inline primitive generators generated code') ----- genLowcodeEffectiveAddress32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | index base offset scale | + self allocateRegistersForLowcodeInteger4: [:offsetValue :scaleValue :indexValue :baseValue | + offset := offsetValue. + scale := scaleValue. + index := indexValue. + base := baseValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | offset base index scale | - (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (offset := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (scale := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (scale := Arg1Reg)]. - - (index := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (index := SendNumArgsReg)]. - - (base := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale)) bitOr: (self registerMaskFor: index))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (base := ClassReg)]. - (((offset = ReceiverResultReg or: [scale = ReceiverResultReg]) or: [index = ReceiverResultReg]) or: [base = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: offset. self ssNativePop: 1. self ssNativeTop nativePopToReg: scale. self ssNativePop: 1. self ssNativeTop nativePopToReg: index. self ssNativePop: 1. self ssNativeTop nativePopToReg: base. self ssNativePop: 1. self MulR: scale R: index. self AddR: index R: base. self AddR: offset R: base. self ssPushNativeRegister: base. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeEffectiveAddress64 (in category 'inline primitive generators generated code') ----- genLowcodeEffectiveAddress64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | base index indexLow indexHigh scaleHigh offsetLow scaleLow offset offsetHigh result scale | + self allocateRegistersForLowcodeInteger4ResultInteger: [:offsetValue :scaleValue :indexValue :baseValue :resultValue | + offset := offsetValue. + scale := scaleValue. + index := indexValue. + base := baseValue. + result := resultValue. + ]. - (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (offset := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (scale := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (scale := Arg1Reg)]. - - (index := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (index := SendNumArgsReg)]. - - (base := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale)) bitOr: (self registerMaskFor: index))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (base := ClassReg)]. - - (result := backEnd availableRegisterOrNoneFor: ((((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale)) bitOr: (self registerMaskFor: index)) bitOr: (self registerMaskFor: base))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := ReceiverResultReg)]. - ((((offset = ReceiverResultReg or: [scale = ReceiverResultReg]) or: [index = ReceiverResultReg]) or: [base = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: offset. self ssNativePop: 1. self ssNativeTop nativePopToReg: scale. self ssNativePop: 1. self ssNativeTop nativePopToReg: index. self ssNativePop: 1. self ssNativeTop nativePopToReg: base. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeEndCall (in category 'inline primitive generators generated code') ----- genLowcodeEndCall + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self endHighLevelCallWithCleanup. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeEndCallNoCleanup (in category 'inline primitive generators generated code') ----- genLowcodeEndCallNoCleanup + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self endHighLevelCallWithoutCleanup. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFirstFieldPointer (in category 'inline primitive generators generated code') ----- genLowcodeFirstFieldPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object | + self allocateRegistersForLowcodeOop: [:objectValue | + object := objectValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcFirstFieldPointer: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFirstIndexableFieldPointer (in category 'inline primitive generators generated code') ----- genLowcodeFirstIndexableFieldPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object | + self allocateRegistersForLowcodeOop: [:objectValue | + object := objectValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcFirstIndexableFieldPointer: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Add (in category 'inline primitive generators generated code') ----- genLowcodeFloat32Add + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self AddRs: second Rs: first. self ssPushNativeRegisterSingleFloat: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Div (in category 'inline primitive generators generated code') ----- genLowcodeFloat32Div + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self DivRs: second Rs: first. self ssPushNativeRegisterSingleFloat: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Equal (in category 'inline primitive generators generated code') ----- genLowcodeFloat32Equal + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRs: second Rs: first. falseJump := self JumpFPNotEqual: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Great (in category 'inline primitive generators generated code') ----- genLowcodeFloat32Great + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRs: second Rs: first. falseJump := self JumpFPLessOrEqual: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32GreatEqual (in category 'inline primitive generators generated code') ----- genLowcodeFloat32GreatEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRs: second Rs: first. falseJump := self JumpFPLess: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Less (in category 'inline primitive generators generated code') ----- genLowcodeFloat32Less + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRs: second Rs: first. falseJump := self JumpFPGreaterOrEqual: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32LessEqual (in category 'inline primitive generators generated code') ----- genLowcodeFloat32LessEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRs: second Rs: first. falseJump := self JumpFPGreater: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Mul (in category 'inline primitive generators generated code') ----- genLowcodeFloat32Mul + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self MulRs: second Rs: first. self ssPushNativeRegisterSingleFloat: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Neg (in category 'inline primitive generators generated code') ----- genLowcodeFloat32Neg + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result | + self allocateRegistersForLowcodeFloatResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - - (result := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg1)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self XorRs: result Rs: result. self SubRs: value Rs: result. self ssPushNativeRegisterSingleFloat: result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32NotEqual (in category 'inline primitive generators generated code') ----- genLowcodeFloat32NotEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRs: second Rs: first. falseJump := self JumpFPEqual: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Sqrt (in category 'inline primitive generators generated code') ----- genLowcodeFloat32Sqrt + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeFloat: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self SqrtRs: value. self ssPushNativeRegisterSingleFloat: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Sub (in category 'inline primitive generators generated code') ----- genLowcodeFloat32Sub + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self SubRs: second Rs: first. self ssPushNativeRegisterSingleFloat: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeFloat32ToFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | singleFloatValue | + self allocateRegistersForLowcodeFloat: [:singleFloatValueValue | + singleFloatValue := singleFloatValueValue. + ]. - (singleFloatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (singleFloatValue := DPFPReg0)]. self ssNativeTop nativePopToReg: singleFloatValue. self ssNativePop: 1. self ConvertRs: singleFloatValue Rd: singleFloatValue. self ssPushNativeRegisterDoubleFloat: singleFloatValue. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToInt32 (in category 'inline primitive generators generated code') ----- genLowcodeFloat32ToInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result | + self allocateRegistersForLowcodeFloatResultInteger: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - - (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (result := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - result = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ConvertRs: value R: result. self ssPushNativeRegister: result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToInt64 (in category 'inline primitive generators generated code') ----- genLowcodeFloat32ToInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | resultLow resultHigh value result | + self allocateRegistersForLowcodeFloatResultInteger: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - - (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (result := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - result = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToOop (in category 'inline primitive generators generated code') ----- genLowcodeFloat32ToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | singleFloatValue object | + self allocateRegistersForLowcodeFloatResultOop: [:singleFloatValueValue :objectValue | + singleFloatValue := singleFloatValueValue. + object := objectValue. + ]. - (singleFloatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (singleFloatValue := DPFPReg0)]. - - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: singleFloatValue. self ssNativePop: 1. self ssFlushAll. objectRepresentation genLcFloat32: singleFloatValue toOop: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToUInt32 (in category 'inline primitive generators generated code') ----- genLowcodeFloat32ToUInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result | + self allocateRegistersForLowcodeFloatResultInteger: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - - (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (result := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - result = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ConvertRs: value R: result. self ssPushNativeRegister: result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToUInt64 (in category 'inline primitive generators generated code') ----- genLowcodeFloat32ToUInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | resultLow resultHigh value result | + self allocateRegistersForLowcodeFloatResultInteger: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - - (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (result := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - result = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Add (in category 'inline primitive generators generated code') ----- genLowcodeFloat64Add + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self AddRd: second Rd: first. self ssPushNativeRegisterDoubleFloat: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Div (in category 'inline primitive generators generated code') ----- genLowcodeFloat64Div + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self DivRd: second Rd: first. self ssPushNativeRegisterDoubleFloat: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Equal (in category 'inline primitive generators generated code') ----- genLowcodeFloat64Equal + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRd: second Rd: first. falseJump := self JumpFPNotEqual: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Great (in category 'inline primitive generators generated code') ----- genLowcodeFloat64Great + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRd: second Rd: first. falseJump := self JumpFPLessOrEqual: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64GreatEqual (in category 'inline primitive generators generated code') ----- genLowcodeFloat64GreatEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRd: second Rd: first. falseJump := self JumpFPLess: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Less (in category 'inline primitive generators generated code') ----- genLowcodeFloat64Less + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRd: second Rd: first. falseJump := self JumpFPGreaterOrEqual: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64LessEqual (in category 'inline primitive generators generated code') ----- genLowcodeFloat64LessEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRd: second Rd: first. falseJump := self JumpFPGreater: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Mul (in category 'inline primitive generators generated code') ----- genLowcodeFloat64Mul + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self MulRd: second Rd: first. self ssPushNativeRegisterDoubleFloat: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Neg (in category 'inline primitive generators generated code') ----- genLowcodeFloat64Neg + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result | + self allocateRegistersForLowcodeFloatResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - - (result := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg1)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self XorRd: result Rd: result. self SubRd: value Rd: result. self ssPushNativeRegisterDoubleFloat: result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64NotEqual (in category 'inline primitive generators generated code') ----- genLowcodeFloat64NotEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. - - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpRd: second Rd: first. falseJump := self JumpFPEqual: 0. "True result" self MoveCq: 1 R: value. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: value. contJump jmpTarget: self Label. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Sqrt (in category 'inline primitive generators generated code') ----- genLowcodeFloat64Sqrt + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeFloat: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self SqrtRd: value. self ssPushNativeRegisterDoubleFloat: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Sub (in category 'inline primitive generators generated code') ----- genLowcodeFloat64Sub + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (second := DPFPReg0)]. - - (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (first := DPFPReg1)]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self SubRd: second Rd: first. self ssPushNativeRegisterDoubleFloat: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeFloat64ToFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | floatValue | + self allocateRegistersForLowcodeFloat: [:floatValueValue | + floatValue := floatValueValue. + ]. - (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)]. self ssNativeTop nativePopToReg: floatValue. self ssNativePop: 1. self ConvertRd: floatValue Rs: floatValue. self ssPushNativeRegisterSingleFloat: floatValue. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToInt32 (in category 'inline primitive generators generated code') ----- genLowcodeFloat64ToInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | floatValue int32Result | + self allocateRegistersForLowcodeFloatResultInteger: [:floatValueValue :int32ResultValue | + floatValue := floatValueValue. + int32Result := int32ResultValue. + ]. - (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)]. - - (int32Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (int32Result := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - int32Result = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: floatValue. self ssNativePop: 1. self ConvertRd: floatValue R: int32Result. self ssPushNativeRegister: int32Result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToInt64 (in category 'inline primitive generators generated code') ----- genLowcodeFloat64ToInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | floatValue int64ResultLow int64Result int64ResultHigh | + self allocateRegistersForLowcodeFloatResultInteger: [:floatValueValue :int64ResultValue | + floatValue := floatValueValue. + int64Result := int64ResultValue. + ]. - (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)]. - - (int64Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (int64Result := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - int64Result = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: floatValue. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToOop (in category 'inline primitive generators generated code') ----- genLowcodeFloat64ToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | floatValue object | + self allocateRegistersForLowcodeFloatResultOop: [:floatValueValue :objectValue | + floatValue := floatValueValue. + object := objectValue. + ]. - (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)]. - - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: floatValue. self ssNativePop: 1. self ssFlushAll. objectRepresentation genLcFloat64: floatValue toOop: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToUInt32 (in category 'inline primitive generators generated code') ----- genLowcodeFloat64ToUInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | floatValue int64Result | + self allocateRegistersForLowcodeFloatResultInteger: [:floatValueValue :int64ResultValue | + floatValue := floatValueValue. + int64Result := int64ResultValue. + ]. - (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)]. - - (int64Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (int64Result := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - int64Result = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: floatValue. self ssNativePop: 1. self ConvertRd: floatValue R: int64Result. self ssPushNativeRegister: int64Result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToUInt64 (in category 'inline primitive generators generated code') ----- genLowcodeFloat64ToUInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | floatValue int64ResultLow int64Result int64ResultHigh | + self allocateRegistersForLowcodeFloatResultInteger: [:floatValueValue :int64ResultValue | + floatValue := floatValueValue. + int64Result := int64ResultValue. + ]. - (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)]. - - (int64Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (int64Result := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - int64Result = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: floatValue. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeFree (in category 'inline primitive generators generated code') ----- genLowcodeFree + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer | + self allocateRegistersForLowcodeInteger: [:pointerValue | + pointer := pointerValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssFlushAll. pointer ~= ReceiverResultReg ifTrue: [self MoveR: pointer R: ReceiverResultReg ]. self CallRT: ceFreeTrampoline. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInstantiateIndexable32Oop (in category 'inline primitive generators generated code') ----- genLowcodeInstantiateIndexable32Oop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | indexableSize object classOop | + self allocateRegistersForLowcodeIntegerOopResultOop: [:indexableSizeValue :classOopValue :objectValue | + indexableSize := indexableSizeValue. + classOop := classOopValue. + object := objectValue. + ]. - (indexableSize := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (indexableSize := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (classOop := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: indexableSize))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (classOop := Arg1Reg)]. - - (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: indexableSize)) bitOr: (self registerMaskFor: classOop))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := SendNumArgsReg)]. - ((indexableSize = ReceiverResultReg or: [classOop = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: indexableSize. self ssNativePop: 1. self ssTop popToReg: classOop. self ssPop: 1. self ssFlushAll. objectRepresentation genLcInstantiateOop: classOop indexableSize: indexableSize. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInstantiateIndexableOop (in category 'inline primitive generators generated code') ----- genLowcodeInstantiateIndexableOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | indexableSize object classOop | indexableSize := extA. + self allocateRegistersForLowcodeOopResultOop: [:classOopValue :objectValue | + classOop := classOopValue. + object := objectValue. + ]. - (classOop := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (classOop := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: classOop))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := Arg1Reg)]. - (classOop = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: classOop. self ssPop: 1. self ssFlushAll. objectRepresentation genLcInstantiateOop: classOop constantIndexableSize: indexableSize. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInstantiateOop (in category 'inline primitive generators generated code') ----- genLowcodeInstantiateOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | classOop | + self allocateRegistersForLowcodeOop: [:classOopValue | + classOop := classOopValue. + ]. - (classOop := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (classOop := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - classOop = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: classOop. self ssPop: 1. self ssFlushAll. objectRepresentation genLcInstantiateOop: classOop. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32Equal (in category 'inline primitive generators generated code') ----- genLowcodeInt32Equal + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpNonZero: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32Great (in category 'inline primitive generators generated code') ----- genLowcodeInt32Great + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpLessOrEqual: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32GreatEqual (in category 'inline primitive generators generated code') ----- genLowcodeInt32GreatEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpLess: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32Less (in category 'inline primitive generators generated code') ----- genLowcodeInt32Less + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpGreaterOrEqual: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32LessEqual (in category 'inline primitive generators generated code') ----- genLowcodeInt32LessEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpGreater: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32NotEqual (in category 'inline primitive generators generated code') ----- genLowcodeInt32NotEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpZero: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeInt32ToFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result | + self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg0)]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ConvertR: value Rs: result. self ssPushNativeRegisterSingleFloat: result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeInt32ToFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result | + self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg0)]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ConvertR: value Rd: result. self ssPushNativeRegisterDoubleFloat: result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToOop (in category 'inline primitive generators generated code') ----- genLowcodeInt32ToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ssFlushAll. objectRepresentation genLcInt32ToOop: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToPointer (in category 'inline primitive generators generated code') ----- genLowcodeInt32ToPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. "TODO: Perform a NOP here" self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64Equal (in category 'inline primitive generators generated code') ----- genLowcodeInt64Equal + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | falseLabel first contJump falseJump secondLow secondHigh second falseJump2 firstHigh firstLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue | + secondLow := secondLowValue. + secondHigh := secondHighValue. + firstLow := firstLowValue. + firstHigh := firstHighValue. + ]. - (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (secondLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)]. - - (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)]. - - (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstHigh := ClassReg)]. - (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh. self ssNativePop: 1. self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh. self ssNativePop: 1. self CmpR: secondHigh R: firstHigh. falseJump := self JumpNonZero: 0. self CmpR: secondLow R: firstLow. falseJump2 := self JumpNonZero: 0. "True result" self MoveCq: 1 R: firstLow. contJump := self Jump: 0. "False result" falseLabel := self MoveCq: 0 R: firstLow. falseJump jmpTarget: falseLabel. falseJump2 jmpTarget: falseLabel. contJump jmpTarget: self Label. self ssPushNativeRegister: firstLow. ] ifFalse: [ + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpNonZero: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64Great (in category 'inline primitive generators generated code') ----- genLowcodeInt64Great + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh value first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh value first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64GreatEqual (in category 'inline primitive generators generated code') ----- genLowcodeInt64GreatEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh value first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh value first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64Less (in category 'inline primitive generators generated code') ----- genLowcodeInt64Less + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh value first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh value first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64LessEqual (in category 'inline primitive generators generated code') ----- genLowcodeInt64LessEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh value first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh value first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64NotEqual (in category 'inline primitive generators generated code') ----- genLowcodeInt64NotEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | falseLabel first contJump falseJump secondLow secondHigh second falseJump2 firstHigh firstLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue | + secondLow := secondLowValue. + secondHigh := secondHighValue. + firstLow := firstLowValue. + firstHigh := firstHighValue. + ]. - (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (secondLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)]. - - (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)]. - - (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstHigh := ClassReg)]. - (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh. self ssNativePop: 1. self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh. self ssNativePop: 1. self CmpR: secondHigh R: firstHigh. falseJump := self JumpNonZero: 0. self CmpR: secondLow R: firstLow. falseJump2 := self JumpNonZero: 0. "False result" self MoveCq: 0 R: firstLow. contJump := self Jump: 0. "True result" falseLabel := self MoveCq: 1 R: firstLow. falseJump jmpTarget: falseLabel. falseJump2 jmpTarget: falseLabel. contJump jmpTarget: self Label. self ssPushNativeRegister: firstLow. ] ifFalse: [ + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpZero: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeInt64ToFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow result | + self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg0)]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeInt64ToFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow result | + self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg0)]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToOop (in category 'inline primitive generators generated code') ----- genLowcodeInt64ToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self ssFlushAll. objectRepresentation genLcInt64ToOop: valueLow highPart: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ssFlushAll. objectRepresentation genLcInt64ToOop: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToPointer (in category 'inline primitive generators generated code') ----- genLowcodeInt64ToPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self ssPushNativeRegister: valueLow. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeIsBytes (in category 'inline primitive generators generated code') ----- genLowcodeIsBytes + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcIsBytes: object to: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeIsFloatObject (in category 'inline primitive generators generated code') ----- genLowcodeIsFloatObject + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcIsFloatObject: object to: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeIsIndexable (in category 'inline primitive generators generated code') ----- genLowcodeIsIndexable + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcIsIndexable: object to: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeIsIntegerObject (in category 'inline primitive generators generated code') ----- genLowcodeIsIntegerObject + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcIsIntegerObject: object to: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeIsPointers (in category 'inline primitive generators generated code') ----- genLowcodeIsPointers + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcIsPointers: object to: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeIsWords (in category 'inline primitive generators generated code') ----- genLowcodeIsWords + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcIsWords: object to: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeIsWordsOrBytes (in category 'inline primitive generators generated code') ----- genLowcodeIsWordsOrBytes + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcIsWordsOrBytes: object to: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLeftShift32 (in category 'inline primitive generators generated code') ----- genLowcodeLeftShift32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value shiftAmount | + self allocateRegistersForLowcodeInteger2: [:shiftAmountValue :valueValue | + shiftAmount := shiftAmountValue. + value := valueValue. + ]. - (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (shiftAmount := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: shiftAmount. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self LogicalShiftLeftR: shiftAmount R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLeftShift64 (in category 'inline primitive generators generated code') ----- genLowcodeLeftShift64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value result shiftAmountHigh shiftAmount resultLow valueLow resultHigh shiftAmountLow valueHigh | + self allocateRegistersForLowcodeInteger2ResultInteger: [:shiftAmountValue :valueValue :resultValue | + shiftAmount := shiftAmountValue. + value := valueValue. + result := resultValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | value result shiftAmount shiftAmountHigh resultLow valueLow resultHigh shiftAmountLow valueHigh | - (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (shiftAmount := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: shiftAmount)) bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: shiftAmount. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentAddress (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentAddress + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | pointer baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset pointer | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:pointerValue | + pointer := pointerValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: pointer. self ssPushNativeRegister: pointer. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | floatValue baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset floatValue | baseOffset := extA. + self allocateRegistersForLowcodeResultFloat: [:floatValueValue | + floatValue := floatValueValue. + ]. - (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg Rs: floatValue. self ssPushNativeRegisterSingleFloat: floatValue. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | doubleValue baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset doubleValue | baseOffset := extA. + self allocateRegistersForLowcodeResultFloat: [:doubleValueValue | + doubleValue := doubleValueValue. + ]. - (doubleValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (doubleValue := DPFPReg0)]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM64: 0 r: TempReg Rd: doubleValue. self ssPushNativeRegisterDoubleFloat: doubleValue. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt16 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentInt16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM16: 0 r: TempReg R: value. self SignExtend16R: value R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt32 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt64 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | valueHigh value valueLow baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value valueLow valueHigh | baseOffset := extA. BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeResultInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. - "TODO: Check the endianness" self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg R: valueLow. self MoveM32: 4 r: TempReg R: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM64: 0 r: TempReg R: value. self ssPushNativeRegister: value. ]. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt8 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentInt8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM8: 0 r: TempReg R: value. self SignExtend8R: value R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentPointer (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | pointerResult baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset pointerResult | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:pointerResultValue | + pointerResult := pointerResultValue. + ]. - (pointerResult := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointerResult := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointerResult = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveMw: 0 r: TempReg R: pointerResult. self ssPushNativeRegister: pointerResult. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt16 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentUInt16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM16: 0 r: TempReg R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt32 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentUInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt64 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentUInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | valueHigh value valueLow baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value valueLow valueHigh | baseOffset := extA. BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeResultInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. - "TODO: Check the endianness" self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg R: valueLow. self MoveM32: 4 r: TempReg R: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM64: 0 r: TempReg R: value. self ssPushNativeRegister: value. ]. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt8 (in category 'inline primitive generators generated code') ----- genLowcodeLoadArgumentUInt8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeArgumentAddress: baseOffset to: TempReg. self MoveM8: 0 r: TempReg R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadFloat32FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadFloat32FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeIntegerResultFloat: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM32: 0 r: pointer Rs: value. self ssPushNativeRegisterSingleFloat: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadFloat64FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadFloat64FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeIntegerResultFloat: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM64: 0 r: pointer Rd: value. self ssPushNativeRegisterDoubleFloat: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt16FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadInt16FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM16: 0 r: pointer R: value. self SignExtend16R: value R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt32FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadInt32FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM32: 0 r: pointer R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt64FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadInt64FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh pointer value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeIntegerResultInteger2: [:pointerValue :valueLowValue :valueHighValue | + pointer := pointerValue. + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueLow := Arg1Reg)]. - - (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)]. - ((pointer = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. "TODO: Check the endianness" self MoveM32: 0 r: pointer R: valueLow. self MoveM32: 4 r: pointer R: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM64: 0 r: pointer R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt8FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadInt8FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM8: 0 r: pointer R: value. self SignExtend8R: value R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalAddress (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalAddress + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | pointer baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset pointer | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:pointerValue | + pointer := pointerValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: pointer. self ssPushNativeRegister: pointer. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | floatValue baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset floatValue | baseOffset := extA. + self allocateRegistersForLowcodeResultFloat: [:floatValueValue | + floatValue := floatValueValue. + ]. - (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg Rs: floatValue. self ssPushNativeRegisterSingleFloat: floatValue. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | doubleValue baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset doubleValue | baseOffset := extA. + self allocateRegistersForLowcodeResultFloat: [:doubleValueValue | + doubleValue := doubleValueValue. + ]. - (doubleValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (doubleValue := DPFPReg0)]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM64: 0 r: TempReg Rd: doubleValue. self ssPushNativeRegisterDoubleFloat: doubleValue. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt16 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalInt16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM16: 0 r: TempReg R: value. self SignExtend16R: value R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt32 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt64 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | valueHigh value valueLow baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value valueLow valueHigh | baseOffset := extA. BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeResultInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. - "TODO: Check the endianness" self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg R: valueLow. self MoveM32: 4 r: TempReg R: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM64: 0 r: TempReg R: value. self ssPushNativeRegister: value. ]. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt8 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalInt8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM8: 0 r: TempReg R: value. self SignExtend8R: value R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalPointer (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | pointerResult baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset pointerResult | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:pointerResultValue | + pointerResult := pointerResultValue. + ]. - (pointerResult := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointerResult := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointerResult = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveMw: 0 r: TempReg R: pointerResult. self ssPushNativeRegister: pointerResult. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt16 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalUInt16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM16: 0 r: TempReg R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt32 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalUInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt64 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalUInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | valueHigh value valueLow baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value valueLow valueHigh | baseOffset := extA. BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeResultInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. - "TODO: Check the endianness" self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM32: 0 r: TempReg R: valueLow. self MoveM32: 4 r: TempReg R: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM64: 0 r: TempReg R: value. self ssPushNativeRegister: value. ]. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt8 (in category 'inline primitive generators generated code') ----- genLowcodeLoadLocalUInt8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value baseOffset | - <option: #LowcodeVM> "Lowcode instruction generator" - | baseOffset value | baseOffset := extA. + self allocateRegistersForLowcodeResultInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveM8: 0 r: TempReg R: value. self ssPushNativeRegister: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadObjectAt (in category 'inline primitive generators generated code') ----- genLowcodeLoadObjectAt + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | fieldIndex object | + self allocateRegistersForLowcodeIntegerOop: [:fieldIndexValue :objectValue | + fieldIndex := fieldIndexValue. + object := objectValue. + ]. - (fieldIndex := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (fieldIndex := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: fieldIndex))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := Arg1Reg)]. - (fieldIndex = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: fieldIndex. self ssNativePop: 1. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcLoadObject: object at: fieldIndex. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadObjectField (in category 'inline primitive generators generated code') ----- genLowcodeLoadObjectField + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | fieldIndex object | fieldIndex := extA. + self allocateRegistersForLowcodeOop: [:objectValue | + object := objectValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcLoadObject: object field: fieldIndex. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadPointerFromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadPointerFromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointerResult pointer | + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :pointerResultValue | + pointer := pointerValue. + pointerResult := pointerResultValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (pointerResult := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (pointerResult := Arg1Reg)]. - (pointer = ReceiverResultReg or: [pointerResult = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveMw: 0 r: pointer R: pointerResult. self ssPushNativeRegister: pointerResult. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt16FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadUInt16FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM16: 0 r: pointer R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt32FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadUInt32FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM32: 0 r: pointer R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt64FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadUInt64FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh pointer value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeIntegerResultInteger2: [:pointerValue :valueLowValue :valueHighValue | + pointer := pointerValue. + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueLow := Arg1Reg)]. - - (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)]. - ((pointer = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. "TODO: Check the endianness" self MoveM32: 0 r: pointer R: valueLow. self MoveM32: 4 r: pointer R: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM64: 0 r: pointer R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt8FromMemory (in category 'inline primitive generators generated code') ----- genLowcodeLoadUInt8FromMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveM8: 0 r: pointer R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLocalFrameSize (in category 'inline primitive generators generated code') ----- genLowcodeLocalFrameSize + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | alignedSize size | - <option: #LowcodeVM> "Lowcode instruction generator" - | size alignedSize | size := extA. self assert: needsFrame. hasNativeFrame := true. "Align the size to 16 bytes." alignedSize := size + 15 bitAnd: -16. "Mark the stack frame" self annotate: (self MoveCw: (objectMemory splObj: LowcodeContextMark) R: TempReg) objRef: (objectMemory splObj: LowcodeContextMark). self MoveR: TempReg Mw: self frameOffsetOfNativeFrameMark r: FPReg. "Fetch the stack" self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg. self AddCq: 1 R: TempReg. self MoveR: TempReg Mw: self frameOffsetOfPreviousNativeStackPointer r: FPReg. "Store the frame pointer" self SubCq: alignedSize R: TempReg. self MoveR: TempReg Mw: self frameOffsetOfNativeFramePointer r: FPReg. "Store the new stack pointer" self MoveR: TempReg Mw: self frameOffsetOfNativeStackPointer r: FPReg. "Allocate space for the locals" self SubCq: 1 + coInterpreter defaultNativeStackFrameSize R: TempReg. self MoveR: TempReg Aw: coInterpreter nativeStackPointerAddress. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLockRegisters (in category 'inline primitive generators generated code') ----- genLowcodeLockRegisters + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssFlushAll. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeLockVM (in category 'inline primitive generators generated code') ----- genLowcodeLockVM + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMalloc32 (in category 'inline primitive generators generated code') ----- genLowcodeMalloc32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer size | + self allocateRegistersForLowcodeIntegerResultInteger: [:sizeValue :pointerValue | + size := sizeValue. + pointer := pointerValue. + ]. - (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (size := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (pointer := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (pointer := Arg1Reg)]. - (size = ReceiverResultReg or: [pointer = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: size. self ssNativePop: 1. self ssFlushAll. size ~= ReceiverResultReg ifTrue: [self MoveR: size R: ReceiverResultReg ]. self CallRT: ceMallocTrampoline. self MoveR: TempReg R: pointer. self ssPushNativeRegister: pointer. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMalloc64 (in category 'inline primitive generators generated code') ----- genLowcodeMalloc64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | sizeHigh size sizeLow pointer | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2ResultInteger: [:sizeLowValue :sizeHighValue :pointerValue | + sizeLow := sizeLowValue. + sizeHigh := sizeHighValue. + pointer := pointerValue. + ]. - (sizeLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (sizeLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (sizeHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: sizeLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (sizeHigh := Arg1Reg)]. - - (pointer := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: sizeLow)) bitOr: (self registerMaskFor: sizeHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (pointer := SendNumArgsReg)]. - ((sizeLow = ReceiverResultReg or: [sizeHigh = ReceiverResultReg]) or: [pointer = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: sizeLow secondReg: sizeHigh. self ssNativePop: 1. self ssFlushAll. sizeLow ~= ReceiverResultReg ifTrue: [self MoveR: sizeLow R: ReceiverResultReg ]. self CallRT: ceMallocTrampoline. self MoveR: TempReg R: pointer. self ssPushNativeRegister: pointer. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultInteger: [:sizeValue :pointerValue | + size := sizeValue. + pointer := pointerValue. + ]. - (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (size := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (pointer := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (pointer := Arg1Reg)]. - (size = ReceiverResultReg or: [pointer = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: size. self ssNativePop: 1. self ssFlushAll. size ~= ReceiverResultReg ifTrue: [self MoveR: size R: ReceiverResultReg ]. self CallRT: ceMallocTrampoline. self MoveR: TempReg R: pointer. self ssPushNativeRegister: pointer. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMemcpy32 (in category 'inline primitive generators generated code') ----- genLowcodeMemcpy32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | source size dest | + self allocateRegistersForLowcodeInteger3: [:sizeValue :sourceValue :destValue | + size := sizeValue. + source := sourceValue. + dest := destValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | source dest size | - (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (size := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (source := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (source := Arg1Reg)]. - - (dest := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: size)) bitOr: (self registerMaskFor: source))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (dest := SendNumArgsReg)]. - ((size = ReceiverResultReg or: [source = ReceiverResultReg]) or: [dest = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: size. self ssNativePop: 1. self ssNativeTop nativePopToReg: source. self ssNativePop: 1. self ssNativeTop nativePopToReg: dest. self ssNativePop: 1. self ssFlushAll. backEnd genMemCopy: source to: dest size: size. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMemcpy64 (in category 'inline primitive generators generated code') ----- genLowcodeMemcpy64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | source sizeLow sizeHigh dest size | + self allocateRegistersForLowcodeInteger3: [:sizeValue :sourceValue :destValue | + size := sizeValue. + source := sourceValue. + dest := destValue. + ]. - (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (size := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (source := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (source := Arg1Reg)]. - - (dest := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: size)) bitOr: (self registerMaskFor: source))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (dest := SendNumArgsReg)]. - ((size = ReceiverResultReg or: [source = ReceiverResultReg]) or: [dest = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: size. self ssNativePop: 1. self ssNativeTop nativePopToReg: source. self ssNativePop: 1. self ssNativeTop nativePopToReg: dest. self ssNativePop: 1. self ssFlushAll. backEnd genMemCopy: source to: dest size: sizeLow. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMemcpyFixed (in category 'inline primitive generators generated code') ----- genLowcodeMemcpyFixed + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | source size dest | size := extA. + self allocateRegistersForLowcodeInteger2: [:sourceValue :destValue | + source := sourceValue. + dest := destValue. + ]. - (source := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (source := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (dest := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: source))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (dest := Arg1Reg)]. - (source = ReceiverResultReg or: [dest = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: source. self ssNativePop: 1. self ssNativeTop nativePopToReg: dest. self ssNativePop: 1. size = BytesPerWord ifTrue: [ self MoveMw: 0 r: source R: TempReg. self MoveR: TempReg Mw: 0 r: dest. ] ifFalse: [ self ssFlushAll. backEnd genMemCopy: source to: dest constantSize: size. ]. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMoveFloat32ToPhysical (in category 'inline primitive generators generated code') ----- genLowcodeMoveFloat32ToPhysical + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: extA. self ssNativePop: 1. currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMoveFloat64ToPhysical (in category 'inline primitive generators generated code') ----- genLowcodeMoveFloat64ToPhysical + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: extA. self ssNativePop: 1. currentCallCleanUpSize := currentCallCleanUpSize + 8. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMoveInt32ToPhysical (in category 'inline primitive generators generated code') ----- genLowcodeMoveInt32ToPhysical + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: extA. self ssNativePop: 1. currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMoveInt64ToPhysical (in category 'inline primitive generators generated code') ----- genLowcodeMoveInt64ToPhysical + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: extA. self ssNativePop: 1. currentCallCleanUpSize := currentCallCleanUpSize + 8. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMovePointerToPhysical (in category 'inline primitive generators generated code') ----- genLowcodeMovePointerToPhysical + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: extA. self ssNativePop: 1. currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMul32 (in category 'inline primitive generators generated code') ----- genLowcodeMul32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self MulR: second R: first. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeMul64 (in category 'inline primitive generators generated code') ----- genLowcodeMul64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue | + second := secondValue. + first := firstValue. + result := resultValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeNeg32 (in category 'inline primitive generators generated code') ----- genLowcodeNeg32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self NegateR: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeNeg64 (in category 'inline primitive generators generated code') ----- genLowcodeNeg64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. "Two complement negation" self NotR: valueLow. self NotR: valueHigh. self AddCq: 1 R: valueLow. self AddcCq: 0 R: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self NegateR: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeNot32 (in category 'inline primitive generators generated code') ----- genLowcodeNot32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self NotR: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeNot64 (in category 'inline primitive generators generated code') ----- genLowcodeNot64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self NotR: valueLow. self NotR: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self NotR: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopEqual (in category 'inline primitive generators generated code') ----- genLowcodeOopEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value contJump falseJump first second | + self allocateRegistersForLowcodeOop2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: second. self ssPop: 1. self ssTop popToReg: first. self ssPop: 1. self CmpR: second R: first. falseJump := self JumpNonZero: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopNotEqual (in category 'inline primitive generators generated code') ----- genLowcodeOopNotEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeOop2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: second. self ssPop: 1. self ssTop popToReg: first. self ssPop: 1. self CmpR: second R: first. falseJump := self JumpZero: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopSmallIntegerToInt32 (in category 'inline primitive generators generated code') ----- genLowcodeOopSmallIntegerToInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object | + self allocateRegistersForLowcodeOop: [:objectValue | + object := objectValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genConvertSmallIntegerToIntegerInReg: object. self ssPushNativeRegister: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopSmallIntegerToInt64 (in category 'inline primitive generators generated code') ----- genLowcodeOopSmallIntegerToInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh object value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeOopResultInteger2: [:objectValue :valueLowValue :valueHighValue | + object := objectValue. + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueLow := Arg1Reg)]. - - (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)]. - ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genConvertSmallIntegerToIntegerInReg: object. self MoveCq: 0 R: valueHigh. self ssPushNativeRegister: object secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genConvertSmallIntegerToIntegerInReg: object. self ssPushNativeRegister: object. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToBoolean32 (in category 'inline primitive generators generated code') ----- genLowcodeOopToBoolean32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object | + self allocateRegistersForLowcodeOop: [:objectValue | + object := objectValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self annotate: (self SubCw: objectMemory falseObject R: object) objRef: objectMemory falseObject. self ssPushNativeRegister: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToBoolean64 (in category 'inline primitive generators generated code') ----- genLowcodeOopToBoolean64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh object value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeOopResultInteger2: [:objectValue :valueLowValue :valueHighValue | + object := objectValue. + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueLow := Arg1Reg)]. - - (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)]. - ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self MoveCq: 0 R: valueHigh. self annotate: (self SubCw: objectMemory falseObject R: object) objRef: objectMemory falseObject. self ssPushNativeRegister: object secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self annotate: (self SubCw: objectMemory falseObject R: object) objRef: objectMemory falseObject. self ssPushNativeRegister: object. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeOopToFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultFloat: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self ssFlushAll. objectRepresentation genLcOop: object toFloat32: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeOopToFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultFloat: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self ssFlushAll. objectRepresentation genLcOop: object toFloat64: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToInt32 (in category 'inline primitive generators generated code') ----- genLowcodeOopToInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object | + self allocateRegistersForLowcodeOop: [:objectValue | + object := objectValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self ssFlushAll. objectRepresentation genLcOopToInt32: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToInt64 (in category 'inline primitive generators generated code') ----- genLowcodeOopToInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh object value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeOopResultInteger2: [:objectValue :valueLowValue :valueHighValue | + object := objectValue. + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueLow := Arg1Reg)]. - - (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)]. - ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self ssFlushAll. objectRepresentation genLcOop: object toInt64: valueLow highPart: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self ssFlushAll. objectRepresentation genLcOopToInt64: object. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToPointer (in category 'inline primitive generators generated code') ----- genLowcodeOopToPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object | + self allocateRegistersForLowcodeOop: [:objectValue | + object := objectValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcOopToPointer: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToPointerReinterpret (in category 'inline primitive generators generated code') ----- genLowcodeOopToPointerReinterpret + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object pointer | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :pointerValue | + object := objectValue. + pointer := pointerValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (pointer := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (pointer := Arg1Reg)]. - (object = ReceiverResultReg or: [pointer = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. "TODO: Generate a nop here" self ssPushNativeRegister: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToUInt32 (in category 'inline primitive generators generated code') ----- genLowcodeOopToUInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object value | + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self ssFlushAll. objectRepresentation genLcOopToUInt32: object. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToUInt64 (in category 'inline primitive generators generated code') ----- genLowcodeOopToUInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh object value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeOopResultInteger2: [:objectValue :valueLowValue :valueHighValue | + object := objectValue. + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueLow := Arg1Reg)]. - - (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)]. - ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self ssFlushAll. objectRepresentation genLcOop: object toUInt64: valueLow highPart: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue | + object := objectValue. + value := valueValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self ssFlushAll. objectRepresentation genLcOopToUInt64: object. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOr32 (in category 'inline primitive generators generated code') ----- genLowcodeOr32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second result first | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue | + second := secondValue. + first := firstValue. + result := resultValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self OrR: second R: first. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeOr64 (in category 'inline primitive generators generated code') ----- genLowcodeOr64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh first second firstLow | - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh first second firstHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue | + secondLow := secondLowValue. + secondHigh := secondHighValue. + firstLow := firstLowValue. + firstHigh := firstHighValue. + ]. - (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (secondLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)]. - - (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)]. - - (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstHigh := ClassReg)]. - (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh. self ssNativePop: 1. self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh. self ssNativePop: 1. self OrR: secondLow R: firstLow. self OrR: secondHigh R: firstHigh. self ssPushNativeRegister: firstLow secondRegister: firstHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self OrR: second R: first. self ssPushNativeRegister: first. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallout (in category 'inline primitive generators generated code') ----- genLowcodePerformCallout + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self callSwitchToCStack. self MoveCw: extA R: TempReg. self CallRT: ceFFICalloutTrampoline. self annotateBytecode: self Label. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCalloutIndirect (in category 'inline primitive generators generated code') ----- genLowcodePerformCalloutIndirect + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssNativeTop nativeStackPopToReg: TempReg. self ssNativePop: 1. self callSwitchToCStack. self CallRT: ceFFICalloutTrampoline. self annotateBytecode: self Label. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePin (in category 'inline primitive generators generated code') ----- genLowcodePin + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object | + self allocateRegistersForLowcodeOop: [:objectValue | + object := objectValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePlaftormCode (in category 'inline primitive generators generated code') ----- genLowcodePlaftormCode + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePointerAddConstantOffset (in category 'inline primitive generators generated code') ----- genLowcodePointerAddConstantOffset + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | base offset | offset := extB. + self allocateRegistersForLowcodeInteger: [:baseValue | + base := baseValue. + ]. - (base := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (base := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - base = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: base. self ssNativePop: 1. self AddCq: offset R: base. self ssPushNativeRegister: base. extB := 0. numExtB := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePointerAddOffset32 (in category 'inline primitive generators generated code') ----- genLowcodePointerAddOffset32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | base offset | + self allocateRegistersForLowcodeInteger2: [:offsetValue :baseValue | + offset := offsetValue. + base := baseValue. + ]. - (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (offset := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (base := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (base := Arg1Reg)]. - (offset = ReceiverResultReg or: [base = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: offset. self ssNativePop: 1. self ssNativeTop nativePopToReg: base. self ssNativePop: 1. self AddR: offset R: base. self ssPushNativeRegister: base. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePointerAddOffset64 (in category 'inline primitive generators generated code') ----- genLowcodePointerAddOffset64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | offsetHigh base offset offsetLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger3: [:offsetLowValue :offsetHighValue :baseValue | + offsetLow := offsetLowValue. + offsetHigh := offsetHighValue. + base := baseValue. + ]. - (offsetLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (offsetLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (offsetHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offsetLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (offsetHigh := Arg1Reg)]. - - (base := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: offsetLow)) bitOr: (self registerMaskFor: offsetHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (base := SendNumArgsReg)]. - ((offsetLow = ReceiverResultReg or: [offsetHigh = ReceiverResultReg]) or: [base = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: offsetLow secondReg: offsetHigh. self ssNativePop: 1. self ssNativeTop nativePopToReg: base. self ssNativePop: 1. self AddR: offsetLow R: base. self ssPushNativeRegister: base. ] ifFalse: [ + self allocateRegistersForLowcodeInteger2: [:offsetValue :baseValue | + offset := offsetValue. + base := baseValue. + ]. - (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (offset := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (base := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (base := Arg1Reg)]. - (offset = ReceiverResultReg or: [base = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: offset. self ssNativePop: 1. self ssNativeTop nativePopToReg: base. self ssNativePop: 1. self AddR: offset R: base. self ssPushNativeRegister: base. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePointerEqual (in category 'inline primitive generators generated code') ----- genLowcodePointerEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpNonZero: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePointerNotEqual (in category 'inline primitive generators generated code') ----- genLowcodePointerNotEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpZero: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePointerToInt32 (in category 'inline primitive generators generated code') ----- genLowcodePointerToInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer | + self allocateRegistersForLowcodeInteger: [:pointerValue | + pointer := pointerValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. "TODO: Perform a NOP here" self ssPushNativeRegister: pointer. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePointerToInt64 (in category 'inline primitive generators generated code') ----- genLowcodePointerToInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | resultLow pointer result resultHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeIntegerResultInteger2: [:pointerValue :resultLowValue :resultHighValue | + pointer := pointerValue. + resultLow := resultLowValue. + resultHigh := resultHighValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (resultLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (resultLow := Arg1Reg)]. - - (resultHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (resultHigh := SendNumArgsReg)]. - ((pointer = ReceiverResultReg or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self MoveR: pointer R: resultLow. self MoveCq: 0 R: resultHigh. self ssPushNativeRegister: resultLow secondRegister: resultHigh. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :resultValue | + pointer := pointerValue. + result := resultValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := Arg1Reg)]. - (pointer = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssPushNativeRegister: pointer. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePointerToOop (in category 'inline primitive generators generated code') ----- genLowcodePointerToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer pointerClassLiteral | pointerClassLiteral := self getLiteral: extA. + self allocateRegistersForLowcodeInteger: [:pointerValue | + pointer := pointerValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssFlushAll. objectRepresentation genLcPointerToOop: pointer class: pointerClassLiteral. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePointerToOopReinterprer (in category 'inline primitive generators generated code') ----- genLowcodePointerToOopReinterprer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer | + self allocateRegistersForLowcodeInteger: [:pointerValue | + pointer := pointerValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. "TODO: Generate a nop here" self ssPushRegister: pointer. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePopFloat32 (in category 'inline primitive generators generated code') ----- genLowcodePopFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeFloat: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePopFloat64 (in category 'inline primitive generators generated code') ----- genLowcodePopFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeFloat: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePopInt32 (in category 'inline primitive generators generated code') ----- genLowcodePopInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePopInt64 (in category 'inline primitive generators generated code') ----- genLowcodePopInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePopMultipleNative (in category 'inline primitive generators generated code') ----- genLowcodePopMultipleNative + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPopNativeSize: extA. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePopPointer (in category 'inline primitive generators generated code') ----- genLowcodePopPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointerValue | + self allocateRegistersForLowcodeInteger: [:pointerValueValue | + pointerValue := pointerValueValue. + ]. - (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointerValue := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointerValue = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointerValue. self ssNativePop: 1. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultFloat32 (in category 'inline primitive generators generated code') ----- genLowcodePushCalloutResultFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" backEnd cFloatResultToRs: DPFPReg0. self ssPushNativeRegisterSingleFloat: DPFPReg0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultFloat64 (in category 'inline primitive generators generated code') ----- genLowcodePushCalloutResultFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" backEnd cFloatResultToRd: DPFPReg0. self ssPushNativeRegisterDoubleFloat: DPFPReg0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultInt32 (in category 'inline primitive generators generated code') ----- genLowcodePushCalloutResultInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self MoveR: backEnd cResultRegister R: ReceiverResultReg. self ssPushNativeRegister: ReceiverResultReg. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultInt64 (in category 'inline primitive generators generated code') ----- genLowcodePushCalloutResultInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" BytesPerWord = 4 ifTrue: [ self MoveR: backEnd cResultRegisterLow R: ReceiverResultReg. self MoveR: backEnd cResultRegisterHigh R: Arg0Reg. self ssPushNativeRegister: ReceiverResultReg secondRegister: Arg0Reg. ] ifFalse: [ self MoveR: backEnd cResultRegister R: ReceiverResultReg. self ssPushNativeRegister: ReceiverResultReg. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultPointer (in category 'inline primitive generators generated code') ----- genLowcodePushCalloutResultPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self MoveR: backEnd cResultRegister R: ReceiverResultReg. self ssPushNativeRegister: ReceiverResultReg. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushConstantUInt32 (in category 'inline primitive generators generated code') ----- genLowcodePushConstantUInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | constant | constant := extA. self ssPushNativeConstantInt32: constant. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushConstantUInt64 (in category 'inline primitive generators generated code') ----- genLowcodePushConstantUInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | constant | constant := extA. self ssPushNativeConstantInt64: constant. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushNullPointer (in category 'inline primitive generators generated code') ----- genLowcodePushNullPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantPointer: 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushOne32 (in category 'inline primitive generators generated code') ----- genLowcodePushOne32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantInt32: 1. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushOne64 (in category 'inline primitive generators generated code') ----- genLowcodePushOne64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantInt64: 1. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushOneFloat32 (in category 'inline primitive generators generated code') ----- genLowcodePushOneFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantFloat32: 1.0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushOneFloat64 (in category 'inline primitive generators generated code') ----- genLowcodePushOneFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantFloat64: 1.0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalFloat32 (in category 'inline primitive generators generated code') ----- genLowcodePushPhysicalFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | registerID | registerID := extA. self abort. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalFloat64 (in category 'inline primitive generators generated code') ----- genLowcodePushPhysicalFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | registerID | registerID := extA. self abort. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalInt32 (in category 'inline primitive generators generated code') ----- genLowcodePushPhysicalInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | registerID | registerID := extA. self abort. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalInt64 (in category 'inline primitive generators generated code') ----- genLowcodePushPhysicalInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | registerID | registerID := extA. self abort. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalPointer (in category 'inline primitive generators generated code') ----- genLowcodePushPhysicalPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | registerID | registerID := extA. self abort. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushSessionIdentifier (in category 'inline primitive generators generated code') ----- genLowcodePushSessionIdentifier + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantInt32: coInterpreter getThisSessionID. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushZero32 (in category 'inline primitive generators generated code') ----- genLowcodePushZero32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantInt32: 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushZero64 (in category 'inline primitive generators generated code') ----- genLowcodePushZero64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantInt64: 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushZeroFloat32 (in category 'inline primitive generators generated code') ----- genLowcodePushZeroFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantFloat32: 0.0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodePushZeroFloat64 (in category 'inline primitive generators generated code') ----- genLowcodePushZeroFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self ssPushNativeConstantFloat64: 0.0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeRem32 (in category 'inline primitive generators generated code') ----- genLowcodeRem32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self DivR: second R: first Quo: second Rem: first. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeRem64 (in category 'inline primitive generators generated code') ----- genLowcodeRem64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue | + second := secondValue. + first := firstValue. + result := resultValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeRightShift32 (in category 'inline primitive generators generated code') ----- genLowcodeRightShift32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value shiftAmount | + self allocateRegistersForLowcodeInteger2: [:shiftAmountValue :valueValue | + shiftAmount := shiftAmountValue. + value := valueValue. + ]. - (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (shiftAmount := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: shiftAmount. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self LogicalShiftRightR: shiftAmount R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeRightShift64 (in category 'inline primitive generators generated code') ----- genLowcodeRightShift64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | value result shiftAmountHigh shiftAmount resultLow valueLow resultHigh shiftAmountLow valueHigh | + self allocateRegistersForLowcodeInteger2ResultInteger: [:shiftAmountValue :valueValue :resultValue | + shiftAmount := shiftAmountValue. + value := valueValue. + result := resultValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | value result shiftAmount shiftAmountHigh resultLow valueLow resultHigh shiftAmountLow valueHigh | - (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (shiftAmount := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: shiftAmount)) bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: shiftAmount. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend32From16 (in category 'inline primitive generators generated code') ----- genLowcodeSignExtend32From16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self SignExtend16R: value R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend32From8 (in category 'inline primitive generators generated code') ----- genLowcodeSignExtend32From8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self SignExtend8R: value R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend64From16 (in category 'inline primitive generators generated code') ----- genLowcodeSignExtend64From16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value isNegative cont valueLow valueHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self SignExtend16R: valueLow R: valueLow. "Check the sign to set the high word" self CmpCq: 0 R: valueLow. "Positive" isNegative := self JumpLess: 0. self MoveCq: 0 R: valueHigh. cont := self Jump: 0. "Negative" isNegative jmpTarget: (self MoveCq: -1 R: valueHigh). cont jmpTarget: self Label. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self SignExtend16R: value R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend64From32 (in category 'inline primitive generators generated code') ----- genLowcodeSignExtend64From32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result resultLow resultHigh isNegative cont | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeIntegerResultInteger2: [:valueValue :resultLowValue :resultHighValue | + value := valueValue. + resultLow := resultLowValue. + resultHigh := resultHighValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (resultLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (resultLow := Arg1Reg)]. - - (resultHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: value)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (resultHigh := SendNumArgsReg)]. - ((value = ReceiverResultReg or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value R: resultLow. "Check the sign to set the high word" self CmpCq: 0 R: value. "Positive" isNegative := self JumpLess: 0. self MoveCq: 0 R: resultHigh. cont := self Jump: 0. "Negative" isNegative jmpTarget: (self MoveCq: -1 R: resultHigh). cont jmpTarget: self Label. self ssPushNativeRegister: resultLow secondRegister: resultHigh. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := Arg1Reg)]. - (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self SignExtend32R: value R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend64From8 (in category 'inline primitive generators generated code') ----- genLowcodeSignExtend64From8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result resultLow resultHigh isNegative valueLow cont valueHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2ResultInteger2: [:valueLowValue :valueHighValue :resultLowValue :resultHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + resultLow := resultLowValue. + resultHigh := resultHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - - (resultLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (resultLow := SendNumArgsReg)]. - - (resultHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (resultHigh := ClassReg)]. - (((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self SignExtend8R: valueLow R: valueLow. "Check the sign to set the high word" self CmpCq: 0 R: valueLow. "Positive" isNegative := self JumpLess: 0. self MoveCq: 0 R: valueHigh. cont := self Jump: 0. "Negative" isNegative jmpTarget: (self MoveCq: -1 R: valueHigh). cont jmpTarget: self Label. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := Arg1Reg)]. - (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ZeroExtend16R: value R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeSmallInt32ToOop (in category 'inline primitive generators generated code') ----- genLowcodeSmallInt32ToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. objectRepresentation genConvertIntegerToSmallIntegerInReg: value. self ssPushRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreFloat32ToMemory (in category 'inline primitive generators generated code') ----- genLowcodeStoreFloat32ToMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | floatValue pointer | + self allocateRegistersForLowcodeFloatInteger: [:floatValueValue :pointerValue | + floatValue := floatValueValue. + pointer := pointerValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssNativeTop nativePopToReg: floatValue. self ssNativePop: 1. self MoveRs: floatValue M32: 0 r: pointer. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreFloat64ToMemory (in category 'inline primitive generators generated code') ----- genLowcodeStoreFloat64ToMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | doubleValue pointer | + self allocateRegistersForLowcodeFloatInteger: [:doubleValueValue :pointerValue | + doubleValue := doubleValueValue. + pointer := pointerValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (doubleValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (doubleValue := DPFPReg0)]. - pointer = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssNativeTop nativePopToReg: doubleValue. self ssNativePop: 1. self MoveRd: doubleValue M64: 0 r: pointer. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt16ToMemory (in category 'inline primitive generators generated code') ----- genLowcodeStoreInt16ToMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeInteger2: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value R: TempReg. self MoveR: TempReg M16: 0 r: pointer. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt32ToMemory (in category 'inline primitive generators generated code') ----- genLowcodeStoreInt32ToMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeInteger2: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value M32: 0 r: pointer. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt64ToMemory (in category 'inline primitive generators generated code') ----- genLowcodeStoreInt64ToMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh pointer value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger3: [:pointerValue :valueLowValue :valueHighValue | + pointer := pointerValue. + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueLow := Arg1Reg)]. - - (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)]. - ((pointer = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self MoveR: valueLow M32: 0 r: pointer. self MoveR: valueHigh M32: 4 r: pointer. ] ifFalse: [ + self allocateRegistersForLowcodeInteger2: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value M64: 0 r: pointer. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt8ToMemory (in category 'inline primitive generators generated code') ----- genLowcodeStoreInt8ToMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointer value | + self allocateRegistersForLowcodeInteger2: [:pointerValue :valueValue | + pointer := pointerValue. + value := valueValue. + ]. - (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := Arg1Reg)]. - (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointer. self ssNativePop: 1. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value R: TempReg. self MoveR: TempReg M8: 0 r: pointer. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeStoreLocalFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value baseOffset | baseOffset := extA. + self allocateRegistersForLowcodeFloat: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveRs: value M32: 0 r: TempReg. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeStoreLocalFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value baseOffset | baseOffset := extA. + self allocateRegistersForLowcodeFloat: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (value := DPFPReg0)]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveRd: value M64: 0 r: TempReg. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt16 (in category 'inline primitive generators generated code') ----- genLowcodeStoreLocalInt16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value baseOffset | baseOffset := extA. + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value R: TempReg. self loadNativeLocalAddress: baseOffset to: value. self MoveR: TempReg M16: 0 r: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt32 (in category 'inline primitive generators generated code') ----- genLowcodeStoreLocalInt32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value baseOffset | baseOffset := extA. + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveR: value M32: 0 r: TempReg. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt64 (in category 'inline primitive generators generated code') ----- genLowcodeStoreLocalInt64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow baseOffset | baseOffset := extA. BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveR: valueLow M32: 0 r: TempReg. self MoveR: valueHigh M32: 4 r: TempReg. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value M64: 0 r: TempReg. ]. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt8 (in category 'inline primitive generators generated code') ----- genLowcodeStoreLocalInt8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value baseOffset | baseOffset := extA. + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value R: TempReg. self loadNativeLocalAddress: baseOffset to: value. self MoveR: TempReg M8: 0 r: value. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalPointer (in category 'inline primitive generators generated code') ----- genLowcodeStoreLocalPointer + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | pointerValue baseOffset | baseOffset := extA. + self allocateRegistersForLowcodeInteger: [:pointerValueValue | + pointerValue := pointerValueValue. + ]. - (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (pointerValue := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - pointerValue = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: pointerValue. self ssNativePop: 1. self loadNativeLocalAddress: baseOffset to: TempReg. self MoveR: pointerValue Mw: 0 r: TempReg. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreObjectField (in category 'inline primitive generators generated code') ----- genLowcodeStoreObjectField + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | fieldIndex object value | fieldIndex := extA. + self allocateRegistersForLowcodeOop2: [:valueValue :objectValue | + value := valueValue. + object := objectValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := Arg1Reg)]. - (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: value. self ssPop: 1. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcStore: value object: object field: fieldIndex. extA := 0. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreObjectFieldAt (in category 'inline primitive generators generated code') ----- genLowcodeStoreObjectFieldAt + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | fieldIndex object value | + self allocateRegistersForLowcodeIntegerOop2: [:fieldIndexValue :valueValue :objectValue | + fieldIndex := fieldIndexValue. + value := valueValue. + object := objectValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (fieldIndex := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (fieldIndex := Arg1Reg)]. - - (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: value)) bitOr: (self registerMaskFor: fieldIndex))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := SendNumArgsReg)]. - ((value = ReceiverResultReg or: [fieldIndex = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: value. self ssPop: 1. self ssNativeTop nativePopToReg: fieldIndex. self ssNativePop: 1. self ssTop popToReg: object. self ssPop: 1. objectRepresentation genLcStore: value object: object at: fieldIndex. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeStorePointerToMemory (in category 'inline primitive generators generated code') ----- genLowcodeStorePointerToMemory + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | memoryPointer pointerValue | + self allocateRegistersForLowcodeInteger2: [:memoryPointerValue :pointerValueValue | + memoryPointer := memoryPointerValue. + pointerValue := pointerValueValue. + ]. - (memoryPointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (memoryPointer := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (pointerValue := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: memoryPointer))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (pointerValue := Arg1Reg)]. - (memoryPointer = ReceiverResultReg or: [pointerValue = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: memoryPointer. self ssNativePop: 1. self ssNativeTop nativePopToReg: pointerValue. self ssNativePop: 1. self MoveR: pointerValue Mw: 0 r: memoryPointer. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeSub32 (in category 'inline primitive generators generated code') ----- genLowcodeSub32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self SubR: second R: first. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeSub64 (in category 'inline primitive generators generated code') ----- genLowcodeSub64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh first second firstLow | - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh first second firstHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue | + secondLow := secondLowValue. + secondHigh := secondHighValue. + firstLow := firstLowValue. + firstHigh := firstHighValue. + ]. - (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (secondLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)]. - - (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)]. - - (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstHigh := ClassReg)]. - (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh. self ssNativePop: 1. self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh. self ssNativePop: 1. self SubR: secondLow R: firstLow. self SubbR: secondHigh R: firstHigh. self ssPushNativeRegister: firstLow secondRegister: firstHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self SubR: second R: first. self ssPushNativeRegister: first. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate32To16 (in category 'inline primitive generators generated code') ----- genLowcodeTruncate32To16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self AndCq: 16rFFFF R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate32To8 (in category 'inline primitive generators generated code') ----- genLowcodeTruncate32To8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self AndCq: 16rFF R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate64To16 (in category 'inline primitive generators generated code') ----- genLowcodeTruncate64To16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self AndCq: 16rFFFF R: valueLow. self ssPushNativeRegister: valueLow. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self AndCq: 16rFFFF R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate64To32 (in category 'inline primitive generators generated code') ----- genLowcodeTruncate64To32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self ssPushNativeRegister: valueLow. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self AndCq: 16rFFFFFFFF R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate64To8 (in category 'inline primitive generators generated code') ----- genLowcodeTruncate64To8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow result | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2ResultInteger: [:valueLowValue :valueHighValue :resultValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + result := resultValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self AndCq: 16rFF R: valueLow. self ssPushNativeRegister: valueLow. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := Arg1Reg)]. - (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self AndCq: 16rFF R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUdiv32 (in category 'inline primitive generators generated code') ----- genLowcodeUdiv32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self DivR: second R: first Quo: first Rem: second. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUdiv64 (in category 'inline primitive generators generated code') ----- genLowcodeUdiv64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue | + second := secondValue. + first := firstValue. + result := resultValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32Great (in category 'inline primitive generators generated code') ----- genLowcodeUint32Great + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpBelowOrEqual: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32GreatEqual (in category 'inline primitive generators generated code') ----- genLowcodeUint32GreatEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpBelow: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32Less (in category 'inline primitive generators generated code') ----- genLowcodeUint32Less + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpAboveOrEqual: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32LessEqual (in category 'inline primitive generators generated code') ----- genLowcodeUint32LessEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second falseJump contJump first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self CmpR: second R: first. falseJump := self JumpAbove: 0. "True result" self MoveCq: 1 R: first. contJump := self Jump: 0. "False result" falseJump jmpTarget: self Label. self MoveCq: 0 R: first. contJump jmpTarget: self Label. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32ToFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeUint32ToFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result | + self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg0)]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ConvertR: value Rs: result. self ssPushNativeRegisterSingleFloat: result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32ToFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeUint32ToFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value result | + self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg0)]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ConvertR: value Rd: result. self ssPushNativeRegisterDoubleFloat: result. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32ToOop (in category 'inline primitive generators generated code') ----- genLowcodeUint32ToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ssFlushAll. objectRepresentation genLcUInt32ToOop: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64Great (in category 'inline primitive generators generated code') ----- genLowcodeUint64Great + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh value first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh value first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64GreatEqual (in category 'inline primitive generators generated code') ----- genLowcodeUint64GreatEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh value first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh value first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64Less (in category 'inline primitive generators generated code') ----- genLowcodeUint64Less + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh value first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh value first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64LessEqual (in category 'inline primitive generators generated code') ----- genLowcodeUint64LessEqual + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh value first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue | + second := secondValue. + first := firstValue. + value := valueValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh value first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (value := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64ToFloat32 (in category 'inline primitive generators generated code') ----- genLowcodeUint64ToFloat32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow result | + self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg0)]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64ToFloat64 (in category 'inline primitive generators generated code') ----- genLowcodeUint64ToFloat64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow result | + self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue: - [self ssAllocateRequiredFloatReg: (result := DPFPReg0)]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64ToOop (in category 'inline primitive generators generated code') ----- genLowcodeUint64ToOop + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh object value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2ResultOop: [:valueLowValue :valueHighValue :objectValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + object := objectValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - - (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := SendNumArgsReg)]. - ((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self ssFlushAll. objectRepresentation genLcUInt64ToOop: valueLow highPart: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultOop: [:valueValue :objectValue | + value := valueValue. + object := objectValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (object := Arg1Reg)]. - (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ssFlushAll. objectRepresentation genLcUInt64ToOop: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUmul32 (in category 'inline primitive generators generated code') ----- genLowcodeUmul32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self MulR: second R: first. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUmul64 (in category 'inline primitive generators generated code') ----- genLowcodeUmul64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue | + second := secondValue. + first := firstValue. + result := resultValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUnlockRegisters (in category 'inline primitive generators generated code') ----- genLowcodeUnlockRegisters + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" "Do nothing for now" ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUnlockVM (in category 'inline primitive generators generated code') ----- genLowcodeUnlockVM + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUnpin (in category 'inline primitive generators generated code') ----- genLowcodeUnpin + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | object | + self allocateRegistersForLowcodeOop: [:objectValue | + object := objectValue. + ]. - (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (object := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - object = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssTop popToReg: object. self ssPop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUrem32 (in category 'inline primitive generators generated code') ----- genLowcodeUrem32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self DivR: second R: first Quo: second Rem: first. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeUrem64 (in category 'inline primitive generators generated code') ----- genLowcodeUrem64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow | + self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue | + second := secondValue. + first := firstValue. + result := resultValue. + ]. - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh | - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - - (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := SendNumArgsReg)]. - ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self abort. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeXor32 (in category 'inline primitive generators generated code') ----- genLowcodeXor32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | second first | + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self XorR: second R: first. self ssPushNativeRegister: first. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeXor64 (in category 'inline primitive generators generated code') ----- genLowcodeXor64 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." + | secondLow secondHigh firstHigh first second firstLow | - <option: #LowcodeVM> "Lowcode instruction generator" - | secondLow firstLow secondHigh first second firstHigh | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue | + secondLow := secondLowValue. + secondHigh := secondHighValue. + firstLow := firstLowValue. + firstHigh := firstHighValue. + ]. - (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (secondLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)]. - - (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)]. - - (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (firstHigh := ClassReg)]. - (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh. self ssNativePop: 1. self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh. self ssNativePop: 1. self XorR: secondLow R: firstLow. self XorR: secondHigh R: firstHigh. self ssPushNativeRegister: firstLow secondRegister: firstHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue | + second := secondValue. + first := firstValue. + ]. - (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (second := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (first := Arg1Reg)]. - (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: second. self ssNativePop: 1. self ssNativeTop nativePopToReg: first. self ssNativePop: 1. self XorR: second R: first. self ssPushNativeRegister: first. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend32From16 (in category 'inline primitive generators generated code') ----- genLowcodeZeroExtend32From16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ZeroExtend16R: value R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend32From8 (in category 'inline primitive generators generated code') ----- genLowcodeZeroExtend32From8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | value | + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ZeroExtend8R: value R: value. self ssPushNativeRegister: value. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend64From16 (in category 'inline primitive generators generated code') ----- genLowcodeZeroExtend64From16 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self ZeroExtend16R: valueLow R: valueLow. self MoveCq: 0 R: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ZeroExtend16R: value R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend64From32 (in category 'inline primitive generators generated code') ----- genLowcodeZeroExtend64From32 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | resultLow resultHigh value result | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeIntegerResultInteger2: [:valueValue :resultLowValue :resultHighValue | + value := valueValue. + resultLow := resultLowValue. + resultHigh := resultHighValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (resultLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (resultLow := Arg1Reg)]. - - (resultHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: value)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (resultHigh := SendNumArgsReg)]. - ((value = ReceiverResultReg or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self MoveR: value R: resultLow. self MoveCq: 0 R: resultHigh. self ssPushNativeRegister: resultLow secondRegister: resultHigh. ] ifFalse: [ + self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :resultValue | + value := valueValue. + result := resultValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (result := Arg1Reg)]. - (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ZeroExtend32R: value R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend64From8 (in category 'inline primitive generators generated code') ----- genLowcodeZeroExtend64From8 + <option: #LowcodeVM> + <inline: true> + "Generated by the Lowcode instruction generator." - <option: #LowcodeVM> "Lowcode instruction generator" | valueHigh value valueLow | BytesPerWord = 4 ifTrue: [ + self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue | + valueLow := valueLowValue. + valueHigh := valueHighValue. + ]. - (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (valueLow := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - - (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue: - [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)]. - (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh. self ssNativePop: 1. self ZeroExtend8R: valueLow R: valueLow. self MoveCq: 0 R: valueHigh. self ssPushNativeRegister: valueLow secondRegister: valueHigh. ] ifFalse: [ + self allocateRegistersForLowcodeInteger: [:valueValue | + value := valueValue. + ]. - (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue: - [self ssAllocateRequiredReg: - (value := optStatus isReceiverResultRegLive - ifTrue: [Arg0Reg] - ifFalse: [ReceiverResultReg])]. - value = ReceiverResultReg ifTrue: - [ optStatus isReceiverResultRegLive: false ]. self ssNativeTop nativePopToReg: value. self ssNativePop: 1. self ZeroExtend8R: value R: value. self ssPushNativeRegister: value. ]. ^ 0 ! Item was added: + ----- Method: StackToRegisterMappingCogit>>ssNativeValue: (in category 'simulation stack') ----- + ssNativeValue: n + <returnTypeC: #'CogSimStackNativeEntry *'> + <option: #LowcodeVM> + ^self simNativeStackAt: simStackPtr - n!

1 0

how to fix appveyor red status?
by Nicolas Cellier 05 Mar '17

05 Mar '17

Hi all, anybody has an idea of what happens in the appveyor builds? The 64bit squeak.stack.spur started to fail with: https://ci.appveyor.com/project/OpenSmalltalk/vm/build/1.0.547/job/28bqcbsl… x86_64-w64-mingw32-clang -o mkNamedPrims.exe -mconsole -m64 ../../platforms/win32/util/mkNamedPrims.c make: *** [../common/Makefile:202: mkNamedPrims.exe] Error 127 Command exited with code 1 Then it did propagate to most of the 32bits builds (but 2) It seems completely unrelated to the committed changes, and I can't reproduce in any of my virtual windows machines. Is it a change in cygwin, or anything else in the appveyor infrastucture? How can we debug that? Nicolas

3 6

[OpenSmalltalk/opensmalltalk-vm] bfe306: Upgrade installed Cygwin packages
by GitHub 05 Mar '17

05 Mar '17

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: bfe3069a8710844ecd77113aca87580bb7ff4ab7 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/bfe3069a8710844ecd… Author: Fabio Niephaus <code(a)fniephaus.com> Date: 2017-03-05 (Sun, 05 Mar 2017) Changed paths: M .appveyor.yml Log Message: ----------- Upgrade installed Cygwin packages

1 0

[OpenSmalltalk/opensmalltalk-vm] c5bff1: Make OS X CameraPlugin assume 1-based cameraNum pa...
by GitHub 04 Mar '17

04 Mar '17

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: c5bff158671a5d0dcda9038fdb74298b553aff52 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/c5bff158671a5d0dcd… Author: Nicolas Cellier <nicolas.cellier.aka.nice(a)gmail.com> Date: 2017-03-04 (Sat, 04 Mar 2017) Changed paths: M platforms/iOS/plugins/CameraPlugin/AVFoundationVideoGrabber.m Log Message: ----------- Make OS X CameraPlugin assume 1-based cameraNum parameters Correctly use cameraNum-1 where 0-based is expected. Correctly initialize deviceID in initialization. Protect grabbers table from buffer overflow.

1 0

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Vm-dev March 2017