Vm-dev June 2015

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28 participants
149 discussions

VM Maker: Cog-eem.270.mcz
by commits＠source.squeak.org 29 Jun '15

29 Jun '15

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.270.mcz ==================== Summary ==================== Name: Cog-eem.270 Author: eem Time: 29 June 2015, 2:06:40.897 pm UUID: e76f505e-4e2e-4323-af4e-9bc0938a7783 Ancestors: Cog-eem.269 Fix the Cog bootatrap given the access control changes in VMMaker.oscog-rmacnak.1392 =============== Diff against Cog-eem.269 =============== Item was changed: ----- Method: SpurBootstrap>>rehashImage (in category 'bootstrap image') ----- rehashImage "Rehash all collections in newHeap. Find out which classes implement rehash, entering a 1 against their classIndex in rehashFlags. Enumerate all objects, rehashing those whose class has a bit set in rehashFlags." | n sim rehashFlags dotDate rehashSym sizeSym | rehashSym := map at: (self findSymbol: #rehash). sizeSym := map at: (self findSymbol: #size). sim := StackInterpreterSimulator onObjectMemory: newHeap options: #(ObjectMemory #Spur32BitMemoryManager). sim setImageHeaderFlagsFrom: oldInterpreter getImageHeaderFlags; imageName: 'spur image'; assertValidExecutionPointersAtEachStep: false.. newHeap coInterpreter: sim. sim bootstrapping: true. sim initializeInterpreter: 0. sim instVarNamed: 'methodDictLinearSearchLimit' put: SmallInteger maxVal. sim redirectTranscriptToHost. newHeap setHashBitsOf: newHeap nilObject to: 1; setHashBitsOf: newHeap falseObject to: 2; setHashBitsOf: newHeap trueObject to: 3. rehashFlags := ByteArray new: newHeap numClassTablePages * newHeap classTablePageSize. n := 0. newHeap classTableObjectsDo: [:class| | classIndex | sim messageSelector: rehashSym. "Lookup rehash but don't be fooled by ProtoObject>>rehash, which is just ^self." + ((sim lookupOrdinaryNoMNUEtcInClass: class) = 0 - ((sim lookupMethodNoMNUEtcInClass: class) = 0 and: [(sim isQuickPrimitiveIndex: (sim primitiveIndexOf: (sim instVarNamed: 'newMethod'))) not]) ifTrue: [n := n + 1. classIndex := newHeap rawHashBitsOf: class. rehashFlags at: classIndex >> 3 + 1 put: ((rehashFlags at: classIndex >> 3 + 1) bitOr: (1 << (classIndex bitAnd: 7)))]]. Transcript cr; print: n; nextPutAll: ' classes understand rehash. rehashing instances...'; flush. dotDate := Time now asSeconds. n := 0. self withExecutableInterpreter: sim do: [sim setBreakSelector: 'error:'. "don't rehash twice (actually without limit), so don't rehash any new objects created." newHeap allExistingOldSpaceObjectsDo: [:o| | classIndex | classIndex := newHeap classIndexOf: o. ((rehashFlags at: classIndex >> 3 + 1) anyMask: 1 << (classIndex bitAnd: 7)) ifTrue: [Time now asSeconds > dotDate ifTrue: [Transcript nextPut: $.; flush. dotDate := Time now asSeconds]. "2845 = n ifTrue: [self halt]." "Rehash an object if its size is > 0. Symbol implements rehash, but let's not waste time rehashing it; in Squeak up to 2013 symbols are kept in a set which will get reashed anyway.. Don't rehash empty collections; they may be large for a reason and rehashing will shrink them." ((sim addressCouldBeClassObj: o) or: [(self interpreter: sim object: o perform: sizeSym withArguments: #()) = (newHeap integerObjectOf: 0)]) ifFalse: [self interpreter: sim object: o perform: rehashSym withArguments: #()]]]]!

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[SPUR] ImageSegment>>#restoreEndianess works head-ful but not head-less, why?
by Tobias Pape 29 Jun '15

29 Jun '15

Dear all, the current Squeak Trunk on Spur is crashing with a 'Recursive not understood error encountered' in ImageSegment>restoreEndianness. (See http://build.squeak.org/job/SqueakTrunkOnSpur/608/console) However, running this thing not headless as jenkins but headful, the indicated test does not crash there. The only thing I noticed is that restoreEndianess relies on the total temporal order of objects: object := segment. [object := object nextObject. "all the way to the end of memory to catch remade objects" object == endMarker ifTrue: [inSeg := false]. "off end" " .... " object == 0] whileFalse. I cannot understand where a recursive dNU should appear here or why it should work with X but not without. I am truly puzzled. I know that ImageSegments are a tad tied to the V3 Memory layout, but nevertheless, I think spur shouldn't choke that hard on them… Best regards -Tobias

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VM Maker: VMMaker.oscog-cb.1399.mcz
by commits＠source.squeak.org 29 Jun '15

29 Jun '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1399.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1399 Author: cb Time: 29 June 2015, 2:59:03.143 pm UUID: 288a6e76-6729-4327-9507-23659247129e Ancestors: VMMaker.oscog-cb.1398 Moved down the return because slang doesn't translate correctly returns on conditions resolved at compile time. =============== Diff against VMMaker.oscog-cb.1398 =============== Item was changed: ----- Method: StackToRegisterMappingCogit>>genExtPushClosureBytecode (in category 'bytecode generators') ----- genExtPushClosureBytecode "Block compilation. At this point in the method create the block. Note its start and defer generating code for it until after the method and any other preceeding blocks. The block's actual code will be compiled later." "253 11111101 eei i i kkk jjjjjjjj Push Closure Num Copied iii (+ Ext A // 16 * 8) Num Args kkk (+ Ext A \\ 16 * 8) BlockSize jjjjjjjj (+ Ext B * 256). ee = num extensions" | startpc numArgs numCopied | self assert: needsFrame. startpc := bytecodePC + (self generatorAt: byte0) numBytes. self addBlockStartAt: startpc "0 relative" numArgs: (numArgs := (byte1 bitAnd: 16r7) + (extA \\ 16 * 8)) numCopied: (numCopied := ((byte1 >> 3) bitAnd: 7) + (extA // 16 * 8)) span: byte2 + (extB << 8). extA := extB := 0. + objectRepresentation createsClosuresInline - ^ objectRepresentation createsClosuresInline ifTrue: [ self genInlineClosure: startpc numArgs: numArgs numCopied: numCopied ] + ifFalse: [ self genOutlineClosure: startpc numArgs: numArgs numCopied: numCopied ]. + + ^ 0! - ifFalse: [ self genOutlineClosure: startpc numArgs: numArgs numCopied: numCopied ]! Item was changed: ----- Method: StackToRegisterMappingCogit>>genInlineClosure:numArgs:numCopied: (in category 'bytecode generator support') ----- genInlineClosure: startpc numArgs: numArgs numCopied: numCopied <inline: true> self assert: objectRepresentation getActiveContextAllocatesInMachineCode. optStatus isReceiverResultRegLive: false. self ssAllocateCallReg: ReceiverResultReg and: SendNumArgsReg and: ClassReg. objectRepresentation genNoPopCreateClosureAt: startpc + 1 "1 relative" numArgs: numArgs numCopied: numCopied contextNumArgs: methodOrBlockNumArgs large: (coInterpreter methodNeedsLargeContext: methodObj) inBlock: inBlock. 1 to: numCopied do: [:i| | reg | reg := self ssStorePop: true toPreferredReg: TempReg. objectRepresentation genStoreSourceReg: reg slotIndex: ClosureFirstCopiedValueIndex + numCopied - i intoNewObjectInDestReg: ReceiverResultReg]. + self ssPushRegister: ReceiverResultReg - ^self ssPushRegister: ReceiverResultReg ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genOutlineClosure:numArgs:numCopied: (in category 'bytecode generator support') ----- genOutlineClosure: startpc numArgs: numArgs numCopied: numCopied <inline: true> numCopied > 0 ifTrue: [self ssFlushTo: simStackPtr]. optStatus isReceiverResultRegLive: false. objectRepresentation getActiveContextAllocatesInMachineCode ifTrue: [self ssAllocateCallReg: ReceiverResultReg and: SendNumArgsReg and: ClassReg] ifFalse: [self ssAllocateCallReg: SendNumArgsReg and: ReceiverResultReg]. objectRepresentation genCreateClosureAt: startpc + 1 "1 relative" numArgs: numArgs numCopied: numCopied contextNumArgs: methodOrBlockNumArgs large: (coInterpreter methodNeedsLargeContext: methodObj) inBlock: inBlock. numCopied > 0 ifTrue: [self ssPop: numCopied]. + self ssPushRegister: ReceiverResultReg - ^self ssPushRegister: ReceiverResultReg ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genPushClosureCopyCopiedValuesBytecode (in category 'bytecode generators') ----- genPushClosureCopyCopiedValuesBytecode "Block compilation. At this point in the method create the block. Note its start and defer generating code for it until after the method and any other preceeding blocks. The block's actual code will be compiled later." "143 10001111 llllkkkk jjjjjjjj iiiiiiii Push Closure Num Copied llll Num Args kkkk BlockSize jjjjjjjjiiiiiiii" | startpc numArgs numCopied | self assert: needsFrame. startpc := bytecodePC + (self generatorAt: byte0) numBytes. self addBlockStartAt: startpc "0 relative" numArgs: (numArgs := byte1 bitAnd: 16rF) numCopied: (numCopied := byte1 >> 4) span: (byte2 << 8) + byte3. + objectRepresentation createsClosuresInline - ^ objectRepresentation createsClosuresInline ifTrue: [ self genInlineClosure: startpc numArgs: numArgs numCopied: numCopied ] + ifFalse: [ self genOutlineClosure: startpc numArgs: numArgs numCopied: numCopied ]. + + ^ 0 - ifFalse: [ self genOutlineClosure: startpc numArgs: numArgs numCopied: numCopied ] !

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VM Maker: VMMaker.oscog-cb.1398.mcz
by commits＠source.squeak.org 29 Jun '15

29 Jun '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1398.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1398 Author: cb Time: 29 June 2015, 2:44:44.1 pm UUID: b7d7554c-3637-4d11-a5e1-4b97eeae7e5a Ancestors: VMMaker.oscog-cb.1397 rewrote the statement so the slang generator won't complain. =============== Diff against VMMaker.oscog-cb.1397 =============== Item was changed: ----- Method: StackToRegisterMappingCogit>>genPushRemoteTempLongBytecode (in category 'bytecode generators') ----- genPushRemoteTempLongBytecode | tempVectReg remoteTempReg | tempVectReg := self allocateRegNotConflictingWith: 0. self MoveMw: (self frameOffsetOfTemporary: byte2) r: FPReg R: tempVectReg. + remoteTempReg := self availableRegOrNilNotConflictingWith: (self registerMaskFor: tempVectReg). + remoteTempReg ifNil: [ remoteTempReg := tempVectReg ]. - remoteTempReg := (self availableRegOrNilNotConflictingWith: (self registerMaskFor: tempVectReg)) ifNil: [ tempVectReg ]. objectRepresentation genLoadSlot: byte1 sourceReg: tempVectReg destReg: remoteTempReg. ^self ssPushRegister: remoteTempReg!

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VM Maker: VMMaker.oscog-cb.1397.mcz
by commits＠source.squeak.org 29 Jun '15

29 Jun '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1397.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1397 Author: cb Time: 29 June 2015, 1:52:05.055 pm UUID: 2462319b-7f8e-4da4-8507-e6e14177bf44 Ancestors: VMMaker.oscog-cb.1396 separate the case where the specialSelector comparison has two constants as operands and share the code between the two JITs =============== Diff against VMMaker.oscog-cb.1396 =============== Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison "Override to count inlined branches if followed by a conditional branch. We borrow the following conditional branch's counter and when about to inline the comparison we decrement the counter (without writing it back) and if it trips simply abort the inlining, falling back to the normal send which will then continue to the conditional branch which will trip and enter the abort." | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor + rcvrIsInt argIsInt argInt jumpNotSmallInts inlineCAB annotateInst - rcvrIsInt argIsInt rcvrInt argInt result jumpNotSmallInts inlineCAB annotateInst counterAddress countTripped counterReg | <var: #countTripped type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> (coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ self genSpecialSelectorComparisonWithoutCounters ]. self ssFlushTo: simStackPtr - 2. primDescriptor := self generatorAt: byte0. argIsInt := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := (self ssValue: 1) type = SSConstant + and: [objectMemory isIntegerObject: (self ssValue: 1) constant]. - and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]. "short-cut the jump if operands are SmallInteger constants." (argIsInt and: [rcvrIsInt]) ifTrue: + [^ self genStaticallyResolvedSpecialSelectorComparison]. - [self cCode: '' inSmalltalk: "In Simulator ints are unsigned..." - [rcvrInt := objectMemory integerValueOf: rcvrInt. - argInt := objectMemory integerValueOf: argInt]. - primDescriptor opcode caseOf: { - [JumpLess] -> [result := rcvrInt < argInt]. - [JumpLessOrEqual] -> [result := rcvrInt <= argInt]. - [JumpGreater] -> [result := rcvrInt > argInt]. - [JumpGreaterOrEqual] -> [result := rcvrInt >= argInt]. - [JumpZero] -> [result := rcvrInt = argInt]. - [JumpNonZero] -> [result := rcvrInt ~= argInt] }. - "Must enter any annotatedConstants into the map" - self annotateBytecodeIfAnnotated: (self ssValue: 1). - self annotateBytecodeIfAnnotated: self ssTop. - "Must annotate the bytecode for correct pc mapping." - self ssPop: 2. - ^self ssPushAnnotatedConstant: (result - ifTrue: [objectMemory trueObject] - ifFalse: [objectMemory falseObject])]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsInt or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. argIsInt ifTrue: [(self ssValue: 1) popToReg: ReceiverResultReg. annotateInst := self ssTop annotateUse. self ssPop: 2. self MoveR: ReceiverResultReg R: TempReg] ifFalse: [self marshallSendArguments: 1. self MoveR: Arg0Reg R: TempReg. rcvrIsInt ifFalse: [objectRepresentation isSmallIntegerTagNonZero ifTrue: [self AndR: ReceiverResultReg R: TempReg] ifFalse: [self OrR: ReceiverResultReg R: TempReg]]]. jumpNotSmallInts := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg. counterReg := self allocateRegNotConflictingWith: (self registerMaskFor: ReceiverResultReg and: Arg0Reg). self genExecutionCountLogicInto: [ :cAddress :countTripBranch | counterAddress := cAddress. countTripped := countTripBranch ] counterReg: counterReg. argIsInt ifTrue: [annotateInst ifTrue: [self annotateBytecode: (self CmpCq: argInt R: ReceiverResultReg)] ifFalse: [self CmpCq: argInt R: ReceiverResultReg]] ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self gen: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self genFallsThroughCountLogicCounterReg: counterReg counterAddress: counterAddress. self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). countTripped jmpTarget: (jumpNotSmallInts jmpTarget: self Label). argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg]. ^self genMarshalledSend: (coInterpreter specialSelector: byte0 - self firstSpecialSelectorBytecodeOffset) numArgs: 1 sendTable: ordinarySendTrampolines! Item was changed: ----- Method: StackToRegisterMappingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor + rcvrIsInt argIsInt argInt jumpNotSmallInts inlineCAB annotateInst | - rcvrIsInt argIsInt rcvrInt argInt result jumpNotSmallInts inlineCAB annotateInst | <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> self ssFlushTo: simStackPtr - 2. primDescriptor := self generatorAt: byte0. argIsInt := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := (self ssValue: 1) type = SSConstant + and: [objectMemory isIntegerObject: (self ssValue: 1) constant]. - and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]. (argIsInt and: [rcvrIsInt]) ifTrue: + [^ self genStaticallyResolvedSpecialSelectorComparison]. - [self cCode: '' inSmalltalk: "In Simulator ints are unsigned..." - [rcvrInt := objectMemory integerValueOf: rcvrInt. - argInt := objectMemory integerValueOf: argInt]. - primDescriptor opcode caseOf: { - [JumpLess] -> [result := rcvrInt < argInt]. - [JumpLessOrEqual] -> [result := rcvrInt <= argInt]. - [JumpGreater] -> [result := rcvrInt > argInt]. - [JumpGreaterOrEqual] -> [result := rcvrInt >= argInt]. - [JumpZero] -> [result := rcvrInt = argInt]. - [JumpNonZero] -> [result := rcvrInt ~= argInt] }. - "Must enter any annotatedConstants into the map" - self annotateBytecodeIfAnnotated: (self ssValue: 1). - self annotateBytecodeIfAnnotated: self ssTop. - "Must annotate the bytecode for correct pc mapping." - self ssPop: 2. - ^self ssPushAnnotatedConstant: (result - ifTrue: [objectMemory trueObject] - ifFalse: [objectMemory falseObject])]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsInt or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. argIsInt ifTrue: [(self ssValue: 1) popToReg: ReceiverResultReg. annotateInst := self ssTop annotateUse. self ssPop: 2. self MoveR: ReceiverResultReg R: TempReg] ifFalse: [self marshallSendArguments: 1. self MoveR: Arg0Reg R: TempReg. rcvrIsInt ifFalse: [objectRepresentation isSmallIntegerTagNonZero ifTrue: [self AndR: ReceiverResultReg R: TempReg] ifFalse: [self OrR: ReceiverResultReg R: TempReg]]]. jumpNotSmallInts := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg. argIsInt ifTrue: [annotateInst ifTrue: [self annotateBytecode: (self CmpCq: argInt R: ReceiverResultReg)] ifFalse: [self CmpCq: argInt R: ReceiverResultReg]] ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self gen: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). jumpNotSmallInts jmpTarget: self Label. argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg]. ^self genMarshalledSend: (coInterpreter specialSelector: byte0 - self firstSpecialSelectorBytecodeOffset) numArgs: 1 sendTable: ordinarySendTrampolines.! Item was added: + ----- Method: StackToRegisterMappingCogit>>genStaticallyResolvedSpecialSelectorComparison (in category 'bytecode generator support') ----- + genStaticallyResolvedSpecialSelectorComparison + "Assumes both operands are ints" + <var: #primDescriptor type: #'BytecodeDescriptor *'> + | rcvrInt argInt primDescriptor result | + primDescriptor := self generatorAt: byte0. + argInt := self ssTop constant. + rcvrInt := (self ssValue: 1) constant. + self cCode: '' inSmalltalk: "In Simulator ints are unsigned..." + [rcvrInt := objectMemory integerValueOf: rcvrInt. + argInt := objectMemory integerValueOf: argInt]. + primDescriptor opcode caseOf: { + [JumpLess] -> [result := rcvrInt < argInt]. + [JumpLessOrEqual] -> [result := rcvrInt <= argInt]. + [JumpGreater] -> [result := rcvrInt > argInt]. + [JumpGreaterOrEqual] -> [result := rcvrInt >= argInt]. + [JumpZero] -> [result := rcvrInt = argInt]. + [JumpNonZero] -> [result := rcvrInt ~= argInt] }. + "Must enter any annotatedConstants into the map" + self annotateBytecodeIfAnnotated: (self ssValue: 1). + self annotateBytecodeIfAnnotated: self ssTop. + "Must annotate the bytecode for correct pc mapping." + self ssPop: 2. + ^self ssPushAnnotatedConstant: (result + ifTrue: [objectMemory trueObject] + ifFalse: [objectMemory falseObject])!

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VM Maker: VMMaker.oscog-cb.1396.mcz
by commits＠source.squeak.org 29 Jun '15

29 Jun '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1396.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1396 Author: cb Time: 29 June 2015, 1:29:37.265 pm UUID: ec6d1c5e-1867-428f-9163-9f54422ce6f9 Ancestors: VMMaker.oscog-cb.1395 fixed trinaryInlined primitive which was forcing a reg to be ReceiverResult reg when it shouldn't. ... =============== Diff against VMMaker.oscog-cb.1394 =============== Item was changed: ----- Method: StackToRegisterMappingCogit>>genTrinaryInlinePrimitive: (in category 'inline primitive generators') ----- genTrinaryInlinePrimitive: prim "Unary inline primitives." "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution. See EncoderForSistaV1's class comment and StackInterpreter>>#trinaryInlinePrimitive:" | ra1 ra2 rr adjust needsStoreCheck | "The store check requires rr to be ReceiverResultReg" + needsStoreCheck := (objectRepresentation isUnannotatableConstant: self ssTop) not. self allocateRegForStackTopThreeEntriesInto: [:rTop :rNext :rThird | ra2 := rTop. ra1 := rNext. rr := rThird ] + thirdIsReceiver: (prim = 0 and: [ needsStoreCheck ]). - thirdIsReceiver: prim = 0. self assert: (rr ~= ra1 and: [rr ~= ra2 and: [ra1 ~= ra2]]). - needsStoreCheck := (objectRepresentation isUnannotatableConstant: self ssTop) not. self ssTop popToReg: ra2. self ssPop: 1. self ssTop popToReg: ra1. self ssPop: 1. self ssTop popToReg: rr. self ssPop: 1. objectRepresentation genConvertSmallIntegerToIntegerInReg: ra1. "Now: ra is the variable object, rr is long, TempReg holds the value to store." prim caseOf: { "0 - 1 pointerAt:put: and byteAt:Put:" [0] -> [ adjust := (objectMemory baseHeaderSize >> objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" adjust ~= 0 ifTrue: [ self AddCq: adjust R: ra1. ]. self MoveR: ra2 Xwr: ra1 R: rr. "I added needsStoreCheck so if you initialize an array with a Smi such as 0 or a boolean you don't need the store check" needsStoreCheck ifTrue: [ self assert: needsFrame. objectRepresentation genStoreCheckReceiverReg: rr valueReg: ra2 scratchReg: TempReg inFrame: true] ]. [1] -> [ objectRepresentation genConvertSmallIntegerToIntegerInReg: ra2. adjust := objectMemory baseHeaderSize - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" self AddCq: adjust R: ra1. self MoveR: ra2 Xbr: ra1 R: rr. objectRepresentation genConvertIntegerToSmallIntegerInReg: ra2. ] } otherwise: [^EncounteredUnknownBytecode]. self ssPushRegister: ra2. ^0! Item was added: + ----- Method: StackToRegisterMappingCogit>>ssFlushUpThrough: (in category 'simulation stack') ----- + ssFlushUpThrough: unaryBlock + "Any occurrences on the stack of the value being stored (which is the top of stack) + must be flushed, and hence any values colder than them stack." + <inline: true> + simStackPtr - 1 to: (simSpillBase max: 0) by: -1 do: + [ :index | + (unaryBlock value: (self simStackAt: index)) ifTrue: [ ^ self ssFlushTo: index ] ]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushUpThroughReceiverVariable: (in category 'simulation stack') ----- ssFlushUpThroughReceiverVariable: slotIndex "Any occurrences on the stack of the value being stored (which is the top of stack) must be flushed, and hence any values colder than them stack." <var: #desc type: #'CogSimStackEntry *'> + self ssFlushUpThrough: + [ :desc | + desc type = SSBaseOffset + and: [desc register = ReceiverResultReg + and: [desc offset = (objectRepresentation slotOffsetOfInstVarIndex: slotIndex) ] ] ]! - simStackPtr - 1 to: (simSpillBase max: 0) by: -1 do: - [:index| | desc | - desc := self simStackAt: index. - (desc type = SSBaseOffset - and: [desc register = ReceiverResultReg - and: [desc offset = (objectRepresentation slotOffsetOfInstVarIndex: slotIndex)]]) ifTrue: - [self ssFlushTo: index. - ^self]]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushUpThroughRegister: (in category 'simulation stack') ----- ssFlushUpThroughRegister: reg "Any occurrences on the stack of the register must be flushed, and hence any values colder than them stack." <var: #desc type: #'CogSimStackEntry *'> + self ssFlushUpThrough: [ :desc | desc type = SSRegister and: [ desc register = reg ] ]! - simStackPtr - 1 to: (simSpillBase max: 0) by: -1 do: - [:index| | desc | - desc := self simStackAt: index. - (desc type = SSRegister - and: [desc register = reg]) ifTrue: - [self ssFlushTo: index. - ^self]]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushUpThroughTemporaryVariable: (in category 'simulation stack') ----- ssFlushUpThroughTemporaryVariable: tempIndex "Any occurrences on the stack of the value being stored (which is the top of stack) must be flushed, and hence any values colder than them stack." <var: #desc type: #'CogSimStackEntry *'> + self ssFlushUpThrough: + [ :desc | + desc type = SSBaseOffset + and: [desc register = FPReg + and: [desc offset = (self frameOffsetOfTemporary: tempIndex) ] ] ]! - simStackPtr - 1 to: simSpillBase by: -1 do: - [:index| | desc | - desc := self simStackAt: index. - (desc type = SSBaseOffset - and: [desc register = FPReg - and: [desc offset = (self frameOffsetOfTemporary: tempIndex)]]) ifTrue: - [self ssFlushTo: index. - ^self]]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPushAnnotatedConstant: (in category 'simulation stack') ----- ssPushAnnotatedConstant: literal self ssPush: 1. + self updateSimSpillBase. - simSpillBase > simStackPtr ifTrue: - [simSpillBase := simStackPtr max: 0]. self ssTop type: SSConstant; annotateUse: true; spilled: false; constant: literal; bcptr: bytecodePC. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPushBase:offset: (in category 'simulation stack') ----- ssPushBase: reg offset: offset self ssPush: 1. + self updateSimSpillBase. - simSpillBase > simStackPtr ifTrue: - [simSpillBase := simStackPtr max: 0]. self ssTop type: SSBaseOffset; spilled: false; annotateUse: false; register: reg; offset: offset; bcptr: bytecodePC. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPushConstant: (in category 'simulation stack') ----- ssPushConstant: literal self ssPush: 1. + self updateSimSpillBase. - simSpillBase > simStackPtr ifTrue: - [simSpillBase := simStackPtr max: 0]. self ssTop type: SSConstant; spilled: false; annotateUse: false; constant: literal; bcptr: bytecodePC. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPushDesc: (in category 'simulation stack') ----- ssPushDesc: simStackEntry <var: #simStackEntry type: #CogSimStackEntry> self cCode: [simStackEntry type = SSSpill ifTrue: [simStackEntry type: SSBaseOffset]. simStackEntry spilled: false; annotateUse: false; bcptr: bytecodePC. simStack at: (simStackPtr := simStackPtr + 1) put: simStackEntry] inSmalltalk: [(simStack at: (simStackPtr := simStackPtr + 1)) copyFrom: simStackEntry; type: (simStackEntry type = SSSpill ifTrue: [SSBaseOffset] ifFalse: [simStackEntry type]); spilled: false; annotateUse: false; bcptr: bytecodePC]. + self updateSimSpillBase. - simSpillBase > simStackPtr ifTrue: - [simSpillBase := simStackPtr max: 0]. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssPushRegister: (in category 'simulation stack') ----- ssPushRegister: reg self ssPush: 1. + self updateSimSpillBase. - simSpillBase > simStackPtr ifTrue: - [simSpillBase := simStackPtr max: 0]. self ssTop type: SSRegister; spilled: false; annotateUse: false; register: reg; bcptr: bytecodePC. ^0! Item was added: + ----- Method: StackToRegisterMappingCogit>>updateSimSpillBase (in category 'simulation stack') ----- + updateSimSpillBase + simSpillBase > simStackPtr ifTrue: + [simSpillBase := simStackPtr max: 0].!

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VM Maker: VMMaker.oscog-cb.1394.mcz
by commits＠source.squeak.org 29 Jun '15

29 Jun '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1394.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1394 Author: cb Time: 29 June 2015, 12:52:59.639 pm UUID: bcbb50b5-80d7-4f84-bb1d-48ffc770dae1 Ancestors: VMMaker.oscog-cb.1393 optStatus ssEntry was initialized only in frameless methods, it is now initialized also in frameful methods. This allows to remove the checks for optStatus ssEntry = (self addressOf: simSelf) at multiple places in the code. =============== Diff against VMMaker.oscog-cb.1393 =============== Item was changed: ----- Method: StackToRegisterMappingCogit>>ensureReceiverResultRegContainsSelf (in category 'bytecode generator support') ----- ensureReceiverResultRegContainsSelf needsFrame ifTrue: + [optStatus isReceiverResultRegLive ifFalse: - [(optStatus isReceiverResultRegLive - and: [optStatus ssEntry = (self addressOf: simSelf)]) ifFalse: [self ssAllocateRequiredReg: ReceiverResultReg. (self addressOf: simSelf) storeToReg: ReceiverResultReg]. + optStatus isReceiverResultRegLive: true] - optStatus - isReceiverResultRegLive: true; - ssEntry: (self addressOf: simSelf)] ifFalse: [self assert: (simSelf type = SSRegister and: [simSelf register = ReceiverResultReg]). self assert: (optStatus isReceiverResultRegLive and: [optStatus ssEntry = (self addressOf: simSelf)])]! Item was changed: ----- Method: StackToRegisterMappingCogit>>genPushReceiverBytecode (in category 'bytecode generators') ----- genPushReceiverBytecode + optStatus isReceiverResultRegLive ifTrue: - (optStatus isReceiverResultRegLive - and: [optStatus ssEntry = (self addressOf: simSelf)]) ifTrue: [^self ssPushRegister: ReceiverResultReg]. ^self ssPushDesc: simSelf! Item was changed: ----- Method: StackToRegisterMappingCogit>>genReturnReceiver (in category 'bytecode generators') ----- genReturnReceiver "In a frameless method ReceiverResultReg already contains self. In a frameful method, ReceiverResultReg /may/ contain self." needsFrame ifTrue: + [ optStatus isReceiverResultRegLive ifFalse: + [ (self addressOf: simSelf) storeToReg: ReceiverResultReg]]. - [(optStatus isReceiverResultRegLive - and: [optStatus ssEntry = (self addressOf: simSelf)]) ifFalse: - [self MoveMw: FoxMFReceiver r: FPReg R: ReceiverResultReg]]. ^self genUpArrowReturn! Item was changed: ----- Method: StackToRegisterMappingCogit>>initSimStackForFramefulMethod: (in category 'simulation stack') ----- initSimStackForFramefulMethod: startpc <var: #desc type: #'CogSimStackEntry *'> - optStatus isReceiverResultRegLive: false. simSelf type: SSBaseOffset; spilled: true; annotateUse: false; register: FPReg; offset: FoxMFReceiver. + optStatus + isReceiverResultRegLive: false; + ssEntry: (self addressOf: simSelf). simSpillBase := methodOrBlockNumTemps. "N.B. Includes num args" simStackPtr := simSpillBase - 1. "args" 0 to: methodOrBlockNumArgs - 1 do: [:i| | desc | desc := self simStackAt: i. desc type: SSBaseOffset; spilled: true; annotateUse: false; register: FPReg; offset: FoxCallerSavedIP + ((methodOrBlockNumArgs - i) * objectMemory wordSize); bcptr: startpc]. "temps" methodOrBlockNumArgs to: simStackPtr do: [:i| | desc | desc := self simStackAt: i. desc type: SSBaseOffset; spilled: true; annotateUse: false; register: FPReg; offset: FoxMFReceiver - (i - methodOrBlockNumArgs + 1 * objectMemory wordSize); bcptr: startpc]!

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VM Maker: VMMaker.oscog-cb.1393.mcz
by commits＠source.squeak.org 29 Jun '15

29 Jun '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1393.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1393 Author: cb Time: 29 June 2015, 11:15:38.181 am UUID: a8818eac-bc1d-46a0-8131-d0b52265c57b Ancestors: VMMaker.oscog-rmacnak.1392 rename from availableRegNotConflictingWith: to: #availableRegOrNilNotConflictingWith: to be more explicit put back Eliot's code written slightly better for pushRemoteTemp as it make sense on slow processor (maybe it impacts things like the PI) refactor a bit the closure code I was reading to avoid important code duplication. =============== Diff against VMMaker.oscog-rmacnak.1392 =============== Item was removed: - ----- Method: StackToRegisterMappingCogit>>availableRegNotConflictingWith: (in category 'simulation stack') ----- - availableRegNotConflictingWith: regMask - <inline: true> - "If there's a free register, answer it, otherwise answer nil." - ^backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: regMask)! Item was added: + ----- Method: StackToRegisterMappingCogit>>availableRegOrNilNotConflictingWith: (in category 'simulation stack') ----- + availableRegOrNilNotConflictingWith: regMask + <inline: true> + "If there's a free register, answer it, otherwise answer nil." + ^backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: regMask)! Item was changed: ----- Method: StackToRegisterMappingCogit>>genExtPushClosureBytecode (in category 'bytecode generators') ----- genExtPushClosureBytecode "Block compilation. At this point in the method create the block. Note its start and defer generating code for it until after the method and any other preceeding blocks. The block's actual code will be compiled later." "253 11111101 eei i i kkk jjjjjjjj Push Closure Num Copied iii (+ Ext A // 16 * 8) Num Args kkk (+ Ext A \\ 16 * 8) BlockSize jjjjjjjj (+ Ext B * 256). ee = num extensions" | startpc numArgs numCopied | self assert: needsFrame. startpc := bytecodePC + (self generatorAt: byte0) numBytes. self addBlockStartAt: startpc "0 relative" numArgs: (numArgs := (byte1 bitAnd: 16r7) + (extA \\ 16 * 8)) numCopied: (numCopied := ((byte1 >> 3) bitAnd: 7) + (extA // 16 * 8)) span: byte2 + (extB << 8). extA := extB := 0. + ^ objectRepresentation createsClosuresInline + ifTrue: [ self genInlineClosure: startpc numArgs: numArgs numCopied: numCopied ] + ifFalse: [ self genOutlineClosure: startpc numArgs: numArgs numCopied: numCopied ]! - objectRepresentation createsClosuresInline ifTrue: - [self assert: objectRepresentation getActiveContextAllocatesInMachineCode. - optStatus isReceiverResultRegLive: false. - self ssAllocateCallReg: ReceiverResultReg - and: SendNumArgsReg - and: ClassReg. - objectRepresentation - genNoPopCreateClosureAt: startpc + 1 "1 relative" - numArgs: numArgs - numCopied: numCopied - contextNumArgs: methodOrBlockNumArgs - large: (coInterpreter methodNeedsLargeContext: methodObj) - inBlock: inBlock. - 1 to: numCopied do: - [:i| | reg | - reg := self ssStorePop: true toPreferredReg: TempReg. - objectRepresentation - genStoreSourceReg: reg - slotIndex: ClosureFirstCopiedValueIndex + numCopied - i - intoNewObjectInDestReg: ReceiverResultReg]. - ^self ssPushRegister: ReceiverResultReg]. - - numCopied > 0 ifTrue: - [self ssFlushTo: simStackPtr]. - optStatus isReceiverResultRegLive: false. - objectRepresentation getActiveContextAllocatesInMachineCode - ifTrue: [self ssAllocateCallReg: ReceiverResultReg - and: SendNumArgsReg - and: ClassReg] - ifFalse: [self ssAllocateCallReg: SendNumArgsReg - and: ReceiverResultReg]. - objectRepresentation - genCreateClosureAt: startpc + 1 "1 relative" - numArgs: numArgs - numCopied: numCopied - contextNumArgs: methodOrBlockNumArgs - large: (coInterpreter methodNeedsLargeContext: methodObj) - inBlock: inBlock. - numCopied > 0 ifTrue: - [self ssPop: numCopied]. - ^self ssPushRegister: ReceiverResultReg! Item was added: + ----- Method: StackToRegisterMappingCogit>>genInlineClosure:numArgs:numCopied: (in category 'bytecode generator support') ----- + genInlineClosure: startpc numArgs: numArgs numCopied: numCopied + <inline: true> + self assert: objectRepresentation getActiveContextAllocatesInMachineCode. + optStatus isReceiverResultRegLive: false. + self ssAllocateCallReg: ReceiverResultReg + and: SendNumArgsReg + and: ClassReg. + objectRepresentation + genNoPopCreateClosureAt: startpc + 1 "1 relative" + numArgs: numArgs + numCopied: numCopied + contextNumArgs: methodOrBlockNumArgs + large: (coInterpreter methodNeedsLargeContext: methodObj) + inBlock: inBlock. + 1 to: numCopied do: + [:i| | reg | + reg := self ssStorePop: true toPreferredReg: TempReg. + objectRepresentation + genStoreSourceReg: reg + slotIndex: ClosureFirstCopiedValueIndex + numCopied - i + intoNewObjectInDestReg: ReceiverResultReg]. + ^self ssPushRegister: ReceiverResultReg + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>genOutlineClosure:numArgs:numCopied: (in category 'bytecode generator support') ----- + genOutlineClosure: startpc numArgs: numArgs numCopied: numCopied + <inline: true> + numCopied > 0 ifTrue: + [self ssFlushTo: simStackPtr]. + optStatus isReceiverResultRegLive: false. + objectRepresentation getActiveContextAllocatesInMachineCode + ifTrue: [self ssAllocateCallReg: ReceiverResultReg + and: SendNumArgsReg + and: ClassReg] + ifFalse: [self ssAllocateCallReg: SendNumArgsReg + and: ReceiverResultReg]. + objectRepresentation + genCreateClosureAt: startpc + 1 "1 relative" + numArgs: numArgs + numCopied: numCopied + contextNumArgs: methodOrBlockNumArgs + large: (coInterpreter methodNeedsLargeContext: methodObj) + inBlock: inBlock. + numCopied > 0 ifTrue: + [self ssPop: numCopied]. + ^self ssPushRegister: ReceiverResultReg + ! Item was changed: ----- Method: StackToRegisterMappingCogit>>genPushClosureCopyCopiedValuesBytecode (in category 'bytecode generators') ----- genPushClosureCopyCopiedValuesBytecode "Block compilation. At this point in the method create the block. Note its start and defer generating code for it until after the method and any other preceeding blocks. The block's actual code will be compiled later." "143 10001111 llllkkkk jjjjjjjj iiiiiiii Push Closure Num Copied llll Num Args kkkk BlockSize jjjjjjjjiiiiiiii" | startpc numArgs numCopied | self assert: needsFrame. startpc := bytecodePC + (self generatorAt: byte0) numBytes. self addBlockStartAt: startpc "0 relative" numArgs: (numArgs := byte1 bitAnd: 16rF) numCopied: (numCopied := byte1 >> 4) span: (byte2 << 8) + byte3. + ^ objectRepresentation createsClosuresInline + ifTrue: [ self genInlineClosure: startpc numArgs: numArgs numCopied: numCopied ] + ifFalse: [ self genOutlineClosure: startpc numArgs: numArgs numCopied: numCopied ] - objectRepresentation createsClosuresInline ifTrue: - [self assert: objectRepresentation getActiveContextAllocatesInMachineCode. - optStatus isReceiverResultRegLive: false. - self ssAllocateCallReg: ReceiverResultReg - and: SendNumArgsReg - and: ClassReg. - objectRepresentation - genNoPopCreateClosureAt: startpc + 1 "1 relative" - numArgs: numArgs - numCopied: numCopied - contextNumArgs: methodOrBlockNumArgs - large: (coInterpreter methodNeedsLargeContext: methodObj) - inBlock: inBlock. - 1 to: numCopied do: - [:i| | reg | - reg := self ssStorePop: true toPreferredReg: TempReg. - objectRepresentation - genStoreSourceReg: reg - slotIndex: ClosureFirstCopiedValueIndex + numCopied - i - intoNewObjectInDestReg: ReceiverResultReg]. - ^self ssPushRegister: ReceiverResultReg]. + ! - numCopied > 0 ifTrue: - [self ssFlushTo: simStackPtr]. - optStatus isReceiverResultRegLive: false. - objectRepresentation getActiveContextAllocatesInMachineCode - ifTrue: [self ssAllocateCallReg: ReceiverResultReg - and: SendNumArgsReg - and: ClassReg] - ifFalse: [self ssAllocateCallReg: SendNumArgsReg - and: ReceiverResultReg]. - objectRepresentation - genCreateClosureAt: startpc + 1 "1 relative" - numArgs: numArgs - numCopied: numCopied - contextNumArgs: methodOrBlockNumArgs - large: (coInterpreter methodNeedsLargeContext: methodObj) - inBlock: inBlock. - numCopied > 0 ifTrue: - [self ssPop: numCopied]. - ^self ssPushRegister: ReceiverResultReg! Item was changed: ----- Method: StackToRegisterMappingCogit>>genPushRemoteTempLongBytecode (in category 'bytecode generators') ----- genPushRemoteTempLongBytecode + | tempVectReg remoteTempReg | + tempVectReg := self allocateRegNotConflictingWith: 0. + self MoveMw: (self frameOffsetOfTemporary: byte2) r: FPReg R: tempVectReg. + remoteTempReg := (self availableRegOrNilNotConflictingWith: (self registerMaskFor: tempVectReg)) ifNil: [ tempVectReg ]. - | newReg | - newReg := self allocateRegNotConflictingWith: 0. - self MoveMw: (self frameOffsetOfTemporary: byte2) r: FPReg R: newReg. objectRepresentation genLoadSlot: byte1 + sourceReg: tempVectReg + destReg: remoteTempReg. + ^self ssPushRegister: remoteTempReg! - sourceReg: newReg - destReg: newReg. - ^self ssPushRegister: newReg!

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[commit][3392] Fix a syntax error in 64-bit linux build.
by commits＠squeakvm.org 28 Jun '15

28 Jun '15

Revision: 3392 Author: eliot Date: 2015-06-28 12:15:19 -0700 (Sun, 28 Jun 2015) Log Message: ----------- Fix a syntax error in 64-bit linux build. Update scripts to upload Newspeak ARM. Modified Paths: -------------- branches/Cog/build.linux64x64/squeak.stack.spur/build/mvm branches/Cog/scripts/mkspurvmarchives Added Paths: ----------- branches/Cog/scripts/mklinuxarchive Modified: branches/Cog/build.linux64x64/squeak.stack.spur/build/mvm =================================================================== --- branches/Cog/build.linux64x64/squeak.stack.spur/build/mvm 2015-06-27 18:55:10 UTC (rev 3391) +++ branches/Cog/build.linux64x64/squeak.stack.spur/build/mvm 2015-06-28 19:15:19 UTC (rev 3392) @@ -1,7 +1,7 @@ #!/bin/bash # Stack Spur VM with VM profiler and threaded heartbeat INSTALLDIR=stkspur64linuxht -OPT="-g -O1 -fwrapv -DNDEBUG -DDEBUGVM=0";; +OPT="-g -O1 -fwrapv -DNDEBUG -DDEBUGVM=0" if [ $# -ge 1 ]; then INSTALLDIR="$1"; shift Added: branches/Cog/scripts/mklinuxarchive =================================================================== --- branches/Cog/scripts/mklinuxarchive (rev 0) +++ branches/Cog/scripts/mklinuxarchive 2015-06-28 19:15:19 UTC (rev 3392) @@ -0,0 +1,72 @@ +#!/bin/sh +# Create one or more linux archives from VM trees in products. +# Output a check of version numbers etc to products/MLALOG +IFS=" +" +cd `dirname $0`/../products + +REV= +TAG= +EXES= + +while [ -n "$1" ]; do + case $1 in + -r) shift;REV="$1";; + -t) shift;TAG="$1";; + -?|-h) echo usage: $0 [-r REV -t TAG] [directories] + exit 0;; + -*) echo usage: $0 [-r REV -t TAG] [directories] + exit 1;; + *) break + esac +done +test -n "$REV" || REV=`grep 'SvnRawRevisionString.*Rev:' ../platforms/Cross/vm/sqSCCSVersion.h \ + | sed 's/^.*Rev: $[0-9][0-9]*$ $";/\1/'` +test -n "$TAG" || TAG=`date +%y.%U.`$REV +echo REV=$REV TAG=$TAG + +if [ $# = 0 ]; then + for f in *linux*/lib/*/*-$REV; do + d="`dirname \`dirname \\\`dirname $f\\\`\``" + case $d in + nscog*) archive="`echo $d | | sed 's/nscog/nsvm/'`";; + *) archive=$d + esac + exe="`basename \`dirname $f\``" + rm -rf $archive-$TAG.tgz + echo $d '=>' $archive-$TAG.tgz + COPYFILE_DISABLE=1 tar czf $archive-$TAG.tgz $d + EXES="$EXES $d/lib/$exe/[0-9.-]*/$exe" + done +else + for d in $*; do + d="`basename $d`" # allow products/blah + if [ -d "$d" ]; then + f=$d/lib/*/*-$REV + if [ -d $f ]; then + exe="`basename \`dirname $f\``" + case $d in + nscog*) archive="`echo $d | | sed 's/nscog/nsvm/'`";; + *) archive=$d + esac + rm -rf $archive-$TAG.tgz + echo $d '=>' $archive-$TAG.tgz + COPYFILE_DISABLE=1 tar czf $archive-$TAG.tgz $d + EXES="$EXES $d/lib/$exe/[0-9.-]*/$exe" + else + echo $0: could not find bin dir in $archive + fi + else + echo $0: could not find directory $archive + fi + done +fi +echo $EXES +for vm in $EXES +do + echo + echo checking $vm version + strings - $vm | egrep '\$Rev: |Interp.*VMMaker|Cogit.*VMMaker| built on ' | sed 's/ uuid:.*//' + echo checking $vm for asserts + strings - $vm | grep "assert[^0-9]*[0-9][0-9][0-9]" +done 2>&1 | tee MLALOG Property changes on: branches/Cog/scripts/mklinuxarchive ___________________________________________________________________ Added: svn:executable + * Modified: branches/Cog/scripts/mkspurvmarchives =================================================================== --- branches/Cog/scripts/mkspurvmarchives 2015-06-27 18:55:10 UTC (rev 3391) +++ branches/Cog/scripts/mkspurvmarchives 2015-06-28 19:15:19 UTC (rev 3392) @@ -58,8 +58,8 @@ done fi if [ -n "$NL" ]; then - set -- nscogspurlinux nscogspurlinuxht - for archive in nsvmspurlinux nsvmspurlinuxht; do + set -- nscogspurlinux nscogspurlinuxht nscogspurlinuxhtARM + for archive in nsvmspurlinux nsvmspurlinuxht nsvmspurlinuxhtARM; do rm -rf $archive-$TAG.tgz echo $1 '=>' $archive-$TAG.tgz COPYFILE_DISABLE=1 tar czf $archive-$TAG.tgz $1

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Re: [Vm-dev] VM Maker: VMMaker.oscog-eem.1391.mcz
by Clément Bera 28 Jun '15

28 Jun '15

I am confused, what did you do in the two last commits ? What is example response ? Was my code correct ? I tried the simulator only and it worked fine. 2015-06-27 21:44 GMT+02:00 <commits(a)source.squeak.org>: > > Eliot Miranda uploaded a new version of VMMaker to project VM Maker: > http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1391.mcz > > ==================== Summary ==================== > > Name: VMMaker.oscog-eem.1391 > Author: eem > Time: 27 June 2015, 12:43:14.39 pm > UUID: bdc64a36-203a-4f8f-b8e9-53ef7e41bfb9 > Ancestors: VMMaker.oscog-eem.1390 > > Revert back to Clément's version of > genPushRemoteTempLongBytecode now that > example response has been committed. > > =============== Diff against VMMaker.oscog-eem.1390 =============== > > Item was changed: > ----- Method: StackToRegisterMappingCogit>>genPushRemoteTempLongBytecode > (in category 'bytecode generators') ----- > genPushRemoteTempLongBytecode > + | newReg | > - | newReg freeReg | > newReg := self allocateRegNotConflictingWith: 0. > + self MoveMw: (self frameOffsetOfTemporary: byte2) r: FPReg R: > newReg. > - freeReg := self availableRegNotConflictingWith: (self > registerMaskFor: newReg). > - self MoveMw: (self frameOffsetOfTemporary: byte2) r: FPReg R: > (freeReg ifNil: newReg). > objectRepresentation > genLoadSlot: byte1 > + sourceReg: newReg > - sourceReg: (freeReg ifNil: newReg) > destReg: newReg. > ^self ssPushRegister: newReg! > >

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Vm-dev June 2015