Vm-dev December 2015

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VM Maker: VMMaker.oscog-eem.1608.mcz
by commits＠source.squeak.org 17 Dec '15

17 Dec '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1608.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1608 Author: eem Time: 17 December 2015, 9:14:34.651 am UUID: bf1e1bd4-7dd4-47e2-bb33-3a988cc4c276 Ancestors: VMMaker.oscog-eem.1607 x64 Cogit: Refactor genLookupForPerformNumArgs: along the same lines as compileOpenPIC:numArgs: to use a base reg to access the metod dict when outside the MoveMw:r:R: offset range. =============== Diff against VMMaker.oscog-eem.1607 =============== Item was changed: ----- Method: CogObjectRepresentationFor64BitSpur>>allImmediate:branchIf:notInstanceOfBehaviors:target: (in category 'sista support') ----- allImmediate: immediateMask branchIf: reg notInstanceOfBehaviors: arrayObj target: targetFixUp | incorrectTag tag1 tag2 | <var: #targetFixUp type: #'AbstractInstruction *'> (self genJumpNotImmediate: reg) jmpTarget: targetFixUp. immediateMask = objectMemory tagMask ifFalse: [ "TempReg holds the rcvr tag" "In this case one immediate tag out of the three is not present in arrayObj. We look for it, and generate a jump to the fixup if the rcvr tag matches" tag1 := objectMemory classTagForClass: (objectMemory fetchPointer: 0 ofObject: arrayObj). tag2 := objectMemory classTagForClass: (objectMemory fetchPointer: 1 ofObject: arrayObj). incorrectTag := self fetchImmediateTagOtherThanTag1: tag1 tag2: tag2. cogit CmpCq: incorrectTag R: TempReg. + cogit JumpZero: targetFixUp]. + ^0! - cogit JumpZero: targetFixUp ].! Item was changed: ----- Method: SimpleStackBasedCogit>>compileOpenPICMethodCacheProbeFor:withShift:baseRegOrNone: (in category 'in-line cacheing') ----- compileOpenPICMethodCacheProbeFor: selector withShift: shift baseRegOrNone: baseRegOrNone + "Compile one method cache probe in an OpenPIC's lookup of selector. + Answer the jump taken if the selector probe fails." - "Compile one method cache probe in an OpenPIC's lookup of selector. Answer the jump taken if the selector probe fails." <returnTypeC: #'AbstractInstruction *'> <inline: false> | jumpSelectorMiss | <var: 'jumpSelectorMiss' type: #'AbstractInstruction *'> self MoveR: SendNumArgsReg R: ClassReg. self annotate: (self XorCw: selector R: ClassReg) objRef: selector. objectMemory shiftForWord > shift ifTrue: [self LogicalShiftLeftCq: objectMemory shiftForWord - shift R: ClassReg]. self AndCq: MethodCacheMask << objectMemory shiftForWord R: ClassReg. baseRegOrNone = NoReg ifTrue: [self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheSelector << objectMemory shiftForWord) r: ClassReg R: TempReg] ifFalse: [self AddR: baseRegOrNone R: ClassReg; MoveMw: MethodCacheSelector << objectMemory shiftForWord r: ClassReg R: TempReg]. self annotate: (self CmpCw: selector R: TempReg) objRef: selector. jumpSelectorMiss := self JumpNonZero: 0. baseRegOrNone = NoReg ifTrue: [self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheClass << objectMemory shiftForWord) r: ClassReg R: TempReg] ifFalse: [self MoveMw: MethodCacheClass << objectMemory shiftForWord r: ClassReg R: TempReg]. self CmpR: SendNumArgsReg R: TempReg. ^jumpSelectorMiss! Item was added: + ----- Method: SimpleStackBasedCogit>>compilePerformMethodCacheProbeFor:withShift:baseRegOrNone: (in category 'in-line cacheing') ----- + compilePerformMethodCacheProbeFor: selectorReg withShift: shift baseRegOrNone: baseRegOrNone + "Compile one method cache probe in a perform: primitive's lookup of selector. + Answer the jump taken if the selector probe fails." + <returnTypeC: #'AbstractInstruction *'> + <inline: false> + | jumpSelectorMiss | + <var: 'jumpSelectorMiss' type: #'AbstractInstruction *'> + self MoveR: SendNumArgsReg R: ClassReg. + self XorR: selectorReg R: ClassReg. + objectMemory shiftForWord > shift ifTrue: + [self LogicalShiftLeftCq: objectMemory shiftForWord - shift R: ClassReg]. + self AndCq: MethodCacheMask << objectMemory shiftForWord R: ClassReg. + baseRegOrNone = NoReg + ifTrue: + [self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheSelector << objectMemory shiftForWord) + r: ClassReg + R: TempReg] + ifFalse: + [self AddR: baseRegOrNone R: ClassReg; + MoveMw: MethodCacheSelector << objectMemory shiftForWord r: ClassReg R: TempReg]. + self CmpR: selectorReg R: TempReg. + jumpSelectorMiss := self JumpNonZero: 0. + baseRegOrNone = NoReg + ifTrue: + [self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheClass << objectMemory shiftForWord) + r: ClassReg + R: TempReg] + ifFalse: + [self MoveMw: MethodCacheClass << objectMemory shiftForWord r: ClassReg R: TempReg]. + self CmpR: SendNumArgsReg R: TempReg. + ^jumpSelectorMiss! Item was changed: ----- Method: SimpleStackBasedCogit>>genLookupForPerformNumArgs: (in category 'primitive generators') ----- genLookupForPerformNumArgs: numArgs "Compile the code for a probe of the first-level method cache for a perform primtiive. The selector is assumed to be in Arg0Reg. Defer to adjustArgumentsForPerform: to adjust the arguments before the jump to the method." + | jumpSelectorMiss jumpClassMiss jumpInterpret itsAHit cacheBaseReg | - | jumpSelectorMiss jumpClassMiss jumpInterpret itsAHit | <var: #jumpSelectorMiss type: #'AbstractInstruction *'> <var: #jumpClassMiss type: #'AbstractInstruction *'> <var: #jumpInterpret type: #'AbstractInstruction *'> <var: #itsAHit type: #'AbstractInstruction *'> "N.B. Can't assume TempReg already contains the tag because a method can of course be invoked via the unchecked entry-point, e.g. as does perform:." + objectRepresentation genGetInlineCacheClassTagFrom: ReceiverResultReg into: SendNumArgsReg forEntry: false. - objectRepresentation genGetInlineCacheClassTagFrom: ReceiverResultReg into: ClassReg forEntry: false. - "Do first of three probes. See StackInterpreter>>lookupInMethodCacheSel:classTag:" self flag: #lookupInMethodCacheSel:classTag:. "so this method shows up as a sender of lookupInMethodCacheSel:class:" + + cacheBaseReg := NoReg. + (backEnd isWithinMwOffsetRange: coInterpreter methodCacheAddress) ifFalse: + [self MoveCq: coInterpreter methodCacheAddress R: (cacheBaseReg := Scratch0Reg)]. + + "Do first of three probes. See CoInterpreter>>lookupInMethodCacheSel:classTag:" + jumpSelectorMiss := self compilePerformMethodCacheProbeFor: Arg0Reg withShift: 0 baseRegOrNone: cacheBaseReg. - self MoveR: ClassReg R: SendNumArgsReg. - self XorR: Arg0Reg R: ClassReg. - self LogicalShiftLeftCq: objectMemory shiftForWord R: ClassReg. - self AndCq: MethodCacheMask << objectMemory shiftForWord R: ClassReg. - self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheSelector << objectMemory shiftForWord) - r: ClassReg - R: TempReg. - self CmpR: Arg0Reg R: TempReg. - jumpSelectorMiss := self JumpNonZero: 0. - self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheClass << objectMemory shiftForWord) - r: ClassReg - R: TempReg. - self CmpR: SendNumArgsReg R: TempReg. jumpClassMiss := self JumpNonZero: 0. + "Fetch the method, and check if it is cogged." + itsAHit := self MoveMw: (cacheBaseReg = NoReg + ifTrue: [coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheMethod << objectMemory shiftForWord)] + ifFalse: [MethodCacheMethod << objectMemory shiftForWord]) + r: ClassReg + R: SendNumArgsReg. - itsAHit := self Label. - "Fetch the method, and check it is cogged." - self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheMethod << objectMemory shiftForWord) - r: ClassReg - R: SendNumArgsReg. "If the method is not compiled fall back on the interpreter primitive." objectRepresentation genLoadSlot: HeaderIndex sourceReg: SendNumArgsReg destReg: ClassReg. jumpInterpret := objectRepresentation genJumpImmediate: ClassReg. "Adjust arguments and jump to the method's unchecked entry-point." self AddCq: cmNoCheckEntryOffset R: ClassReg. self adjustArgumentsForPerform: numArgs. self JumpR: ClassReg. "First probe missed. Do second of three probes. Shift hash right one and retry." jumpSelectorMiss jmpTarget: (jumpClassMiss jmpTarget: self Label). + jumpSelectorMiss := self compilePerformMethodCacheProbeFor: Arg0Reg withShift: 1 baseRegOrNone: cacheBaseReg. - self MoveR: SendNumArgsReg R: ClassReg. - self XorR: Arg0Reg R: ClassReg. - self LogicalShiftLeftCq: objectMemory shiftForWord - 1 R: ClassReg. - self AndCq: MethodCacheMask << objectMemory shiftForWord R: ClassReg. - self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheSelector << objectMemory shiftForWord) - r: ClassReg - R: TempReg. - self CmpR: Arg0Reg R: TempReg. - jumpSelectorMiss := self JumpNonZero: 0. - self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheClass << objectMemory shiftForWord) - r: ClassReg - R: TempReg. - self CmpR: SendNumArgsReg R: TempReg. self JumpZero: itsAHit. "Second probe missed. Do last probe. Shift hash right two and retry." jumpSelectorMiss jmpTarget: self Label. + jumpSelectorMiss := self compilePerformMethodCacheProbeFor: Arg0Reg withShift: 1 baseRegOrNone: cacheBaseReg. - self MoveR: SendNumArgsReg R: ClassReg. - self XorR: Arg0Reg R: ClassReg. - objectMemory shiftForWord > 2 ifTrue: - [self LogicalShiftLeftCq: objectMemory shiftForWord - 1 R: ClassReg]. - self AndCq: MethodCacheMask << objectMemory shiftForWord R: ClassReg. - self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheSelector << objectMemory shiftForWord) - r: ClassReg - R: TempReg. - self CmpR: Arg0Reg R: TempReg. - jumpSelectorMiss := self JumpNonZero: 0. - self MoveMw: coInterpreter methodCacheAddress asUnsignedInteger + (MethodCacheClass << objectMemory shiftForWord) - r: ClassReg - R: TempReg. - self CmpR: SendNumArgsReg R: TempReg. self JumpZero: itsAHit. "Last probe missed. Caller will generate the call to fall back on the interpreter primitive." jumpSelectorMiss jmpTarget: (jumpInterpret jmpTarget: self Label). ^0!

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VM Maker: Cog-eem.311.mcz
by commits＠source.squeak.org 17 Dec '15

17 Dec '15

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.311.mcz ==================== Summary ==================== Name: Cog-eem.311 Author: eem Time: 17 December 2015, 9:12:51.591 am UUID: 0e27e1e0-b2f9-4e89-9c6d-57da998c94fc Ancestors: Cog-eem.310 Fix slip in relative address disassembly decoration. =============== Diff against Cog-eem.310 =============== Item was changed: ----- Method: BochsIA32Alien>>decorateDisassembly:for:fromAddress: (in category 'disassembly') ----- decorateDisassembly: anInstructionString for: aSymbolManager "<Cogit>" fromAddress: address | string i1 i2 v | string := anInstructionString. aSymbolManager relativeBaseForDisassemblyInto: [:baseAddress :baseName| string := baseName, '+', (address - baseAddress printStringBase: 16 length: 4 padded: true), (string copyFrom: (string indexOf: $:) + 1 to: string size)]. - aSymbolManager relativeBaseForDisassemblyInto: - [:baseAddress :baseName| | stream delta | - stream := ReadStream on: string from: 1 to: string size. - delta := (Integer readFrom: stream base: 16) - baseAddress. - string := baseName, '+', (delta printStringBase: 16 length: 4 padded: true), (string copyFrom: stream position to: stream size)]. (i1 := string indexOfSubCollection: '%ds:0x') > 0 ifTrue: [i2 := i1 + 6. ['0123456789abcdef' includes: (string at: i2)] whileTrue: [i2 := i2 + 1]. string := string copyReplaceFrom: i1 + 4 to: i2 - 1 with: (aSymbolManager lookupCHexString: (string copyFrom: i1 + 4 to: i2 - 1))]. (i1 := string indexOfSubCollection: '%ss:0x') > 0 ifTrue: [i2 := i1 + 6. ['0123456789abcdef' includes: (string at: i2)] whileTrue: [i2 := i2 + 1]. ((string at: i2) = $( and: [(string at: i2 + 1) = $%]) ifTrue: [v := Integer readFrom: (ReadStream on: string from: i1 + 6 to: i2 - 1) base: 16. string := string copyReplaceFrom: i1 to: i2 - 1 with: ((v bitAnd: (1 bitShift: 31) - 1) - (v bitAnd: (1 bitShift: 31))) printString]]. (i1 := string indexOfSubCollection: '$0x') > 0 ifTrue: [i2 := i1 + 3. ['0123456789abcdef' includes: (string at: i2)] whileTrue: [i2 := i2 + 1]. string := string copyReplaceFrom: i1 + 1 to: i2 - 1 with: (aSymbolManager lookupCHexString: (string copyFrom: i1 + 1 to: i2 - 1))]. ((i1 := string indexOf: $() > 1 and: [(string at: i1 + 1) isDigit and: [i1 < (i2 := string indexOf: $))]]) ifTrue: [string := string copyReplaceFrom: i1 + 1 to: i2 - 1 with: (aSymbolManager lookupCHexString: (string copyFrom: i1 + 1 to: i2 - 1))]. ^string!

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Re: [Vm-dev] VM Maker: VMMaker.oscog-rmacnak.1595.mcz
by Eliot Miranda 17 Dec '15

17 Dec '15

Hi Ryan, On Mon, Dec 14, 2015 at 7:32 PM, <commits(a)source.squeak.org> wrote: > > Ryan Macnak uploaded a new version of VMMaker to project VM Maker: > http://source.squeak.org/VMMaker/VMMaker.oscog-rmacnak.1595.mcz > > ==================== Summary ==================== > > Name: VMMaker.oscog-rmacnak.1595 > Author: rmacnak > Time: 14 December 2015, 7:29:18.283 pm > UUID: 3aac3671-b1ff-45b9-8ed0-f3ecc5bca0b3 > Ancestors: VMMaker.oscog-eem.1594 > > MIPS: Complete simulation of the Newspeak test suite! (~30 billion > instructions) (Modulo Aliens, which don't work under the IA32 simulation > either.) > Can you say a little bit more about this? How long did the simulation take? What machine(s) did you run it on? I *love* that you caught the MNU in followForwardingPointersInScheduler. I want to set this up for Squeak but never had the patience/.resources before. > Fix off-by-8 in patching I-type branches. Bug had the effect of skipping > loading the cPIC address for a cPIC miss if the cPIC was created for an MNU > case. > > Handle PushCw in storeLiteral:beforeFollowingAddress:. > > Add the GC's variant of rewriteInlineCacheTag:at:. > > Fix MNU in followForwardingPointersInScheduler. > > =============== Diff against VMMaker.oscog-eem.1594 =============== > > Item was changed: > ----- Method: CogMIPSELCompiler>>rewriteITypeBranchAtAddress:target: (in > category 'inline cacheing') ----- > rewriteITypeBranchAtAddress: mcpc target: newTarget > + | newDisplacement oldInstruction newInstruction | > + newDisplacement := newTarget - (mcpc + 4). "Displacement is > relative to delay slot." > + newDisplacement := newDisplacement >> 2. "Displacement is in > words." > - | newDisplacement oldInstruction newInstruction | > - newDisplacement := newTarget - (mcpc - 4). "Displacement relative > to delay slot" > - newDisplacement := newDisplacement >> 2. > > self assert: (newDisplacement between: -16r8000 and: 16r7FFF). > newDisplacement < 0 > ifTrue: [newDisplacement := newDisplacement + 16r10000] > ifFalse: [newDisplacement := newDisplacement]. > self assert: (newDisplacement between: 0 and: 16rFFFF). > > oldInstruction := objectMemory longAt: mcpc. > newInstruction := (oldInstruction bitAnd: 16rFFFF0000) bitOr: > newDisplacement. > > objectMemory longAt: mcpc put: newInstruction.! > > Item was added: > + ----- Method: CogMIPSELCompiler>>rewriteInlineCacheTag:at: (in category > 'inline cacheing') ----- > + rewriteInlineCacheTag: cacheTag at: callSiteReturnAddress > + "Rewrite an inline cache with a new tag. This variant is used > + by the garbage collector." > + > + "MoveCwR ClassReg selectorIndex/expectedClass > + Call: unlinked send stub/expectedTarget > + Push ReceiverResult <-- callSiteReturnAddress" > + > + "lui s3, selector/tagHigh > + ori s3, s3, selector/tagLow > + lui t9, stub/targetHigh > + ori t9, t9, stub/targetLow > + jalr t9 > + nop (delay slot) > + ... <-- callSiteReturnAddress" > + > + <var: #callSiteReturnAddress type: #usqInt> > + <var: #callTargetAddress type: #usqInt> > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 24) = > LUI. > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 20) = > ORI. > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = > LUI. > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = > ORI. > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = > SPECIAL. > + self assert: (self functionAtAddress: callSiteReturnAddress - 8) = > JALR. > + self assert: (objectMemory longAt: callSiteReturnAddress - 4) = > self nop. > + "cogit disassembleFrom: callSiteReturnAddress - 24 to: > callSiteReturnAddress." > + > + self literalAtAddress: callSiteReturnAddress - 20 put: cacheTag. > + > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 24) = > LUI. > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 20) = > ORI. > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = > LUI. > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = > ORI. > + self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = > SPECIAL. > + self assert: (self functionAtAddress: callSiteReturnAddress - 8) = > JALR. > + self assert: (objectMemory longAt: callSiteReturnAddress - 4) = > self nop. > + "cogit disassembleFrom: callSiteReturnAddress - 24 to: > callSiteReturnAddress."! > > Item was changed: > ----- Method: CogMIPSELCompiler>>storeLiteral:beforeFollowingAddress: > (in category 'inline cacheing') ----- > storeLiteral: literal beforeFollowingAddress: followingAddress > "Rewrite the long constant loaded by a MoveCwR or PushCwR before > the given address" > - | lastOpcode lastFunction oriAddress | > self flag: #bogus. "The caller ought to know what it is patching, > and this should be split into separate methods with stricter checking." > > + "Cmp/MoveCwR > + pc-8 lui rx, uper > + pc-4 ori rx, rx, lower" > + (self opcodeAtAddress: followingAddress - 4) = ORI ifTrue: > + [^self literalAtAddress: followingAddress - 4 put: > literal]. > + > + "PushCw > + pc-16 lui at, upper > + pc-12 ori at, at, lower > + pc-8 addiu sp, sp, -4 > + pc-4 sw at, 0(sp)" > + ((self opcodeAtAddress: followingAddress - 4) = SW and: > + [(self opcodeAtAddress: followingAddress - 8) = ADDIU]) > ifTrue: > + [^self literalAtAddress: followingAddress - 12 > put: literal]. > + > + self unreachable. > + ^0! > - lastOpcode := self opcodeAtAddress: followingAddress - 4. > - lastFunction := self functionAtAddress: followingAddress - 4. > - oriAddress := 0. > - lastOpcode = ORI ifTrue: [oriAddress := followingAddress - 4]. > - lastOpcode = ADDIU ifTrue: [oriAddress := followingAddress - 16]. > - lastOpcode = SPECIAL ifTrue: [lastFunction = SUBU ifTrue: > [oriAddress := followingAddress - 8]]. > - self assert: oriAddress ~= 0. > - ^self literalAtAddress: oriAddress put: literal! > > Item was changed: > ----- Method: StackInterpreter>>followForwardingPointersInScheduler (in > category 'object memory support') ----- > followForwardingPointersInScheduler > | schedAssoc sched procLists | > schedAssoc := objectMemory splObj: SchedulerAssociation. > "the GC follows pointers in the special objects array for us." > self assert: (objectMemory isForwarded: schedAssoc) not. > > "Make sure the active process has been followed." > + objectMemory followForwardedObjectFields: schedAssoc toDepth: 1. > - self followForwardedObjectFields: schedAssoc toDepth: 1. > > sched := objectMemory fetchPointer: ValueIndex ofObject: > schedAssoc. > > procLists := objectMemory followObjField: ProcessListsIndex > ofObject: sched. > > "Follow all links in the process list to ensure the lists are > valid." > 0 to: (objectMemory numSlotsOf: procLists) - 1 do: > [:i| | list first last next | > list := objectMemory followObjField: i ofObject: procLists. > first := objectMemory followObjField: FirstLinkIndex > ofObject: list. > last := objectMemory followObjField: LastLinkIndex > ofObject: list. > [first ~= last] whileTrue: > [next := objectMemory followObjField: > NextLinkIndex ofObject: first. > first := next]] > ! > > -- _,,,^..^,,,_ best, Eliot

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VM Maker: VMMaker.oscog-eem.1607.mcz
by commits＠source.squeak.org 17 Dec '15

17 Dec '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1607.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1607 Author: eem Time: 17 December 2015, 12:19:52.584 am UUID: 5f0a0a13-5e92-417b-8351-729d7cf5aead Ancestors: VMMaker.oscog-eem.1606 Cogit: generateCaptureCStackPointers: must establish the VarBaseReg before accessing any of the stack pointer variables. =============== Diff against VMMaker.oscog-eem.1606 =============== Item was changed: ----- Method: Cogit>>generateCaptureCStackPointers: (in category 'initialization') ----- generateCaptureCStackPointers: captureFramePointer "Generate the routine that writes the current values of the C frame and stack pointers into variables. These are used to establish the C stack in trampolines back into the C run-time. This is a presumptuous quick hack for x86. It is presumptuous for two reasons. Firstly the system's frame and stack pointers may differ from those we use in generated code, e.g. on register-rich RISCs. Secondly the ABI may not support a simple frameless call as written here (for example 128-bit stack alignment on Mac OS X)." | startAddress | <inline: false> self allocateOpcodes: 32 bytecodes: 0. startAddress := methodZoneBase. + backEnd maybeEstablishVarBase. "Must happen first; value may be used in accessing any of the following addresses" captureFramePointer ifTrue: [self MoveR: FPReg Aw: self cFramePointerAddress]. "Capture the stack pointer prior to the call." backEnd leafCallStackPointerDelta = 0 ifTrue: [self MoveR: SPReg Aw: self cStackPointerAddress] ifFalse: [self MoveR: SPReg R: TempReg. self AddCq: backEnd leafCallStackPointerDelta R: TempReg. self MoveR: TempReg Aw: self cStackPointerAddress]. self RetN: 0. self outputInstructionsForGeneratedRuntimeAt: startAddress. processor flushICacheFrom: startAddress asUnsignedInteger to: methodZoneBase asUnsignedInteger. self recordGeneratedRunTime: 'ceCaptureCStackPointers' address: startAddress. ceCaptureCStackPointers := self cCoerceSimple: startAddress to: #'void (*)(void)'!

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VM Maker: VMMaker.oscog-eem.1606.mcz
by commits＠source.squeak.org 17 Dec '15

17 Dec '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1606.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1606 Author: eem Time: 17 December 2015, 12:08:45.954 am UUID: 1efb5990-cfe7-420e-ae74-f40197a68c68 Ancestors: VMMaker.oscog-rmacnak.1605 x86 Cogit: Fix order of cmp in ArithCwR. Extend var base range to 1Mb =============== Diff against VMMaker.oscog-rmacnak.1605 =============== Item was changed: ----- Method: CogInLineLiteralsX64Compiler>>concretizeArithCwR: (in category 'generate machine code') ----- concretizeArithCwR: x64opcode + | value reg reverse | - | value reg | value := operands at: 0. reg := self concreteRegister: (operands at: 1). + reverse := x64opcode = 16r85 or: [x64opcode = 16r39]. "Tst & Cmp; backwards" machineCode at: 0 put: (self rexR: ConcreteRISCTempReg x: 0 b: ConcreteRISCTempReg); at: 1 put: 16rB8 + (ConcreteRISCTempReg bitAnd: 7); at: 2 put: (value bitAnd: 16rFF); at: 3 put: (value >> 8 bitAnd: 16rFF); at: 4 put: (value >> 16 bitAnd: 16rFF); at: 5 put: (value >> 24 bitAnd: 16rFF); at: 6 put: (value >> 32 bitAnd: 16rFF); at: 7 put: (value >> 40 bitAnd: 16rFF); at: 8 put: (value >> 48 bitAnd: 16rFF); at: 9 put: (value >> 56 bitAnd: 16rFF); + at: 10 put: (reverse - at: 10 put: (x64opcode = 16r85 "Tst; backwards" ifTrue: [self rexR: ConcreteRISCTempReg x: 0 b: reg] ifFalse: [self rexR: reg x: 0 b: ConcreteRISCTempReg]); at: 11 put: x64opcode; + at: 12 put: (reverse - at: 12 put: (x64opcode = 16r85 "Tst; backwards" ifTrue: [self mod: ModReg RM: reg RO: ConcreteRISCTempReg] ifFalse: [self mod: ModReg RM: ConcreteRISCTempReg RO: reg]). ^machineCodeSize := 13! Item was changed: ----- Method: CogX64Compiler>>concretizeArithCqRWithRO:raxOpcode: (in category 'generate machine code') ----- concretizeArithCqRWithRO: regOpcode raxOpcode: raxOpcode "Will get inlined into concretizeAt: switch." <inline: false> | value reg | value := operands at: 0. reg := self concreteRegister: (operands at: 1). machineCode at: 0 put: (self rexR: 0 x: 0 b: reg). (self isQuick: value) ifTrue: [machineCode at: 1 put: 16r83; at: 2 put: (self mod: ModReg RM: reg RO: regOpcode); at: 3 put: (value bitAnd: 16rFF). ^machineCodeSize := 4]. (self isSignExtendedFourByteValue: value) ifTrue: [reg = RAX ifTrue: [machineCode at: 1 put: raxOpcode; at: 2 put: (value bitAnd: 16rFF); at: 3 put: (value >> 8 bitAnd: 16rFF); at: 4 put: (value >> 16 bitAnd: 16rFF); at: 5 put: (value >> 24 bitAnd: 16rFF). ^machineCodeSize := 6]. machineCode at: 1 put: 16r81; at: 2 put: (self mod: ModReg RM: reg RO: regOpcode); at: 3 put: (value bitAnd: 16rFF); at: 4 put: (value >> 8 bitAnd: 16rFF); at: 5 put: (value >> 16 bitAnd: 16rFF); at: 6 put: (value >> 24 bitAnd: 16rFF). ^machineCodeSize := 7]. + ^self concretizeArithCwR: (raxOpcode = 16r3D "Cmp" ifTrue: [16r39] ifFalse: [raxOpcode - 2])! - ^self concretizeArithCwR: (raxOpcode = 16r3D ifTrue: [16r39] ifFalse: [raxOpcode - 2])! Item was changed: ----- Method: CogX64Compiler>>isAddressRelativeToVarBase: (in category 'testing') ----- isAddressRelativeToVarBase: varAddress <inline: true> <var: #varAddress type: #usqInt> + "Support for addressing variables off the dedicated VarBaseReg. Allow for 1Mb of variables. - "Support for addressing variables off the dedicated VarBaseReg. Allow for 16k of variables. The x64 supports 32-bit offsets, but we choose not to address everything from VarBaseReg." ^varAddress notNil and: [varAddress >= cogit varBaseAddress + and: [varAddress - cogit varBaseAddress < (1 << 20)]]! - and: [varAddress - cogit varBaseAddress < (1 << 14)]]!

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VM Maker: Cog-eem.310.mcz
by commits＠source.squeak.org 17 Dec '15

17 Dec '15

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.310.mcz ==================== Summary ==================== Name: Cog-eem.310 Author: eem Time: 17 December 2015, 12:05:25.428 am UUID: 1b369b07-853b-4937-8a11-b48bef3e5cae Ancestors: Cog-eem.309 Fix or implement Move ALOb/ObAL/AXOv/OvAX error handling for x64. I had copied the opcodes wrongly from x64. =============== Diff against Cog-eem.309 =============== Item was changed: ----- Method: BochsX64Alien class>>initialize (in category 'class initialization') ----- initialize "BochsX64Alien initialize" | it | it := self basicNew. OpcodeExceptionMap := Array new: 256 withAll: #handleExecutionPrimitiveFailureAt:in:rex:. OpcodeExceptionMap + at: 1 + it callOpcode put: #handleCallFailureAt:in:rex:; + at: 1 + it jmpOpcode put: #handleJmpFailureAt:in:rex:; + at: 1 + it retOpcode put: #handleRetFailureAt:in:rex:; - at: 1 + it callOpcode put: #handleCallFailureAt:in:rex:; - at: 1 + it jmpOpcode put: #handleJmpFailureAt:in:rex:; - at: 1 + it retOpcode put: #handleRetFailureAt:in:rex:; at: 1 + it movALObOpcode put: #handleMovALObFailureAt:in:rex:; + at: 1 + it movAXOvOpcode put: #handleMovAXOvFailureAt:in:rex:; at: 1 + it movObALOpcode put: #handleMovObALFailureAt:in:rex:; + at: 1 + it movOvAXOpcode put: #handleMovOvAXFailureAt:in:rex:; at: 1 + it movGvEvOpcode put: #handleMovGvEvFailureAt:in:rex:; at: 1 + it movEvGvOpcode put: #handleMovEvGvFailureAt:in:rex:; at: 1 + it movGbEbOpcode put: #handleMovGbEbFailureAt:in:rex:; at: 1 + it movEbGbOpcode put: #handleMovEbGbFailureAt:in:rex:; at: 1 + 16rFF put: #handleGroup5FailureAt:in:rex:. "Table A6 One-Byte and Two-Byte Opcode ModRM Extensions" ExtendedOpcodeExceptionMap := Array new: 256 withAll: #handleExecutionPrimitiveFailureAt:in:rex:. ExtendedOpcodeExceptionMap at: 1 + it movGvEbOpcode put: #handleMovGvEbFailureAt:in:rex:! Item was changed: ----- Method: BochsX64Alien>>handleMovALObFailureAt:in:rex: (in category 'error handling') ----- handleMovALObFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" rex: rexByteOrNil "<Integer|nil>" + "Convert an execution primitive failure for a read into al into a ProcessorSimulationTrap signal." - "Convert an execution primitive failure for a read into rax/eax into a ProcessorSimulationTrap signal." rexByteOrNil ifNotNil: + [self assert: rexByteOrNil = 16r48. + ^(ProcessorSimulationTrap - [^(ProcessorSimulationTrap pc: pc nextpc: pc + 10 address: (memoryArray unsignedLong64At: pc + 3) type: #read + accessor: #al:) - accessor: #rax:) signal]. ^(ProcessorSimulationTrap pc: pc nextpc: pc + 5 address: (memoryArray unsignedLongAt: pc + 2) type: #read + accessor: #al:) - accessor: #eax:) signal! Item was added: + ----- Method: BochsX64Alien>>handleMovAXOvFailureAt:in:rex: (in category 'error handling') ----- + handleMovAXOvFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" rex: rexByteOrNil "<Integer|nil>" + "Convert an execution primitive failure for a read into rax/eax into a ProcessorSimulationTrap signal." + rexByteOrNil ifNotNil: + [self assert: rexByteOrNil = 16r48. + ^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 10 + address: (memoryArray unsignedLong64At: pc + 3) + type: #read + accessor: #rax:) + signal]. + ^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 5 + address: (memoryArray unsignedLongAt: pc + 2) + type: #read + accessor: #eax:) + signal! Item was changed: ----- Method: BochsX64Alien>>handleMovObALFailureAt:in:rex: (in category 'error handling') ----- handleMovObALFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" rex: rexByteOrNil "<Integer|nil>" + "Convert an execution primitive failure for a write of al into a ProcessorSimulationTrap signal." + self assert: rexByteOrNil = 16r48. - "Convert an execution primitive failure for a write of eax into a ProcessorSimulationTrap signal." - self shouldBeImplemented. ^(ProcessorSimulationTrap pc: pc + nextpc: pc + 10 + address: (memoryArray unsignedLong64At: pc + 3) - nextpc: pc + 5 - address: (memoryArray unsignedLongAt: pc + 2 bigEndian: false) type: #write + accessor: #al) - accessor: #eax) signal! Item was added: + ----- Method: BochsX64Alien>>handleMovOvAXFailureAt:in:rex: (in category 'error handling') ----- + handleMovOvAXFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" rex: rexByteOrNil "<Integer|nil>" + "Convert an execution primitive failure for a write of rax into a ProcessorSimulationTrap signal." + self assert: rexByteOrNil = 16r48. + ^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 10 + address: (memoryArray unsignedLong64At: pc + 3) + type: #write + accessor: #rax) + signal! Item was changed: ----- Method: BochsX64Alien>>movALObOpcode (in category 'opcodes') ----- movALObOpcode "[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z. table A2, pA7" + ^16rA0! - ^16rA1! Item was added: + ----- Method: BochsX64Alien>>movAXOvOpcode (in category 'opcodes') ----- + movAXOvOpcode + "[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z. + table A2, pA7" + ^16rA1! Item was changed: ----- Method: BochsX64Alien>>movObALOpcode (in category 'opcodes') ----- movObALOpcode "[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z. table A2, pA7" + ^16rA2! - ^16rA3! Item was added: + ----- Method: BochsX64Alien>>movOvAXOpcode (in category 'opcodes') ----- + movOvAXOpcode + "[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z. + table A2, pA7" + ^16rA3!

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VM Maker: VMMaker.oscog-rmacnak.1605.mcz
by commits＠source.squeak.org 17 Dec '15

17 Dec '15

Ryan Macnak uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-rmacnak.1605.mcz ==================== Summary ==================== Name: VMMaker.oscog-rmacnak.1605 Author: rmacnak Time: 16 December 2015, 10:38:55.921 pm UUID: d5c6ef8e-2868-4f0a-8ff7-ae4bfeb5e37e Ancestors: VMMaker.oscog-eem.1604 MIPS: Get compiled VM up to ceCaptureCStackPointers, crashing because no one setup VarBaseReg. Dumb luck that the address has been out of VarBase range on ARM so far. Implement identifyingPredefinedMacros and therefore start generating C for MIPSEL alongside IA32 and ARMv5. Implement machineCodeDeclaration so our instructions don't get truncated. (Though oddly enough they're not totally incomprehensible because the function for many instructions in the low bits.) Optimistically copy I-cache flush implementation from ARM. Rename break: to avoid the C reserved word since Slang doesn't do it for us. Also don't rename it _break: because `#_break: numArgs` is wrong in Squeak. Rename various shadowing temps since Slang warns it doesn't make sure they refer to the same thing in C as they did in Smalltalk when inlining. Remove various simulation-only code. Add stubs for various unreachable code to make the C compiler happy. =============== Diff against VMMaker.oscog-eem.1604 =============== Item was added: + ----- Method: CogMIPSELCompiler class>>identifyingPredefinedMacros (in category 'translation') ----- + identifyingPredefinedMacros + ^#('__MIPSEL__')! Item was added: + ----- Method: CogMIPSELCompiler class>>machineCodeDeclaration (in category 'translation') ----- + machineCodeDeclaration + "Answer the declaration for the machineCode array." + ^{#'unsigned long'. '[', self basicNew machineCodeWords printString, ']'}! Item was removed: - ----- Method: CogMIPSELCompiler>>break: (in category 'encoding - control') ----- - break: code - self assert: (code between: 0 and: 16rFFFFF). - ^(code << 6) bitOr: BREAK! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrLongEqualRR (in category 'generate machine code - concretize') ----- concretizeBrLongEqualRR + | jumpTargetInstruction jumpTargetAddr leftReg rightReg | + <var: #jumpTargetInstruction type: #'AbstractInstruction *'> + jumpTargetInstruction := self longJumpTargetAddress. - | jumpTarget leftReg rightReg | - <var: #jumpTarget type: #'AbstractInstruction *'> - jumpTarget := self longJumpTargetAddress. self flag: #todo. "Check not crossing 256MB block." + jumpTargetAddr := jumpTargetInstruction asUnsignedInteger bitAnd: 16rFFFFFFF. - jumpTarget := jumpTarget bitAnd: 16rFFFFFFF. leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). self machineCodeAt: 0 put: (self bneR: leftReg R: rightReg offset: 12). self machineCodeAt: 4 put: (self nop). "Delay slot" + self machineCodeAt: 8 put: (self jA: jumpTargetAddr). - self machineCodeAt: 8 put: (self jA: jumpTarget). self machineCodeAt: 12 put: self nop. "Delay slot" ^machineCodeSize := 16! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrLongNotEqualRR (in category 'generate machine code - concretize') ----- concretizeBrLongNotEqualRR + | jumpTargetInstruction jumpTargetAddr leftReg rightReg | + <var: #jumpTargetInstruction type: #'AbstractInstruction *'> + jumpTargetInstruction := self longJumpTargetAddress. - | jumpTarget leftReg rightReg | - <var: #jumpTarget type: #'AbstractInstruction *'> - jumpTarget := self longJumpTargetAddress. self flag: #todo. "Check not crossing 256MB block." + jumpTargetAddr := jumpTargetInstruction asUnsignedInteger bitAnd: 16rFFFFFFF. - jumpTarget := jumpTarget bitAnd: 16rFFFFFFF. leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). self machineCodeAt: 0 put: (self beqR: leftReg R: rightReg offset: 12). self machineCodeAt: 4 put: (self nop). "Delay slot" + self machineCodeAt: 8 put: (self jA: jumpTargetAddr). - self machineCodeAt: 8 put: (self jA: jumpTarget). self machineCodeAt: 12 put: self nop. "Delay slot" ^machineCodeSize := 16! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeCallFull (in category 'generate machine code - concretize') ----- concretizeCallFull + | jumpTargetInstruction jumpTargetAddr | + <var: #jumpTargetInstruction type: #'AbstractInstruction *'> + jumpTargetInstruction := self longJumpTargetAddress. + jumpTargetAddr := jumpTargetInstruction asUnsignedInteger. + self machineCodeAt: 0 put: (self luiR: TargetReg C: (self high16BitsOf: jumpTargetAddr)). + self machineCodeAt: 4 put: (self oriR: TargetReg R: TargetReg C: (self low16BitsOf: jumpTargetAddr)). - | jumpTarget | - <var: #jumpTarget type: #'AbstractInstruction *'> - jumpTarget := self longJumpTargetAddress. - self machineCodeAt: 0 put: (self luiR: TargetReg C: (self high16BitsOf: jumpTarget)). - self machineCodeAt: 4 put: (self oriR: TargetReg R: TargetReg C: (self low16BitsOf: jumpTarget)). self machineCodeAt: 8 put: (self jalR: TargetReg). self machineCodeAt: 12 put: self nop. "Delay slot" ^machineCodeSize := 16! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeJumpFull (in category 'generate machine code - concretize') ----- concretizeJumpFull + | jumpTargetInstruction jumpTargetAddr | + <var: #jumpTargetInstruction type: #'AbstractInstruction *'> + jumpTargetInstruction := self longJumpTargetAddress. + jumpTargetAddr := jumpTargetInstruction asUnsignedInteger. + self machineCodeAt: 0 put: (self luiR: TargetReg C: (self high16BitsOf: jumpTargetAddr)). + self machineCodeAt: 4 put: (self oriR: TargetReg R: TargetReg C: (self low16BitsOf: jumpTargetAddr)). - | jumpTarget | - <var: #jumpTarget type: #'AbstractInstruction *'> - jumpTarget := self longJumpTargetAddress. - self machineCodeAt: 0 put: (self luiR: TargetReg C: (self high16BitsOf: jumpTarget)). - self machineCodeAt: 4 put: (self oriR: TargetReg R: TargetReg C: (self low16BitsOf: jumpTarget)). self machineCodeAt: 8 put: (self jR: TargetReg). self machineCodeAt: 12 put: self nop. "Delay slot" ^machineCodeSize := 16! Item was changed: ----- Method: CogMIPSELCompiler>>concretizePrefetchAw (in category 'generate machine code - concretize') ----- concretizePrefetchAw + | addressOperand | + addressOperand := operands at: 0. + self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: addressOperand)). + self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: addressOperand)). - | address | - address := operands at: 0. - self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: address)). - self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: address)). self machineCodeAt: 8 put: (self prefR: AT offset: 0 hint: HintLoad). ^machineCodeSize := 12! Item was added: + ----- Method: CogMIPSELCompiler>>concretizeUnimplemented (in category 'generate machine code - concretize') ----- + concretizeUnimplemented + self error: 'Unimplemented RTL instruction'. + ^0! Item was changed: ----- Method: CogMIPSELCompiler>>dispatchConcretize (in category 'generate machine code') ----- dispatchConcretize "Attempt to generate concrete machine code for the instruction at address. This is the inner dispatch of concretizeAt: actualAddress which exists only to get around the branch size limits in the SqueakV3 (blue book derived) bytecode set." <returnTypeC: #void> opcode caseOf: { [BrEqualRR] -> [^self concretizeBrEqualRR]. [BrNotEqualRR] -> [^self concretizeBrNotEqualRR]. [BrUnsignedLessRR] -> [^self concretizeBrUnsignedLessRR]. [BrUnsignedLessEqualRR] -> [^self concretizeBrUnsignedLessEqualRR]. [BrUnsignedGreaterRR] -> [^self concretizeBrUnsignedGreaterRR]. [BrUnsignedGreaterEqualRR] -> [^self concretizeBrUnsignedGreaterEqualRR]. [BrSignedLessRR] -> [^self concretizeBrSignedLessRR]. [BrSignedLessEqualRR] -> [^self concretizeBrSignedLessEqualRR]. [BrSignedGreaterRR] -> [^self concretizeBrSignedGreaterRR]. [BrSignedGreaterEqualRR] -> [^self concretizeBrSignedGreaterEqualRR]. [BrLongEqualRR] -> [^self concretizeBrLongEqualRR]. [BrLongNotEqualRR] -> [^self concretizeBrLongNotEqualRR]. + [MulRR] -> [^self concretizeUnimplemented]. - [MulRR] -> [^self concretizeMulRR]. [DivRR] -> [^self concretizeDivRR]. [MoveLowR] -> [^self concretizeMoveLowR]. [MoveHighR] -> [^self concretizeMoveHighR]. "Noops & Pseudo Ops" [Label] -> [^self concretizeLabel]. [AlignmentNops] -> [^self concretizeAlignmentNops]. [Fill32] -> [^self concretizeFill32]. [Nop] -> [^self concretizeNop]. "Control" [Call] -> [^self concretizeCall]. "call code within code space" [CallFull] -> [^self concretizeCallFull]. "call code anywhere in address space" [JumpR] -> [^self concretizeJumpR]. [JumpFull] -> [^self concretizeJumpFull]."jump within address space" [JumpLong] -> [^self concretizeJumpLong]."jumps witihn code space" [JumpLongZero] -> [^self concretizeJumpLongZero]. [JumpLongNonZero] -> [^self concretizeJumpLongNonZero]. [Jump] -> [^self concretizeJump]. [JumpZero] -> [^self concretizeJumpZero]. [JumpNonZero] -> [^self concretizeJumpNonZero]. [JumpNegative] -> [^self concretizeUnimplemented]. [JumpNonNegative] -> [^self concretizeUnimplemented]. [JumpOverflow] -> [^self concretizeJumpOverflow]. [JumpNoOverflow] -> [^self concretizeJumpNoOverflow]. [JumpCarry] -> [^self concretizeUnimplemented]. [JumpNoCarry] -> [^self concretizeUnimplemented]. [JumpLess] -> [^self concretizeJumpSignedLessThan]. [JumpGreaterOrEqual] -> [^self concretizeJumpSignedGreaterEqual]. [JumpGreater] -> [^self concretizeJumpSignedGreaterThan]. [JumpLessOrEqual] -> [^self concretizeJumpSignedLessEqual]. [JumpBelow] -> [^self concretizeJumpUnsignedLessThan]. [JumpAboveOrEqual] -> [^self concretizeJumpUnsignedGreaterEqual]. [JumpAbove] -> [^self concretizeJumpUnsignedGreaterThan]. [JumpBelowOrEqual] -> [^self concretizeJumpUnsignedLessEqual]. [JumpFPEqual] -> [^self concretizeUnimplemented]. [JumpFPNotEqual] -> [^self concretizeUnimplemented]. [JumpFPLess] -> [^self concretizeUnimplemented]. [JumpFPGreaterOrEqual] -> [^self concretizeUnimplemented]. [JumpFPGreater] -> [^self concretizeUnimplemented]. [JumpFPLessOrEqual] -> [^self concretizeUnimplemented]. [JumpFPOrdered] -> [^self concretizeUnimplemented]. [JumpFPUnordered] -> [^self concretizeUnimplemented]. [RetN] -> [^self concretizeRetN]. [Stop] -> [^self concretizeStop]. "Arithmetic" [AddCqR] -> [^self concretizeAddCqR]. [AndCqR] -> [^self concretizeAndCqR]. [AndCqRR] -> [^self concretizeAndCqRR]. [CmpCqR] -> [^self concretizeCmpCqR]. [OrCqR] -> [^self concretizeOrCqR]. [SubCqR] -> [^self concretizeSubCqR]. [TstCqR] -> [^self concretizeTstCqR]. + [XorCqR] -> [^self concretizeUnimplemented]. - [XorCqR] -> [^self concretizeXorCqR]. [AddCwR] -> [^self concretizeAddCwR]. [AndCwR] -> [^self concretizeAndCwR]. [CmpCwR] -> [^self concretizeCmpCwR]. [OrCwR] -> [^self concretizeOrCwR]. [SubCwR] -> [^self concretizeSubCwR]. [XorCwR] -> [^self concretizeXorCwR]. [AddRR] -> [^self concretizeAddRR]. [AndRR] -> [^self concretizeAndRR]. [CmpRR] -> [^self concretizeCmpRR]. [OrRR] -> [^self concretizeOrRR]. [SubRR] -> [^self concretizeSubRR]. [XorRR] -> [^self concretizeXorRR]. [AddRdRd] -> [^self concretizeUnimplemented]. [CmpRdRd] -> [^self concretizeUnimplemented]. [DivRdRd] -> [^self concretizeUnimplemented]. [MulRdRd] -> [^self concretizeUnimplemented]. [SubRdRd] -> [^self concretizeUnimplemented]. [SqrtRd] -> [^self concretizeUnimplemented]. [NegateR] -> [^self concretizeNegateR]. [LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR]. [ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR]. [LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR]. [LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR]. [ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR]. [LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR]. [LogicalShiftRightRR] -> [^self concretizeLogicalShiftRightRR]. "Data Movement" [MoveCqR] -> [^self concretizeMoveCqR]. [MoveCwR] -> [^self concretizeMoveCwR]. [MoveRR] -> [^self concretizeMoveRR]. [MoveAwR] -> [^self concretizeMoveAwR]. [MoveRAw] -> [^self concretizeMoveRAw]. [MoveAbR] -> [^self concretizeMoveAbR]. [MoveRAb] -> [^self concretizeMoveRAb]. [MoveMbrR] -> [^self concretizeMoveMbrR]. + [MoveRMbr] -> [^self concretizeUnimplemented]. - [MoveRMbr] -> [^self concretizeRMbr]. [MoveM16rR] -> [^self concretizeMoveM16rR]. + [MoveM64rRd] -> [^self concretizeUnimplemented]. - [MoveM64rRd] -> [^self concretizeM64rRd]. [MoveMwrR] -> [^self concretizeMoveMwrR]. [MoveXbrRR] -> [^self concretizeMoveXbrRR]. [MoveRXbrR] -> [^self concretizeMoveRXbrR]. [MoveXwrRR] -> [^self concretizeMoveXwrRR]. [MoveRXwrR] -> [^self concretizeMoveRXwrR]. [MoveRMwr] -> [^self concretizeMoveRMwr]. + [MoveRdM64r] -> [^self concretizeUnimplemented]. - [MoveRdM64r] -> [^self concretizeRdM64r]. [PopR] -> [^self concretizePopR]. [PushR] -> [^self concretizePushR]. [PushCq] -> [^self concretizePushCq]. [PushCw] -> [^self concretizePushCw]. [PrefetchAw] -> [^self concretizePrefetchAw]. [AddCheckOverflowCqR] -> [^self concretizeAddCheckOverflowCqR]. [AddCheckOverflowRR] -> [^self concretizeAddCheckOverflowRR]. [SubCheckOverflowCqR] -> [^self concretizeSubCheckOverflowCqR]. [SubCheckOverflowRR] -> [^self concretizeSubCheckOverflowRR]. [MulCheckOverflowRR] -> [^self concretizeMulCheckOverflowRR]. "Conversion" [ConvertRRd] -> [^self concretizeUnimplemented]}! Item was added: + ----- Method: CogMIPSELCompiler>>flushICacheFrom:to: (in category 'inline cacheing') ----- + flushICacheFrom: startAddress "<Integer>" to: endAddress "<Integer>" + <cmacro: '(me,startAddress,endAddress) __clear_cache((char*) startAddress, (char*) (endAddress ))'> + "On ARM we almost certainly need to flush and wash hands. On linux we use __clear_cache (see http://community.arm.com/groups/processors/blog/2010/02/17/caches-and-self-… for a decent example) and remember that the end address is *exclusive* so we can just use the end address passed in since it is always the byte after the actual last one needing flushing" + self halt: #ceFlushICache! Item was added: + ----- Method: CogMIPSELCompiler>>genLoadCStackPointer (in category 'smalltalk calling convention') ----- + genLoadCStackPointer + "Load the stack pointer register with that of the C stack, effecting + a switch to the C stack. Used when machine code calls into the + CoInterpreter run-time (e.g. to invoke interpreter primitives)." + cogit MoveAw: cogit cStackPointerAddress R: SPReg. + ^0! Item was added: + ----- Method: CogMIPSELCompiler>>genRestoreRegsExcept: (in category 'abi') ----- + genRestoreRegsExcept: abstractReg + "Restore the general purpose registers except for abstractReg for a trampoline call." + self flag: #bogus.! Item was added: + ----- Method: CogMIPSELCompiler>>getDefaultCogCodeSize (in category 'accessing') ----- + getDefaultCogCodeSize + "Return the default number of bytes to allocate for native code at startup. + The actual value can be set via vmParameterAt: and/or a preference in the ini file." + <inline: true> + ^1024 * 1536! Item was added: + ----- Method: CogMIPSELCompiler>>hasVarBaseRegister (in category 'testing') ----- + hasVarBaseRegister + "Answer if the processor has a dedicated callee-saved register to point to + the base of commonly-accessed variables." + <inline: true> + ^true "S6"! Item was changed: ----- Method: CogMIPSELCompiler>>isJumpAt: (in category 'testing') ----- isJumpAt: pc + "cogit disassembleFrom: pc to: pc + 4." - cogit disassembleFrom: pc to: pc + 4. (self opcodeAtAddress: pc) = J ifTrue: [^true]. + (self opcodeAtAddress: pc) = SPECIAL ifTrue: + [(self functionAtAddress: pc) = JR ifTrue: [^true]]. - (self opcodeAtAddress: pc) = SPECIAL ifTrue: [ - (self functionAtAddress: pc) = JR ifTrue: [^true]. - ]. (self opcodeAtAddress: pc) = BEQ ifTrue: [^true]. (self opcodeAtAddress: pc) = BNE ifTrue: [^true]. (self opcodeAtAddress: pc) = BLEZ ifTrue: [^true]. (self opcodeAtAddress: pc) = BGTZ ifTrue: [^true]. + (self opcodeAtAddress: pc) = REGIMM ifTrue: + [(self rtAtAddress: pc) = BLTZ ifTrue: [^true]. + (self rtAtAddress: pc) = BGEZ ifTrue: [^true]]. - (self opcodeAtAddress: pc) = REGIMM ifTrue: [ - (self rtAtAddress: pc) = BLTZ ifTrue: [^true]. - (self rtAtAddress: pc) = BGEZ ifTrue: [^true]. - ]. ^false! Item was changed: ----- Method: CogMIPSELCompiler>>itype:rs:rt:eitherImmediate: (in category 'encoding') ----- + itype: op rs: rs rt: rt eitherImmediate: signedImmediate - itype: opcode rs: rs rt: rt eitherImmediate: signedImmediate | unsignedImmediate | + self assert: (op between: 0 and: 63). - self assert: (opcode between: 0 and: 63). self assert: (rs between: 0 and: 31). self assert: (rt between: 0 and: 31). signedImmediate < 0 ifTrue: [unsignedImmediate := signedImmediate + 16r10000] ifFalse: [unsignedImmediate := signedImmediate]. self assert: (unsignedImmediate between: 0 and: 16rFFFF). + ^(((op << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: unsignedImmediate! - ^(((opcode << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: unsignedImmediate! Item was changed: ----- Method: CogMIPSELCompiler>>itype:rs:rt:signedImmediate: (in category 'encoding') ----- + itype: op rs: rs rt: rt signedImmediate: signedImmediate - itype: opcode rs: rs rt: rt signedImmediate: signedImmediate | unsignedImmediate | + self assert: (op between: 0 and: 63). - self assert: (opcode between: 0 and: 63). self assert: (rs between: 0 and: 31). self assert: (rt between: 0 and: 31). self assert: (signedImmediate between: -16r8000 and: 16r7FFF). signedImmediate < 0 ifTrue: [unsignedImmediate := signedImmediate + 16r10000] ifFalse: [unsignedImmediate := signedImmediate]. self assert: (unsignedImmediate between: 0 and: 16rFFFF). + ^(((op << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: unsignedImmediate! - ^(((opcode << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: unsignedImmediate! Item was changed: ----- Method: CogMIPSELCompiler>>itype:rs:rt:unsignedImmediate: (in category 'encoding') ----- + itype: op rs: rs rt: rt unsignedImmediate: immediate + self assert: (op between: 0 and: 63). - itype: opcode rs: rs rt: rt unsignedImmediate: immediate - self assert: (opcode between: 0 and: 63). self assert: (rs between: 0 and: 31). self assert: (rt between: 0 and: 31). self assert: (immediate between: 0 and: 16rFFFF). + ^(((op << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: immediate! - ^(((opcode << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: immediate! Item was changed: ----- Method: CogMIPSELCompiler>>jtype:target: (in category 'encoding') ----- + jtype: op target: target + self assert: (op between: 0 and: 63). + self assert: (target between: 0 and: 16r7FFFFFF). + ^(op << 26) bitOr: target! - jtype: opcode target: target - self assert: (opcode between: 0 and: 63). - self assert: (opcode between: 0 and: 16r7FFFFFF). - ^(opcode << 26) bitOr: target! Item was added: + ----- Method: CogMIPSELCompiler>>mipsbreak: (in category 'encoding - control') ----- + mipsbreak: code + self assert: (code between: 0 and: 16rFFFFF). + ^(code << 6) bitOr: BREAK! Item was changed: ----- Method: CogMIPSELCompiler>>noteFollowingConditionalBranch: (in category 'abstract instructions') ----- noteFollowingConditionalBranch: branch "Support for processors without condition codes, such as the MIPS. Answer the branch opcode. Modify the receiver and the branch to implement a suitable conditional branch that doesn't depend on condition codes being set by the receiver." <returnTypeC: #'AbstractInstruction *'> <var: #branch type: #'AbstractInstruction *'> | newBranchLeft newBranchOpcode newBranchRight | ((branch opcode = JumpOverflow) or: [branch opcode = JumpNoOverflow]) ifTrue: [^self noteFollowingOverflowBranch: branch]. newBranchOpcode := branch opcode caseOf: { [JumpZero] -> [BrEqualRR]. [JumpNonZero] -> [BrNotEqualRR]. [JumpBelow] -> [BrUnsignedLessRR]. [JumpBelowOrEqual] -> [BrUnsignedLessEqualRR]. [JumpAbove] -> [BrUnsignedGreaterRR]. [JumpAboveOrEqual] -> [BrUnsignedGreaterEqualRR]. [JumpLess] -> [BrSignedLessRR]. [JumpLessOrEqual] -> [BrSignedLessEqualRR]. [JumpGreater] -> [BrSignedGreaterRR]. [JumpGreaterOrEqual] -> [BrSignedGreaterEqualRR]. [JumpLongZero] -> [BrLongEqualRR]. [JumpLongNonZero] -> [BrLongNotEqualRR]. [JumpNegative] -> [BrSignedLessRR]. + } otherwise: [self unreachable. 0]. - } otherwise: [self unreachable]. opcode caseOf: { [BrEqualRR] -> ["I.e., two jumps after a compare." newBranchLeft := operands at: 1. newBranchRight := operands at: 2]. [BrUnsignedLessRR] -> ["I.e., two jumps after a compare." newBranchLeft := operands at: 1. newBranchRight := operands at: 2]. [CmpRR] -> [newBranchLeft := operands at: 1. newBranchRight := operands at: 0. opcode := Label]. [CmpCqR] -> [newBranchLeft := operands at: 1. newBranchRight := AT. opcode := MoveCqR. operands at: 1 put: AT]. [CmpCwR] -> [newBranchLeft := operands at: 1. newBranchRight := AT. opcode := MoveCwR. operands at: 1 put: AT]. [TstCqR] -> [newBranchLeft := Cmp. newBranchRight := ZR]. [AndCqR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [AndCqRR] -> [newBranchLeft := operands at: 2. newBranchRight := ZR]. [OrRR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [XorRR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [SubCwR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [SubCqR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [ArithmeticShiftRightCqR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. } otherwise: [self unreachable]. branch rewriteOpcode: newBranchOpcode with: newBranchLeft with: newBranchRight. ^branch! Item was changed: ----- Method: CogMIPSELCompiler>>noteFollowingOverflowBranch: (in category 'abstract instructions') ----- noteFollowingOverflowBranch: branch "Support for processors without condition codes, such as the MIPS. Answer the branch opcode. Modify the receiver and the branch to implement a suitable conditional branch that doesn't depend on condition codes being set by the receiver." <var: #branch type: #'AbstractInstruction *'> | newBranchOpcode | (opcode = MulRR) ifTrue: [opcode := MulCheckOverflowRR. newBranchOpcode := branch opcode caseOf: { [JumpOverflow] -> [BrNotEqualRR]. [JumpNoOverflow] -> [BrEqualRR]. + } otherwise: [self unreachable. 0]. - } otherwise: [self unreachable]. branch rewriteOpcode: newBranchOpcode with: OverflowTemp1 with: OverflowTemp2. ^branch]. opcode := opcode caseOf: { [AddCqR] -> [AddCheckOverflowCqR]. [AddRR] -> [AddCheckOverflowRR]. [SubCqR] -> [SubCheckOverflowCqR]. [SubRR] -> [SubCheckOverflowRR]. + } otherwise: [self unreachable. 0]. - } otherwise: [self unreachable]. newBranchOpcode := branch opcode caseOf: { [JumpOverflow] -> [BrSignedLessRR]. [JumpNoOverflow] -> [BrSignedGreaterEqualRR]. + } otherwise: [self unreachable. 0]. - } otherwise: [self unreachable]. branch rewriteOpcode: newBranchOpcode with: Overflow with: ZR. ^branch! Item was changed: ----- Method: CogMIPSELCompiler>>rewriteInlineCacheTag:at: (in category 'inline cacheing') ----- rewriteInlineCacheTag: cacheTag at: callSiteReturnAddress "Rewrite an inline cache with a new tag. This variant is used by the garbage collector." "MoveCwR ClassReg selectorIndex/expectedClass Call: unlinked send stub/expectedTarget Push ReceiverResult <-- callSiteReturnAddress" "lui s3, selector/tagHigh ori s3, s3, selector/tagLow lui t9, stub/targetHigh ori t9, t9, stub/targetLow jalr t9 nop (delay slot) ... <-- callSiteReturnAddress" <var: #callSiteReturnAddress type: #usqInt> - <var: #callTargetAddress type: #usqInt> self assert: (self opcodeAtAddress: callSiteReturnAddress - 24) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 20) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL. self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. "cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress." self literalAtAddress: callSiteReturnAddress - 20 put: cacheTag. self assert: (self opcodeAtAddress: callSiteReturnAddress - 24) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 20) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL. self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. "cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress."! Item was changed: ----- Method: CogMIPSELCompiler>>rewriteOpcode:with:with: (in category 'abstract instructions') ----- rewriteOpcode: anOpcode with: left with: right <inline: true> - self assert: anOpcode isInteger. - self assert: left isInteger. - self assert: right isInteger. - opcode := anOpcode. operands "0 is target" at: 1 put: left; at: 2 put: right! Item was added: + ----- Method: CogMIPSELCompiler>>rtAtAddress: (in category 'inline cacheing') ----- + rtAtAddress: mcpc + ^(objectMemory longAt: mcpc) >> 16 bitAnd: 31 + ! Item was changed: ----- Method: CogMIPSELCompiler>>rtype:rs:rt:rd:sa:funct: (in category 'encoding') ----- + rtype: op rs: rs rt: rt rd: rd sa: sa funct: funct + self assert: (op between: 0 and: 63). - rtype: opcode rs: rs rt: rt rd: rd sa: sa funct: funct - self assert: (opcode between: 0 and: 63). self assert: (rs between: 0 and: 31). self assert: (rt between: 0 and: 31). self assert: (rd between: 0 and: 31). self assert: (sa between: 0 and: 31). self assert: (funct between: 0 and: 63). + ^(((((op << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: (rd << 11)) bitOr: (sa << 6)) bitOr: funct! - ^(((((opcode << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: (rd << 11)) bitOr: (sa << 6)) bitOr: funct! Item was changed: ----- Method: CogMIPSELCompiler>>stop (in category 'encoding - control') ----- stop + ^self mipsbreak: 0! - ^self break: 0!

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Re: interleaving indexing has me scrambled
by Robert Withers 17 Dec '15

17 Dec '15

God works in mysterious ways, doesn't he? Not that I had any intention of breaking it. Not what I am about. Well, perhaps it isn;t meant to be interleaved just now. Perhaps,,, we go into the future, togehter. peace, robert On 12/16/2015 11:59 PM, Robert Withers wrote: > I had to bail on this. I really don't understand what it is doing. sorry > it didn't deliver, hopefully I'll be able to get your back > > regards, > > robert > > On 12/16/2015 10:23 PM, Robert Withers wrote: >> In particular the tempIndex of the second scan goes out of range and I >> scratching my head. If anyone actually wants to look at how this method >> works and can help, awesome! :) >> >> best, >> robert >> >> >> >> --- >> >> interleave: symbols blockCount: blockCount >> >> | symbolsPerChunk table interleaved interleavedBlock fourChunk >> symbolsPerBlock | >> ((symbols size \\ 4) > 0) ifTrue: [self error: 'interleaving bytes >> size not a multiple of 4']. >> symbolsPerChunk := symbols size // blockCount. >> symbolsPerBlock := symbols size // (blockCount // 4). >> table := OrderedCollection new: 4 withAll: 0. >> table at: 1 put: (ByteArray new: symbolsPerChunk withAll: 0). >> table at: 2 put: (ByteArray new: symbolsPerChunk withAll: 0). >> table at: 3 put: (ByteArray new: symbolsPerChunk withAll: 0). >> table at: 4 put: (ByteArray new: symbolsPerChunk withAll: 0). >> interleavedBlock := ByteArray new: (symbols size / blockCount) >> withAll: 0. >> interleaved := ByteArray new: (symbols size + 1) withAll: 0. >> interleaved at: 1 put: blockCount. >> >> 0 to: blockCount - 1 do: [ :blockIndex | >> | end start | >> start := blockIndex * symbolsPerBlock + 1. >> end := (blockIndex + 1) * symbolsPerBlock. >> fourChunk := symbols copyFrom: start to: end. >> "first scan: bytes to populate the table" >> 0 to: 3 do: [ :chunkIndex | >> | chunk slice symbol | >> chunk := fourChunk copyFrom: (chunkIndex * symbolsPerChunk >> + 1) to: ((chunkIndex + 1) * symbolsPerChunk). >> 1 to: symbolsPerChunk do: [ :index | >> slice := table at: (chunkIndex + 1). >> symbol := chunk at: index. >> slice at: index put: symbol]]. >> "second scan: table to populate the interleaved bytes" >> 1 to: symbolsPerChunk do: [ :index | >> 0 to: 3 do: [ :chunkIndex | >> | localIndex offset tempIndex symbol | >> offset := symbolsPerBlock * blockIndex. >> tempIndex := index * 4 + chunkIndex - 3. >> localIndex := offset + tempIndex. >> symbol := (table at: (chunkIndex + 1)) at: index. >> interleavedBlock at: localIndex put: symbol]]. >> start := symbols size / blockCount * blockIndex + 1. >> end := symbols size / blockCount * blockIndex + >> interleavedBlock size. >> interleaved replaceFrom: (start + 1) to: (end + 1) with: >> interleavedBlock startingAt: 1]. >> ^ interleaved > -- . .. .. ^,^ best, robert

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VM Maker: VMMaker.oscog-eem.1604.mcz
by commits＠source.squeak.org 17 Dec '15

17 Dec '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1604.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1604 Author: eem Time: 16 December 2015, 7:23:41.075 pm UUID: 296b641e-1f4e-40ae-ae2a-ed66e94ab4e8 Ancestors: VMMaker.oscog-eem.1603 Cogit: Nuke incorrect uses of signedIntToLong on the results of callTargetFromReturnAddress: =============== Diff against VMMaker.oscog-eem.1603 =============== Item was changed: ----- Method: CogARMCompiler>>rewriteTransferAt:target: (in category 'inline cacheing') ----- rewriteTransferAt: callSiteReturnAddress target: callTargetAddress "Rewrite a call/jump instruction to call a different target. This variant is used to link PICs in ceSendMiss et al, and to rewrite call/jumps in CPICs. Answer the extent of the code change which is used to compute the range of the icache to flush." <var: #callSiteReturnAddress type: #usqInt> <var: #callTargetAddress type: #usqInt> | callDistance instr | "for debug - [cogit disassembleFrom: callSiteReturnAddress - 10 to: callSiteReturnAddress - 1]." false ifTrue: [self assert: callTargetAddress >= cogit minCallAddress] ifFalse: [callTargetAddress >= cogit minCallAddress ifFalse: [self error: 'linking callsite to invalid address']]. callDistance := (callTargetAddress - (callSiteReturnAddress + 8 "pc offset"- 4 "return offset")) signedIntToLong. self assert: (self isInImmediateJumpRange: callDistance). "we don't support long call updates, yet" instr := self instructionBeforeAddress: callSiteReturnAddress. self assert: ((self instructionIsB: instr) or: [self instructionIsBL: instr]). objectMemory longAt: (self instructionAddressBefore: callSiteReturnAddress) put: ((instr bitAnd: 16rFF000000) bitOr: (callDistance // 4 bitAnd: 16rFFFFFF)). + self assert: (self callTargetFromReturnAddress: callSiteReturnAddress) = callTargetAddress. - self assert: (self callTargetFromReturnAddress: callSiteReturnAddress) signedIntToLong = callTargetAddress. ^4! Item was changed: ----- Method: CogIA32Compiler>>rewriteInlineCacheAt:tag:target: (in category 'inline cacheing') ----- rewriteInlineCacheAt: callSiteReturnAddress tag: cacheTag target: callTargetAddress "Rewrite an inline cache to call a different target for a new tag. This variant is used to link unlinked sends in ceSend:to:numArgs: et al. Answer the extent of the code change which is used to compute the range of the icache to flush." <var: #callSiteReturnAddress type: #usqInt> <var: #callTargetAddress type: #usqInt> | callDistance | "self cCode: '' inSmalltalk: [cogit disassembleFrom: callSiteReturnAddress - 10 to: callSiteReturnAddress - 1]." false ifTrue: [self assert: callTargetAddress >= cogit minCallAddress] ifFalse: [callTargetAddress >= cogit minCallAddress ifFalse: [self error: 'linking callsite to invalid address']]. callDistance := (callTargetAddress - callSiteReturnAddress) signedIntToLong. objectMemory byteAt: callSiteReturnAddress - 1 put: (callDistance >> 24 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 2 put: (callDistance >> 16 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 3 put: (callDistance >> 8 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 4 put: (callDistance bitAnd: 16rFF); byteAt: callSiteReturnAddress - 6 put: (cacheTag >> 24 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 7 put: (cacheTag >> 16 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 8 put: (cacheTag >> 8 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 9 put: (cacheTag bitAnd: 16rFF). + self assert: (self callTargetFromReturnAddress: callSiteReturnAddress) = callTargetAddress. - self assert: (self callTargetFromReturnAddress: callSiteReturnAddress) signedIntToLong = callTargetAddress. "self cCode: '' inSmalltalk: [cogit disassembleFrom: callSiteReturnAddress - 10 to: callSiteReturnAddress - 1]." ^10! Item was changed: ----- Method: CogInLineLiteralsARMCompiler>>rewriteInlineCacheAt:tag:target: (in category 'inline cacheing') ----- rewriteInlineCacheAt: callSiteReturnAddress tag: cacheTag target: callTargetAddress "Rewrite an inline cache to call a different target for a new tag. This variant is used to link unlinked sends in ceSend:to:numArgs: et al. Answer the extent of the code change which is used to compute the range of the icache to flush." <var: #callSiteReturnAddress type: #usqInt> <var: #callTargetAddress type: #usqInt> | call callDistance | false ifTrue: [self assert: callTargetAddress >= cogit minCallAddress] ifFalse: [callTargetAddress >= cogit minCallAddress ifFalse: [self error: 'linking callsite to invalid address']]. callDistance := (callTargetAddress - (callSiteReturnAddress + 8 "pc offset"- 4 "return offset")) signedIntToLong. self assert: (self isInImmediateJumpRange: callDistance). "we don't support long call updates here" call := self bl: callDistance. objectMemory longAt: (self instructionAddressBefore: callSiteReturnAddress ) put: call. self insert32BitOperand: cacheTag into4InstructionsPreceding: (self instructionAddressBefore: callSiteReturnAddress ). + self assert: (self callTargetFromReturnAddress: callSiteReturnAddress) = callTargetAddress. - self assert: (self callTargetFromReturnAddress: callSiteReturnAddress) signedIntToLong = callTargetAddress. self assert: (self extract32BitOperandFrom4InstructionsPreceding: (self instructionAddressBefore: callSiteReturnAddress )) = cacheTag. "self cCode: '' inSmalltalk: [cogit disassembleFrom: callSiteReturnAddress - 20 to: callSiteReturnAddress - 1]." ^20! Item was changed: ----- Method: CogX64Compiler>>rewriteInlineCacheAt:tag:target: (in category 'inline cacheing') ----- rewriteInlineCacheAt: callSiteReturnAddress tag: cacheTag target: callTargetAddress "Rewrite an inline cache to call a different target for a new tag. This variant is used to link unlinked sends in ceSend:to:numArgs: et al. Answer the extent of the code change which is used to compute the range of the icache to flush. N.B. On 64-bit platforms the inline cache tag is only 32-bits wide, hence this code is identical to that for the IA32." <var: #callSiteReturnAddress type: #usqInt> <var: #callTargetAddress type: #usqInt> | callDistance | "self cCode: '' inSmalltalk: [cogit disassembleFrom: callSiteReturnAddress - 12 to: callSiteReturnAddress - 1]." false ifTrue: [self assert: callTargetAddress >= cogit minCallAddress] ifFalse: [callTargetAddress >= cogit minCallAddress ifFalse: [self error: 'linking callsite to invalid address']]. callDistance := (callTargetAddress - callSiteReturnAddress) signedIntToLong. objectMemory byteAt: callSiteReturnAddress - 1 put: (callDistance >> 24 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 2 put: (callDistance >> 16 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 3 put: (callDistance >> 8 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 4 put: (callDistance bitAnd: 16rFF); byteAt: callSiteReturnAddress - 6 put: (cacheTag >> 24 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 7 put: (cacheTag >> 16 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 8 put: (cacheTag >> 8 bitAnd: 16rFF); byteAt: callSiteReturnAddress - 9 put: (cacheTag bitAnd: 16rFF). + self assert: (self callTargetFromReturnAddress: callSiteReturnAddress) = callTargetAddress. - self assert: (self callTargetFromReturnAddress: callSiteReturnAddress) signedIntToLong = callTargetAddress. "self cCode: '' inSmalltalk: [cogit disassembleFrom: callSiteReturnAddress - 12 to: callSiteReturnAddress - 1]." ^12!

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VM Maker: VMMaker.oscog-eem.1603.mcz
by commits＠source.squeak.org 17 Dec '15

17 Dec '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1603.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1603 Author: eem Time: 16 December 2015, 7:09:36.295 pm UUID: 70337b05-e1e3-418f-9fcd-8a7f72c9a082 Ancestors: VMMaker.oscog-eem.1602 x64 Cogit: Fix stupidities in concretize[Call|Jump]Full (move absolute value, not value referenced by absolute address). Delete the hack in the simulator that made this mistake "work". Fix REX byte slip in concretizeMoveCwR. =============== Diff against VMMaker.oscog-eem.1602 =============== Item was changed: ----- Method: CogInLineLiteralsX64Compiler>>concretizeMoveCwR (in category 'generate machine code') ----- concretizeMoveCwR "Will get inlined into concretizeAt: switch." <inline: true> | value reg offset | value := operands at: 0. reg := self concreteRegister: (operands at: 1). (self isAnInstruction: (cogit cCoerceSimple: value to: #'AbstractInstruction *')) ifTrue: [value := (cogit cCoerceSimple: value to: #'AbstractInstruction *') address]. (cogit addressIsInCurrentCompilation: value) ifTrue: [offset := value - (address + 7). machineCode at: 0 put: (self rexR: reg x: 0 b: 0); at: 1 put: 16r8D; "LoadEffectiveAddress" at: 2 put: (self mod: ModRegInd RM: 5 RO: reg); at: 3 put: (offset bitAnd: 16rFF); at: 4 put: (offset >> 8 bitAnd: 16rFF); at: 5 put: (offset >> 16 bitAnd: 16rFF); at: 6 put: (offset >> 24 bitAnd: 16rFF). ^machineCodeSize := 7]. machineCode + at: 0 put: (self rexR: 0 x: 0 b: reg); - at: 0 put: (self rexR: reg x: 0 b: reg); at: 1 put: 16rB8 + (reg bitAnd: 7); at: 2 put: (value bitAnd: 16rFF); at: 3 put: (value >> 8 bitAnd: 16rFF); at: 4 put: (value >> 16 bitAnd: 16rFF); at: 5 put: (value >> 24 bitAnd: 16rFF); at: 6 put: (value >> 32 bitAnd: 16rFF); at: 7 put: (value >> 40 bitAnd: 16rFF); at: 8 put: (value >> 48 bitAnd: 16rFF); at: 9 put: (value >> 56 bitAnd: 16rFF). opcode = MoveCqR ifTrue: [^machineCodeSize := 10]. "Add a nop to disambiguate between MoveCwR/PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)" machineCode at: 10 put: 16r90. self assert: (self mod: ModReg RM: 0 RO: 0) > 16r90. ^machineCodeSize := 11! Item was changed: ----- Method: CogX64Compiler>>concretizeCallFull (in category 'generate machine code') ----- concretizeCallFull "Since CallFull (and JumpFull) is used to invoke code in dynamically-loaded plugins it shouldn't assume that code will be loaded within 2Gb of the code zone. Hence generate a full 64-bit call, + movabsq $0x123456789abcdef0, %rax; callq *%rax." - movabsq 0x123456789abcdef0, %rax; callq *%rax." <inline: true> | operand | operand := operands at: 0. machineCode at: 0 put: 16r48; + at: 1 put: 16rB8; - at: 1 put: 16rA1; at: 2 put: (operand bitAnd: 16rFF); at: 3 put: (operand >> 8 bitAnd: 16rFF); at: 4 put: (operand >> 16 bitAnd: 16rFF); at: 5 put: (operand >> 24 bitAnd: 16rFF); at: 6 put: (operand >> 32 bitAnd: 16rFF); at: 7 put: (operand >> 40 bitAnd: 16rFF); at: 8 put: (operand >> 48 bitAnd: 16rFF); at: 9 put: (operand >> 56 bitAnd: 16rFF); at: 10 put: 16rFF; at: 11 put: (self mod: ModReg RM: RAX RO: 2). ^machineCodeSize := 12! Item was changed: ----- Method: CogX64Compiler>>concretizeJumpFull (in category 'generate machine code') ----- concretizeJumpFull "Since JumpFull (and CallFull) is used to invoke code in dynamically-loaded plugins it shouldn't assume that code will be loaded within 2Gb of the code zone. Hence generate a full 64-bit call, movabsq 0x123456789abcdef0, %rax; jmpq *%rax." <inline: true> | operand | operand := operands at: 0. machineCode at: 0 put: 16r48; + at: 1 put: 16rB8; - at: 1 put: 16rA1; at: 2 put: (operand bitAnd: 16rFF); at: 3 put: (operand >> 8 bitAnd: 16rFF); at: 4 put: (operand >> 16 bitAnd: 16rFF); at: 5 put: (operand >> 24 bitAnd: 16rFF); at: 6 put: (operand >> 32 bitAnd: 16rFF); at: 7 put: (operand >> 40 bitAnd: 16rFF); at: 8 put: (operand >> 48 bitAnd: 16rFF); at: 9 put: (operand >> 56 bitAnd: 16rFF); at: 10 put: 16rFF; at: 11 put: (self mod: ModReg RM: RAX RO: 4). ^machineCodeSize := 12! Item was changed: ----- Method: Cogit>>handleReadSimulationTrap: (in category 'simulation only') ----- handleReadSimulationTrap: aProcessorSimulationTrap - "Try to read the value of a variable given its fake address in simulatedVariableGetters. - simulatedVariableGetters maps to an evaluable that yields the variable's actual value. - To support the x64, also gracefully accept an address which is in simulatedTrampolines, - in which case no mapping is necessary." <doNotGenerate> + | variableValue accessor | + variableValue := (simulatedVariableGetters at: aProcessorSimulationTrap address) value asInteger. - | address variableValue accessor | - address := aProcessorSimulationTrap address. - variableValue := (simulatedVariableGetters - at: address - ifAbsent: - [(simulatedTrampolines includesKey: address) - ifTrue: [address] - ifFalse: [simulatedVariableGetters errorKeyNotFound: address]]) value asInteger. accessor := aProcessorSimulationTrap registerAccessor. processor perform: accessor + with: variableValue signedIntToLong. - with: (variableValue == address - ifTrue: [address] - ifFalse: [processor convertIntegerToInternal: variableValue]). accessor ~~ #pc: ifTrue: [processor pc: aProcessorSimulationTrap nextpc]!

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Vm-dev December 2015